Patent
US 11,716,010 B2DRIVING CONTROL CIRCUIT, METHOD AND DEVICE FOR GALLIUM NITRIDE (GAN) TRANSISTOR, AND MEDIUM
Haipeng Chen
Zhuhai Ismartware Technology Co., Ltd., Zhuhai (CN)·Aug. 1, 2023·US
Copyright © 2026 Matter42. All rights reserved.
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US 11,716,010 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic view illustrating a first driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 2 is a schematic view illustrating a second driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 3 is a schematic view illustrating a third driving circuit for driving a GaN transistor in the prior art according 45 to Embodiment 1 of the present …
FIG. 4 is a schematic view illustrating partial connection of a driving control circuit according to Embodiment 1 of the present disclosure;
FIG. 5 is a schematic view illustrating overall connection 50 of a driving control circuit according to Embodiment 1 of the present disclosure;
FIG. 6 is a schematic view illustrating an output level of an ADriver pin and a Driver pin within a driving control cycle according to Embodiment 1 of the …
FIG. 7 is a schematic view illustrating an internal con- nection circuit of an ADriver pin and a Driver pin according to Embodiment 1 of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driving control circuit for a gallium nitride (GaN) transistor, comprising a flyback power supply circuit and an electronic switch, wherein the flyback power supply circuit comprises a control chip, a driving resistor, a GaN transistor and a current detection resistor; the control chip comprises a Driver pin and a current sense pin; the driving resistor comprises one terminal connected to the Driver pin, and the other terminal connected to a gate of the GaN transistor; a source of the GaN transistor is connected to the current sense pin and one terminal of the current detection resistor; and the other terminal of the current detection resistor is grounded; the control chip further comprises an ADriver pin; and the electronic switch comprises a first terminal connected to the ADriver pin, a second terminal connected between the driving resistor and the GaN transistor, and a third terminal connected between the current detec-tion resistor and the current sense pin; and during each driving control cycle of the GaN transistor, the following operation is performed: the Driver pin of the control chip outputs a high level, and the ADriver pin outputs a low level; when a voltage on the current sense pin reaches a preset limit value, the Driver pin outputs a low level, and the ADriver pin outputs the low level; after a delay of first dead time, the Driver pin outputs the low level, and the ADriver pin outputs a high level; until a first preset time is reached, the Driver pin outputs the low level, and the ADriver pin outputs the low level; and a next driving control cycle is entered after a delay of second dead time.
The driving control circuit according to claim 1, wherein there are a 6 V voltage-stabilizing output module, a Driver driving module, a dead zone generating module and an ADriver driving module in the control chip; the 6 V voltage-stabilizing output module is connected to the Driver driving module and the dead zone generating module; the Driver driving module is connected to the dead zone gen-erating module; the dead zone generating module is further connected to the ADriver driving module; the Driver driving module is connected to the Driver pin; and the ADriver driving module is connected to the ADriver pin.
The driving control circuit according to claim 1, wherein there are two operating modes for the control chip, comprising a continuous conduction mode and a discontinu-ous conduction mode; in response to the continuous con-duction mode of the control chip, the first preset time is determined according to a preset fixed time interval from start time of the driving control cycle to the first preset time, and the second dead time is determined according to the preset fixed time interval and the driving control cycle; and in response to the discontinuous conduction mode of the control chip, the first preset time is time when an amplitude of oscillation detected by a zero-current detection pin of the control chip is greater than a preset amplitude of oscillation, and the second dead time is a sum of an interval from the first preset time to time when the zero-current detection pin of the control chip detects a zero voltage and a first preset time interval.
A driving control method for a gallium nitride (GaN) transistor, comprising: performing the following operation during each driving control cycle of a GaN transistor: controlling a Driver pin of a control chip to output a high level, and an ADriver pin to output a low level; controlling, until a voltage on a current sense pin of the control chip reaches a preset limit value, the Driver pin to output a low level, and the ADriver pin to output the low level; controlling, after a delay of first dead time, the Driver pin to output the low level, and the ADriver pin to output a high level; controlling, until a first preset time is reached, the Driver pin to output the low level, and the ADriver pin to output the low level; and entering a next driving control cycle after a delay of 50 second dead time.
The driving control method according to claim 5, wherein the controlling, until a voltage on a current sense pin of the control chip reaches a preset limit value, the Driver pin to output a low level, and the ADriver pin to output the low level specifically comprises: detecting the voltage on the current sense pin of the control chip in real time; determining whether the voltage on the current sense pin reaches the preset limit value, the preset limit value being a voltage value obtained after a voltage on an FB pin of the control chip is divided in the control chip; if yes, controlling the Driver pin to output the low level, and the ADriver pin to output the low level; and if no, controlling the Driver pin of the control chip to output the high level, and the ADriver pin to output the low level.
The driving control method according to claim 5, after the controlling the Driver pin to output the low level, and the ADriver pin to output a high level, further comprising: determining an operating mode of the control chip at present; determining, if the control chip is in a continuous con-duction mode at present, the first preset time according to a preset fixed time interval from start time of the driving control cycle to the first preset time; and detecting in real time, if the control chip is in a discon-tinuous conduction mode at present, an amplitude of oscillation detected by a zero-current detection pin of the control chip, and determining whether the ampli-tude of oscillation is greater than a preset amplitude of oscillation, time when the amplitude of oscillation is greater than the preset amplitude of oscillation being the first preset time.
The driving control method according to claim 5, wherein the entering a next driving control cycle after a delay of second dead time specifically comprises: determining an operating mode of the control chip at present; determining, if the control chip is in a continuous con-duction mode at present, the second dead time accord-ing to a preset fixed time interval and the driving control cycle, and entering the next driving control cycle after the delay of the second dead time; and determining in real time, if the control chip is in a discontinuous conduction mode at present, whether a zero-current detection pin of the control chip detects a zero voltage; and entering, when the zero-current detection pin of the control chip detects the zero voltage, the next driving control cycle after a delay of a first preset time interval.
A driving control device for a gallium nitride (GaN) transistor, comprising: a processor; and a memory, storing a computer-readable program instruc-tion therein, wherein the computer-readable program instruction executes, when run by the processor, the driving control method according to claim 5.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor flyback power supply driving control circuit
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic view illustrating a first driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 4 V | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 11,716,010 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic view illustrating a first driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 2 is a schematic view illustrating a second driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 3 is a schematic view illustrating a third driving circuit for driving a GaN transistor in the prior art according 45 to Embodiment 1 of the present …
FIG. 4 is a schematic view illustrating partial connection of a driving control circuit according to Embodiment 1 of the present disclosure;
FIG. 5 is a schematic view illustrating overall connection 50 of a driving control circuit according to Embodiment 1 of the present disclosure;
FIG. 6 is a schematic view illustrating an output level of an ADriver pin and a Driver pin within a driving control cycle according to Embodiment 1 of the …
FIG. 7 is a schematic view illustrating an internal con- nection circuit of an ADriver pin and a Driver pin according to Embodiment 1 of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driving control circuit for a gallium nitride (GaN) transistor, comprising a flyback power supply circuit and an electronic switch, wherein the flyback power supply circuit comprises a control chip, a driving resistor, a GaN transistor and a current detection resistor; the control chip comprises a Driver pin and a current sense pin; the driving resistor comprises one terminal connected to the Driver pin, and the other terminal connected to a gate of the GaN transistor; a source of the GaN transistor is connected to the current sense pin and one terminal of the current detection resistor; and the other terminal of the current detection resistor is grounded; the control chip further comprises an ADriver pin; and the electronic switch comprises a first terminal connected to the ADriver pin, a second terminal connected between the driving resistor and the GaN transistor, and a third terminal connected between the current detec-tion resistor and the current sense pin; and during each driving control cycle of the GaN transistor, the following operation is performed: the Driver pin of the control chip outputs a high level, and the ADriver pin outputs a low level; when a voltage on the current sense pin reaches a preset limit value, the Driver pin outputs a low level, and the ADriver pin outputs the low level; after a delay of first dead time, the Driver pin outputs the low level, and the ADriver pin outputs a high level; until a first preset time is reached, the Driver pin outputs the low level, and the ADriver pin outputs the low level; and a next driving control cycle is entered after a delay of second dead time.
The driving control circuit according to claim 1, wherein there are a 6 V voltage-stabilizing output module, a Driver driving module, a dead zone generating module and an ADriver driving module in the control chip; the 6 V voltage-stabilizing output module is connected to the Driver driving module and the dead zone generating module; the Driver driving module is connected to the dead zone gen-erating module; the dead zone generating module is further connected to the ADriver driving module; the Driver driving module is connected to the Driver pin; and the ADriver driving module is connected to the ADriver pin.
The driving control circuit according to claim 1, wherein there are two operating modes for the control chip, comprising a continuous conduction mode and a discontinu-ous conduction mode; in response to the continuous con-duction mode of the control chip, the first preset time is determined according to a preset fixed time interval from start time of the driving control cycle to the first preset time, and the second dead time is determined according to the preset fixed time interval and the driving control cycle; and in response to the discontinuous conduction mode of the control chip, the first preset time is time when an amplitude of oscillation detected by a zero-current detection pin of the control chip is greater than a preset amplitude of oscillation, and the second dead time is a sum of an interval from the first preset time to time when the zero-current detection pin of the control chip detects a zero voltage and a first preset time interval.
A driving control method for a gallium nitride (GaN) transistor, comprising: performing the following operation during each driving control cycle of a GaN transistor: controlling a Driver pin of a control chip to output a high level, and an ADriver pin to output a low level; controlling, until a voltage on a current sense pin of the control chip reaches a preset limit value, the Driver pin to output a low level, and the ADriver pin to output the low level; controlling, after a delay of first dead time, the Driver pin to output the low level, and the ADriver pin to output a high level; controlling, until a first preset time is reached, the Driver pin to output the low level, and the ADriver pin to output the low level; and entering a next driving control cycle after a delay of 50 second dead time.
The driving control method according to claim 5, wherein the controlling, until a voltage on a current sense pin of the control chip reaches a preset limit value, the Driver pin to output a low level, and the ADriver pin to output the low level specifically comprises: detecting the voltage on the current sense pin of the control chip in real time; determining whether the voltage on the current sense pin reaches the preset limit value, the preset limit value being a voltage value obtained after a voltage on an FB pin of the control chip is divided in the control chip; if yes, controlling the Driver pin to output the low level, and the ADriver pin to output the low level; and if no, controlling the Driver pin of the control chip to output the high level, and the ADriver pin to output the low level.
The driving control method according to claim 5, after the controlling the Driver pin to output the low level, and the ADriver pin to output a high level, further comprising: determining an operating mode of the control chip at present; determining, if the control chip is in a continuous con-duction mode at present, the first preset time according to a preset fixed time interval from start time of the driving control cycle to the first preset time; and detecting in real time, if the control chip is in a discon-tinuous conduction mode at present, an amplitude of oscillation detected by a zero-current detection pin of the control chip, and determining whether the ampli-tude of oscillation is greater than a preset amplitude of oscillation, time when the amplitude of oscillation is greater than the preset amplitude of oscillation being the first preset time.
The driving control method according to claim 5, wherein the entering a next driving control cycle after a delay of second dead time specifically comprises: determining an operating mode of the control chip at present; determining, if the control chip is in a continuous con-duction mode at present, the second dead time accord-ing to a preset fixed time interval and the driving control cycle, and entering the next driving control cycle after the delay of the second dead time; and determining in real time, if the control chip is in a discontinuous conduction mode at present, whether a zero-current detection pin of the control chip detects a zero voltage; and entering, when the zero-current detection pin of the control chip detects the zero voltage, the next driving control cycle after a delay of a first preset time interval.
A driving control device for a gallium nitride (GaN) transistor, comprising: a processor; and a memory, storing a computer-readable program instruc-tion therein, wherein the computer-readable program instruction executes, when run by the processor, the driving control method according to claim 5.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor flyback power supply driving control circuit
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic view illustrating a first driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 4 V | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,716,010 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic view illustrating a first driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 2 is a schematic view illustrating a second driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 3 is a schematic view illustrating a third driving circuit for driving a GaN transistor in the prior art according 45 to Embodiment 1 of the present …
FIG. 4 is a schematic view illustrating partial connection of a driving control circuit according to Embodiment 1 of the present disclosure;
FIG. 5 is a schematic view illustrating overall connection 50 of a driving control circuit according to Embodiment 1 of the present disclosure;
FIG. 6 is a schematic view illustrating an output level of an ADriver pin and a Driver pin within a driving control cycle according to Embodiment 1 of the …
FIG. 7 is a schematic view illustrating an internal con- nection circuit of an ADriver pin and a Driver pin according to Embodiment 1 of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driving control circuit for a gallium nitride (GaN) transistor, comprising a flyback power supply circuit and an electronic switch, wherein the flyback power supply circuit comprises a control chip, a driving resistor, a GaN transistor and a current detection resistor; the control chip comprises a Driver pin and a current sense pin; the driving resistor comprises one terminal connected to the Driver pin, and the other terminal connected to a gate of the GaN transistor; a source of the GaN transistor is connected to the current sense pin and one terminal of the current detection resistor; and the other terminal of the current detection resistor is grounded; the control chip further comprises an ADriver pin; and the electronic switch comprises a first terminal connected to the ADriver pin, a second terminal connected between the driving resistor and the GaN transistor, and a third terminal connected between the current detec-tion resistor and the current sense pin; and during each driving control cycle of the GaN transistor, the following operation is performed: the Driver pin of the control chip outputs a high level, and the ADriver pin outputs a low level; when a voltage on the current sense pin reaches a preset limit value, the Driver pin outputs a low level, and the ADriver pin outputs the low level; after a delay of first dead time, the Driver pin outputs the low level, and the ADriver pin outputs a high level; until a first preset time is reached, the Driver pin outputs the low level, and the ADriver pin outputs the low level; and a next driving control cycle is entered after a delay of second dead time.
The driving control circuit according to claim 1, wherein there are a 6 V voltage-stabilizing output module, a Driver driving module, a dead zone generating module and an ADriver driving module in the control chip; the 6 V voltage-stabilizing output module is connected to the Driver driving module and the dead zone generating module; the Driver driving module is connected to the dead zone gen-erating module; the dead zone generating module is further connected to the ADriver driving module; the Driver driving module is connected to the Driver pin; and the ADriver driving module is connected to the ADriver pin.
The driving control circuit according to claim 1, wherein there are two operating modes for the control chip, comprising a continuous conduction mode and a discontinu-ous conduction mode; in response to the continuous con-duction mode of the control chip, the first preset time is determined according to a preset fixed time interval from start time of the driving control cycle to the first preset time, and the second dead time is determined according to the preset fixed time interval and the driving control cycle; and in response to the discontinuous conduction mode of the control chip, the first preset time is time when an amplitude of oscillation detected by a zero-current detection pin of the control chip is greater than a preset amplitude of oscillation, and the second dead time is a sum of an interval from the first preset time to time when the zero-current detection pin of the control chip detects a zero voltage and a first preset time interval.
A driving control method for a gallium nitride (GaN) transistor, comprising: performing the following operation during each driving control cycle of a GaN transistor: controlling a Driver pin of a control chip to output a high level, and an ADriver pin to output a low level; controlling, until a voltage on a current sense pin of the control chip reaches a preset limit value, the Driver pin to output a low level, and the ADriver pin to output the low level; controlling, after a delay of first dead time, the Driver pin to output the low level, and the ADriver pin to output a high level; controlling, until a first preset time is reached, the Driver pin to output the low level, and the ADriver pin to output the low level; and entering a next driving control cycle after a delay of 50 second dead time.
The driving control method according to claim 5, wherein the controlling, until a voltage on a current sense pin of the control chip reaches a preset limit value, the Driver pin to output a low level, and the ADriver pin to output the low level specifically comprises: detecting the voltage on the current sense pin of the control chip in real time; determining whether the voltage on the current sense pin reaches the preset limit value, the preset limit value being a voltage value obtained after a voltage on an FB pin of the control chip is divided in the control chip; if yes, controlling the Driver pin to output the low level, and the ADriver pin to output the low level; and if no, controlling the Driver pin of the control chip to output the high level, and the ADriver pin to output the low level.
The driving control method according to claim 5, after the controlling the Driver pin to output the low level, and the ADriver pin to output a high level, further comprising: determining an operating mode of the control chip at present; determining, if the control chip is in a continuous con-duction mode at present, the first preset time according to a preset fixed time interval from start time of the driving control cycle to the first preset time; and detecting in real time, if the control chip is in a discon-tinuous conduction mode at present, an amplitude of oscillation detected by a zero-current detection pin of the control chip, and determining whether the ampli-tude of oscillation is greater than a preset amplitude of oscillation, time when the amplitude of oscillation is greater than the preset amplitude of oscillation being the first preset time.
The driving control method according to claim 5, wherein the entering a next driving control cycle after a delay of second dead time specifically comprises: determining an operating mode of the control chip at present; determining, if the control chip is in a continuous con-duction mode at present, the second dead time accord-ing to a preset fixed time interval and the driving control cycle, and entering the next driving control cycle after the delay of the second dead time; and determining in real time, if the control chip is in a discontinuous conduction mode at present, whether a zero-current detection pin of the control chip detects a zero voltage; and entering, when the zero-current detection pin of the control chip detects the zero voltage, the next driving control cycle after a delay of a first preset time interval.
A driving control device for a gallium nitride (GaN) transistor, comprising: a processor; and a memory, storing a computer-readable program instruc-tion therein, wherein the computer-readable program instruction executes, when run by the processor, the driving control method according to claim 5.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor flyback power supply driving control circuit
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic view illustrating a first driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 4 V | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,716,010 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic view illustrating a first driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 2 is a schematic view illustrating a second driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 3 is a schematic view illustrating a third driving circuit for driving a GaN transistor in the prior art according 45 to Embodiment 1 of the present …
FIG. 4 is a schematic view illustrating partial connection of a driving control circuit according to Embodiment 1 of the present disclosure;
FIG. 5 is a schematic view illustrating overall connection 50 of a driving control circuit according to Embodiment 1 of the present disclosure;
FIG. 6 is a schematic view illustrating an output level of an ADriver pin and a Driver pin within a driving control cycle according to Embodiment 1 of the …
FIG. 7 is a schematic view illustrating an internal con- nection circuit of an ADriver pin and a Driver pin according to Embodiment 1 of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driving control circuit for a gallium nitride (GaN) transistor, comprising a flyback power supply circuit and an electronic switch, wherein the flyback power supply circuit comprises a control chip, a driving resistor, a GaN transistor and a current detection resistor; the control chip comprises a Driver pin and a current sense pin; the driving resistor comprises one terminal connected to the Driver pin, and the other terminal connected to a gate of the GaN transistor; a source of the GaN transistor is connected to the current sense pin and one terminal of the current detection resistor; and the other terminal of the current detection resistor is grounded; the control chip further comprises an ADriver pin; and the electronic switch comprises a first terminal connected to the ADriver pin, a second terminal connected between the driving resistor and the GaN transistor, and a third terminal connected between the current detec-tion resistor and the current sense pin; and during each driving control cycle of the GaN transistor, the following operation is performed: the Driver pin of the control chip outputs a high level, and the ADriver pin outputs a low level; when a voltage on the current sense pin reaches a preset limit value, the Driver pin outputs a low level, and the ADriver pin outputs the low level; after a delay of first dead time, the Driver pin outputs the low level, and the ADriver pin outputs a high level; until a first preset time is reached, the Driver pin outputs the low level, and the ADriver pin outputs the low level; and a next driving control cycle is entered after a delay of second dead time.
The driving control circuit according to claim 1, wherein there are a 6 V voltage-stabilizing output module, a Driver driving module, a dead zone generating module and an ADriver driving module in the control chip; the 6 V voltage-stabilizing output module is connected to the Driver driving module and the dead zone generating module; the Driver driving module is connected to the dead zone gen-erating module; the dead zone generating module is further connected to the ADriver driving module; the Driver driving module is connected to the Driver pin; and the ADriver driving module is connected to the ADriver pin.
The driving control circuit according to claim 1, wherein there are two operating modes for the control chip, comprising a continuous conduction mode and a discontinu-ous conduction mode; in response to the continuous con-duction mode of the control chip, the first preset time is determined according to a preset fixed time interval from start time of the driving control cycle to the first preset time, and the second dead time is determined according to the preset fixed time interval and the driving control cycle; and in response to the discontinuous conduction mode of the control chip, the first preset time is time when an amplitude of oscillation detected by a zero-current detection pin of the control chip is greater than a preset amplitude of oscillation, and the second dead time is a sum of an interval from the first preset time to time when the zero-current detection pin of the control chip detects a zero voltage and a first preset time interval.
A driving control method for a gallium nitride (GaN) transistor, comprising: performing the following operation during each driving control cycle of a GaN transistor: controlling a Driver pin of a control chip to output a high level, and an ADriver pin to output a low level; controlling, until a voltage on a current sense pin of the control chip reaches a preset limit value, the Driver pin to output a low level, and the ADriver pin to output the low level; controlling, after a delay of first dead time, the Driver pin to output the low level, and the ADriver pin to output a high level; controlling, until a first preset time is reached, the Driver pin to output the low level, and the ADriver pin to output the low level; and entering a next driving control cycle after a delay of 50 second dead time.
The driving control method according to claim 5, wherein the controlling, until a voltage on a current sense pin of the control chip reaches a preset limit value, the Driver pin to output a low level, and the ADriver pin to output the low level specifically comprises: detecting the voltage on the current sense pin of the control chip in real time; determining whether the voltage on the current sense pin reaches the preset limit value, the preset limit value being a voltage value obtained after a voltage on an FB pin of the control chip is divided in the control chip; if yes, controlling the Driver pin to output the low level, and the ADriver pin to output the low level; and if no, controlling the Driver pin of the control chip to output the high level, and the ADriver pin to output the low level.
The driving control method according to claim 5, after the controlling the Driver pin to output the low level, and the ADriver pin to output a high level, further comprising: determining an operating mode of the control chip at present; determining, if the control chip is in a continuous con-duction mode at present, the first preset time according to a preset fixed time interval from start time of the driving control cycle to the first preset time; and detecting in real time, if the control chip is in a discon-tinuous conduction mode at present, an amplitude of oscillation detected by a zero-current detection pin of the control chip, and determining whether the ampli-tude of oscillation is greater than a preset amplitude of oscillation, time when the amplitude of oscillation is greater than the preset amplitude of oscillation being the first preset time.
The driving control method according to claim 5, wherein the entering a next driving control cycle after a delay of second dead time specifically comprises: determining an operating mode of the control chip at present; determining, if the control chip is in a continuous con-duction mode at present, the second dead time accord-ing to a preset fixed time interval and the driving control cycle, and entering the next driving control cycle after the delay of the second dead time; and determining in real time, if the control chip is in a discontinuous conduction mode at present, whether a zero-current detection pin of the control chip detects a zero voltage; and entering, when the zero-current detection pin of the control chip detects the zero voltage, the next driving control cycle after a delay of a first preset time interval.
A driving control device for a gallium nitride (GaN) transistor, comprising: a processor; and a memory, storing a computer-readable program instruc-tion therein, wherein the computer-readable program instruction executes, when run by the processor, the driving control method according to claim 5.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor flyback power supply driving control circuit
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic view illustrating a first driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 4 V | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
FIG. 2 is a schematic view illustrating a second driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 3 is a schematic view illustrating a third driving circuit for driving a GaN transistor in the prior art according 45 to Embodiment 1 of the present …
FIG. 2 is a schematic view illustrating a second driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 3 is a schematic view illustrating a third driving circuit for driving a GaN transistor in the prior art according 45 to Embodiment 1 of the present …
FIG. 2 is a schematic view illustrating a second driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 3 is a schematic view illustrating a third driving circuit for driving a GaN transistor in the prior art according 45 to Embodiment 1 of the present …
FIG. 2 is a schematic view illustrating a second driving circuit for driving a GaN transistor in the prior art according to Embodiment 1 of the present …
FIG. 3 is a schematic view illustrating a third driving circuit for driving a GaN transistor in the prior art according 45 to Embodiment 1 of the present …