Patent
Atlas literature
Patent
US 12,080,757 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial cross-sectional view of a vertical junction field-effect transistor (JFET) device with super junction structure according to an embodiment …
FIG. 2 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 3A-3C and 3F-3N are partial cross-sectional views illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 4 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 5A through 5J are partial cross-sectional views illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 6 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 7A through 7J are partial cross-sectional views 40 illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 8 is a partial cross-sectional view of a metal-oxide- semiconductor field-effect transistor (MOSFET) device with 45 a super junction structure according to …
FIG. 9 is a simplified flowchart of a method of manufac- turing a MOSFET device with a super junction structure according to an embodiment of the present …
FIGS. 10A-10C and 10F-10P are partial cross-sectional views illustrating intermediate stages of a method of manu- facturing a MOSFET device with a super …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical metal oxide semiconductor field effect tran-sistor (MOSFET) device comprising: a III-nitride substrate having a first conductivity type; a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type, and the first III-nitride layer comprises a first plurality of first trenches; a second III-nitride structure formed within the first plurality of first trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type; a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conduc-tivity type; a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is character-ized by the first conductivity type; a second plurality of second trenches formed within the third and fourth III-nitride layers, wherein the second plurality of second trenches expose a first portion of the first III-nitride layer; a gate dielectric formed within the second plurality of second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer; a gate metal layer formed within the second plurality of second trenches, wherein the gate metal layer is coupled to the gate dielectric; and a source metal layer coupled to an upper portion of the fourth III-nitride layer.
The vertical MOSFET device of claim 1 wherein a dopant concentration of the second III-nitride structure is substantially equal to a dopant concentration of the first III-nitride layer.
The vertical MOSFET device of claim 1 wherein a depth of the first plurality of first trenches extend an entire thickness of the first III-nitride layer.
The vertical MOSFET device of claim 1 wherein sidewalls of the first plurality of first trenches are parallel to a III-nitride m-plane.
The vertical MOSFET device of claim 1 wherein sidewalls of the second plurality of second trenches are parallel to a III-nitride m-plane.
The vertical MOSFET device of claim 1 wherein the second III-nitride structure comprises an epitaxially regrown layer.
The vertical MOSFET device of claim 1 wherein the gate dielectric is conformal to a sidewall and bottom wall of each of the second plurality of second trenches.
The vertical MOSFET device of claim 1 wherein the gate dielectric comprises multiple layers of individual dielectrics.
The vertical MOSFET device of claim 1 wherein the gate metal layer comprises a refractory metal. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical super-junction MOSFET
Materials described outside the worked examples.
III-nitride substrate
second III-nitride structure (p-type epitaxially regrown)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial cross-sectional view of a vertical junction field-effect transistor (JFET) device with super junction structure according to an embodiment …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 950–1150 °C | — |
Pressure | 100–600 mTorr |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,080,757 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial cross-sectional view of a vertical junction field-effect transistor (JFET) device with super junction structure according to an embodiment …
FIG. 2 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 3A-3C and 3F-3N are partial cross-sectional views illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 4 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 5A through 5J are partial cross-sectional views illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 6 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 7A through 7J are partial cross-sectional views 40 illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 8 is a partial cross-sectional view of a metal-oxide- semiconductor field-effect transistor (MOSFET) device with 45 a super junction structure according to …
FIG. 9 is a simplified flowchart of a method of manufac- turing a MOSFET device with a super junction structure according to an embodiment of the present …
FIGS. 10A-10C and 10F-10P are partial cross-sectional views illustrating intermediate stages of a method of manu- facturing a MOSFET device with a super …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical metal oxide semiconductor field effect tran-sistor (MOSFET) device comprising: a III-nitride substrate having a first conductivity type; a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type, and the first III-nitride layer comprises a first plurality of first trenches; a second III-nitride structure formed within the first plurality of first trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type; a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conduc-tivity type; a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is character-ized by the first conductivity type; a second plurality of second trenches formed within the third and fourth III-nitride layers, wherein the second plurality of second trenches expose a first portion of the first III-nitride layer; a gate dielectric formed within the second plurality of second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer; a gate metal layer formed within the second plurality of second trenches, wherein the gate metal layer is coupled to the gate dielectric; and a source metal layer coupled to an upper portion of the fourth III-nitride layer.
The vertical MOSFET device of claim 1 wherein a dopant concentration of the second III-nitride structure is substantially equal to a dopant concentration of the first III-nitride layer.
The vertical MOSFET device of claim 1 wherein a depth of the first plurality of first trenches extend an entire thickness of the first III-nitride layer.
The vertical MOSFET device of claim 1 wherein sidewalls of the first plurality of first trenches are parallel to a III-nitride m-plane.
The vertical MOSFET device of claim 1 wherein sidewalls of the second plurality of second trenches are parallel to a III-nitride m-plane.
The vertical MOSFET device of claim 1 wherein the second III-nitride structure comprises an epitaxially regrown layer.
The vertical MOSFET device of claim 1 wherein the gate dielectric is conformal to a sidewall and bottom wall of each of the second plurality of second trenches.
The vertical MOSFET device of claim 1 wherein the gate dielectric comprises multiple layers of individual dielectrics.
The vertical MOSFET device of claim 1 wherein the gate metal layer comprises a refractory metal. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical super-junction MOSFET
Materials described outside the worked examples.
III-nitride substrate
second III-nitride structure (p-type epitaxially regrown)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial cross-sectional view of a vertical junction field-effect transistor (JFET) device with super junction structure according to an embodiment …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 950–1150 °C | — |
Pressure | 100–600 mTorr |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,080,757 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial cross-sectional view of a vertical junction field-effect transistor (JFET) device with super junction structure according to an embodiment …
FIG. 2 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 3A-3C and 3F-3N are partial cross-sectional views illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 4 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 5A through 5J are partial cross-sectional views illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 6 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 7A through 7J are partial cross-sectional views 40 illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 8 is a partial cross-sectional view of a metal-oxide- semiconductor field-effect transistor (MOSFET) device with 45 a super junction structure according to …
FIG. 9 is a simplified flowchart of a method of manufac- turing a MOSFET device with a super junction structure according to an embodiment of the present …
FIGS. 10A-10C and 10F-10P are partial cross-sectional views illustrating intermediate stages of a method of manu- facturing a MOSFET device with a super …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical metal oxide semiconductor field effect tran-sistor (MOSFET) device comprising: a III-nitride substrate having a first conductivity type; a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type, and the first III-nitride layer comprises a first plurality of first trenches; a second III-nitride structure formed within the first plurality of first trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type; a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conduc-tivity type; a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is character-ized by the first conductivity type; a second plurality of second trenches formed within the third and fourth III-nitride layers, wherein the second plurality of second trenches expose a first portion of the first III-nitride layer; a gate dielectric formed within the second plurality of second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer; a gate metal layer formed within the second plurality of second trenches, wherein the gate metal layer is coupled to the gate dielectric; and a source metal layer coupled to an upper portion of the fourth III-nitride layer.
The vertical MOSFET device of claim 1 wherein a dopant concentration of the second III-nitride structure is substantially equal to a dopant concentration of the first III-nitride layer.
The vertical MOSFET device of claim 1 wherein a depth of the first plurality of first trenches extend an entire thickness of the first III-nitride layer.
The vertical MOSFET device of claim 1 wherein sidewalls of the first plurality of first trenches are parallel to a III-nitride m-plane.
The vertical MOSFET device of claim 1 wherein sidewalls of the second plurality of second trenches are parallel to a III-nitride m-plane.
The vertical MOSFET device of claim 1 wherein the second III-nitride structure comprises an epitaxially regrown layer.
The vertical MOSFET device of claim 1 wherein the gate dielectric is conformal to a sidewall and bottom wall of each of the second plurality of second trenches.
The vertical MOSFET device of claim 1 wherein the gate dielectric comprises multiple layers of individual dielectrics.
The vertical MOSFET device of claim 1 wherein the gate metal layer comprises a refractory metal. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical super-junction MOSFET
Materials described outside the worked examples.
III-nitride substrate
second III-nitride structure (p-type epitaxially regrown)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial cross-sectional view of a vertical junction field-effect transistor (JFET) device with super junction structure according to an embodiment …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 950–1150 °C | — |
Pressure | 100–600 mTorr |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,080,757 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial cross-sectional view of a vertical junction field-effect transistor (JFET) device with super junction structure according to an embodiment …
FIG. 2 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 3A-3C and 3F-3N are partial cross-sectional views illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 4 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 5A through 5J are partial cross-sectional views illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 6 is a simplified flowchart showing a method of manufacturing a vertical JFET device with a super junction structure according to an embodiment of the …
FIGS. 7A through 7J are partial cross-sectional views 40 illustrating intermediate stages of a method of manufactur- ing a vertical JFET device with a super …
FIG. 8 is a partial cross-sectional view of a metal-oxide- semiconductor field-effect transistor (MOSFET) device with 45 a super junction structure according to …
FIG. 9 is a simplified flowchart of a method of manufac- turing a MOSFET device with a super junction structure according to an embodiment of the present …
FIGS. 10A-10C and 10F-10P are partial cross-sectional views illustrating intermediate stages of a method of manu- facturing a MOSFET device with a super …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical metal oxide semiconductor field effect tran-sistor (MOSFET) device comprising: a III-nitride substrate having a first conductivity type; a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type, and the first III-nitride layer comprises a first plurality of first trenches; a second III-nitride structure formed within the first plurality of first trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type; a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conduc-tivity type; a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is character-ized by the first conductivity type; a second plurality of second trenches formed within the third and fourth III-nitride layers, wherein the second plurality of second trenches expose a first portion of the first III-nitride layer; a gate dielectric formed within the second plurality of second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer; a gate metal layer formed within the second plurality of second trenches, wherein the gate metal layer is coupled to the gate dielectric; and a source metal layer coupled to an upper portion of the fourth III-nitride layer.
The vertical MOSFET device of claim 1 wherein a dopant concentration of the second III-nitride structure is substantially equal to a dopant concentration of the first III-nitride layer.
The vertical MOSFET device of claim 1 wherein a depth of the first plurality of first trenches extend an entire thickness of the first III-nitride layer.
The vertical MOSFET device of claim 1 wherein sidewalls of the first plurality of first trenches are parallel to a III-nitride m-plane.
The vertical MOSFET device of claim 1 wherein sidewalls of the second plurality of second trenches are parallel to a III-nitride m-plane.
The vertical MOSFET device of claim 1 wherein the second III-nitride structure comprises an epitaxially regrown layer.
The vertical MOSFET device of claim 1 wherein the gate dielectric is conformal to a sidewall and bottom wall of each of the second plurality of second trenches.
The vertical MOSFET device of claim 1 wherein the gate dielectric comprises multiple layers of individual dielectrics.
The vertical MOSFET device of claim 1 wherein the gate metal layer comprises a refractory metal. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical super-junction MOSFET
Materials described outside the worked examples.
III-nitride substrate
second III-nitride structure (p-type epitaxially regrown)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial cross-sectional view of a vertical junction field-effect transistor (JFET) device with super junction structure according to an embodiment …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 950–1150 °C | — |
Pressure | 100–600 mTorr |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
vertical super-junction JFET
first III-nitride layer
third III-nitride layer
fourth III-nitride layer
gate dielectric
gate metal layer
source metal layer
III-nitride gate layer (JFET)
III-nitride fins
FIG. 8 is a partial cross-sectional view of a metal-oxide- semiconductor field-effect transistor (MOSFET) device with 45 a super junction structure according to …
| — |
Pressure | 0.1–760 Torr | — |
Temperature | 900–1150 °C | — |
Temperature | 950–1100 °C | — |
Thickness | 300–600 nm | — |
Temperature | 900–1040 °C | — |
Thickness | 6–12 µm | — |
Thickness | 5–12 µm | — |
Temperature | 740–900 °C | — |
Thickness | 5–20 µm | — |
Thickness | 0.4–1 µm | — |
Thickness | 1.5–3 µm | — |
Thickness | 0.1–0.3 µm | — |
Thickness | 0.4–1.5 µm | — |
Thickness | 0.1–0.6 µm | — |
Thickness | 0.2–0.6 µm | — |
Thickness | 50–100 nm | — |
Thickness | 0.4–0.8 µm | — |
vertical super-junction JFET
first III-nitride layer
third III-nitride layer
fourth III-nitride layer
gate dielectric
gate metal layer
source metal layer
III-nitride gate layer (JFET)
III-nitride fins
FIG. 8 is a partial cross-sectional view of a metal-oxide- semiconductor field-effect transistor (MOSFET) device with 45 a super junction structure according to …
| — |
Pressure | 0.1–760 Torr | — |
Temperature | 900–1150 °C | — |
Temperature | 950–1100 °C | — |
Thickness | 300–600 nm | — |
Temperature | 900–1040 °C | — |
Thickness | 6–12 µm | — |
Thickness | 5–12 µm | — |
Temperature | 740–900 °C | — |
Thickness | 5–20 µm | — |
Thickness | 0.4–1 µm | — |
Thickness | 1.5–3 µm | — |
Thickness | 0.1–0.3 µm | — |
Thickness | 0.4–1.5 µm | — |
Thickness | 0.1–0.6 µm | — |
Thickness | 0.2–0.6 µm | — |
Thickness | 50–100 nm | — |
Thickness | 0.4–0.8 µm | — |
vertical super-junction JFET
first III-nitride layer
third III-nitride layer
fourth III-nitride layer
gate dielectric
gate metal layer
source metal layer
III-nitride gate layer (JFET)
III-nitride fins
FIG. 8 is a partial cross-sectional view of a metal-oxide- semiconductor field-effect transistor (MOSFET) device with 45 a super junction structure according to …
| — |
Pressure | 0.1–760 Torr | — |
Temperature | 900–1150 °C | — |
Temperature | 950–1100 °C | — |
Thickness | 300–600 nm | — |
Temperature | 900–1040 °C | — |
Thickness | 6–12 µm | — |
Thickness | 5–12 µm | — |
Temperature | 740–900 °C | — |
Thickness | 5–20 µm | — |
Thickness | 0.4–1 µm | — |
Thickness | 1.5–3 µm | — |
Thickness | 0.1–0.3 µm | — |
Thickness | 0.4–1.5 µm | — |
Thickness | 0.1–0.6 µm | — |
Thickness | 0.2–0.6 µm | — |
Thickness | 50–100 nm | — |
Thickness | 0.4–0.8 µm | — |
vertical super-junction JFET
first III-nitride layer
third III-nitride layer
fourth III-nitride layer
gate dielectric
gate metal layer
source metal layer
III-nitride gate layer (JFET)
III-nitride fins
FIG. 8 is a partial cross-sectional view of a metal-oxide- semiconductor field-effect transistor (MOSFET) device with 45 a super junction structure according to …
| — |
Pressure | 0.1–760 Torr | — |
Temperature | 900–1150 °C | — |
Temperature | 950–1100 °C | — |
Thickness | 300–600 nm | — |
Temperature | 900–1040 °C | — |
Thickness | 6–12 µm | — |
Thickness | 5–12 µm | — |
Temperature | 740–900 °C | — |
Thickness | 5–20 µm | — |
Thickness | 0.4–1 µm | — |
Thickness | 1.5–3 µm | — |
Thickness | 0.1–0.3 µm | — |
Thickness | 0.4–1.5 µm | — |
Thickness | 0.1–0.6 µm | — |
Thickness | 0.2–0.6 µm | — |
Thickness | 50–100 nm | — |
Thickness | 0.4–0.8 µm | — |
