Patent
US 10,075,085GALLIUM NITRIDE DRIVER WITH TUNED DEAD-TIME
Ziang CHEN
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 10,075,085Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example system 100 in accordance with one or more embodiments described herein. The system 100 can be, for example, a power converter …
FIG. 2 illustrates the dead-time generator 108 in accordance with one or more embodiments described herein. The dead-time generator 108 can include a dead- …
FIG. 3 presents an example first dead-time tuner, in accordance with one or more embodiments described herein; [0007]
FIG. 4 presents an example second dead-time tuner, in accordance with one or more embodiments described herein; [0008]
FIG. 5 presents a block diagram of another example power converter system, in accordance with one or more embodiments described herein; [0009]
FIG. 6 presents example timing diagrams associated a digital dead-time correction device, in accordance with one or more embodiments described herein; [0010]
FIG. 7 presents an example timing diagram associated a dead-time generator, in accordance with one or more embodiments described herein; [0011]
FIG. 8 presents an example timing diagram associated a first dead-time tuner, in accordance with one or more embodiments described herein; [0012]
FIG. 9 presents an example timing diagram associated a second dead-time tuner, in accordance with one or more embodiments described herein; [0013]
FIG. 10 presents a flow diagram of an example method for performing a tuning process, in accordance with one or more embodiments described herein; and [0014]
FIG. 11 presents a flow diagram of an example method for generating a control signal to drive a gate of a switching device, in accordance with one or more …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a dead-time generator circuit configured to generate, based on a modulated signal, a control signal for a first switching device that is coupled to a second switching device via a switching node, wherein the control signal is associated with a first dead-time value indicative of an interval of time that is added to a switching operation associated with the first switching device; a first dead-time tuner circuit configured to generate, based on the control signal and a switching signal indicative of a voltage associated with the switching node, a first modified control signal for the first switching device; a second dead-time tuner circuit configured to generate, based on a modified version of the switching signal and a tuning process that repeatedly modifies the control signal until the first dead-time value satisfies a defined criterion, a second modified control signal for the first switching device; and a digital circuit configured to combine the control signal, the first modified control signal and the second modified control signal to generate a gate-drive control signal for the first switching device, wherein the gate-drive control signal is associated with a second dead- time value that is less than the first dead-time value.
The device of claim 1, wherein the voltage is a first voltage, and wherein the first dead-time tuner circuit is configured to generate the first modified control signal based on the control signal, the switching signal and a gate signal indicative of a second voltage associated with a gate node for the second switching device.
The device of claim 1, wherein the control signal is a first control signal, wherein the first dead-time tuner circuit is further configured to generate, based on the switching signal and a second control signal for the second switching device, a third modified control signal for the second switching device, and wherein the second control signal is associated with the first dead-time value.
The device of claim 1, wherein the voltage is a first voltage, and wherein the control signal is a first control signal, wherein the first dead-time tuner circuit is further configured to generate, based on the switching signal, a second control signal for the second switching device and a gate signal indicative of a second voltage associated with a gate node for the second switching device, a third modified control signal for the second switching device, and wherein the second control signal is associated with the first dead-time value.
The device of claim 1, wherein the dead-time generator circuit is further configured to generate a flag signal that indicates a voltage state of the voltage associated with the switching node, and wherein the first dead-time tuner circuit is configured to generate the first modified control signal based on the control signal, the switching signal and the flag signal.
The device of claim 1, wherein the first switching device is a first gallium nitride (GaN) high electron mobility transistor (HEMT) and the second switching device is a second GaN HEMT.
A system, comprising: a buffer amplifier coupled to a first transistor device and a second transistor device, wherein the first transistor device is coupled to the second transistor device via a switching node; a dead-time generator configured to generate, based on a digital signal, a gate-drive signal with a first dead-time value that is indicative of a time period added to a switching operation for the first transistor device; and a dead-time tuner, wherein the dead-time tuner comprises: a first dead-time tuner configured to modify, based on a switching signal indicative of a switching voltage associated with the switching node, the gate-drive signal to generate a first modified gate-drive signal; and a second dead-time tuner configured to modify, based on a modified version of the switching signal and a tuning process that repeatedly modifies the gate-drive signal until the first dead-time value satisfies a defined criterion, the gate-drive signal to generate a second modified gate-drive signal, wherein the gate-drive signal, the first modified gate-drive signal and the second modified gate-drive signal are combined to generate a tuned gate-drive signal for the first transistor device, wherein the tuned gate-drive signal is associated with a second dead-time value that is less than the first dead-time value.
The system of claim 10, wherein the first dead-time tuner is configured to generate the first modified gate-drive signal based on the gate-drive signal, the switching signal and a gate signal indicative of a gate voltage associated with a gate node for the second transistor device.
The system of claim 10, wherein the second dead-time tuner is configured to generate the second modified gate-drive signal based on based on a time-delayed version of the gate- drive signal, the modified version of the switching signal, and the tuning process.
The system of claim 10, wherein the dead-time generator is further configured to generate a flag signal that indicates a voltage state of the switching voltage associated with the switching node, and wherein the second dead-time tuner is configured to generate the second modified gate-drive signal based on the flag signal, the modified version of the switching signal and the tuning process.
The system of claim 10, wherein the first transistor device is a first gallium nitride (GaN) transistor device and the second transistor device is a second GaN transistor device.
The system of claim 10, wherein the buffer amplifier transmits the tuned gate-drive signal to the first transistor device.
A method, comprising: generating, based on a pulse width modulation signal, a control signal for a first switching device that is coupled to a second switching device via a switching node; generating, based on the control signal and a switching signal indicative of a switching voltage associated with the switching node, a first modified control signal for the first switching device; generating a second modified control signal for the first switching device by repeatedly modifying the control signal based on a modified version of the switching signal until the control signal satisfies a defined criterion; and generating a tuned control signal for the first switching device by combining the control signal, the first modified control signal and the second modified control signal.
The method of claim 17, wherein the generating the first modified control signal comprises generating the first modified control signal based on the control signal, the switching signal and a gate signal indicative of a gate voltage associated with a gate node for the second switching device.
The method of claim 17, further comprising modifying a voltage level of the tuned control signal and transmitting the tuned control signal to the first switching device.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT dead-time corrector device
GaN transistor power converter system with tuned dead-time
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example system 100 in accordance with one or more embodiments described herein. The system 100 can be, for example, a power converter …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,075,085Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example system 100 in accordance with one or more embodiments described herein. The system 100 can be, for example, a power converter …
FIG. 2 illustrates the dead-time generator 108 in accordance with one or more embodiments described herein. The dead-time generator 108 can include a dead- …
FIG. 3 presents an example first dead-time tuner, in accordance with one or more embodiments described herein; [0007]
FIG. 4 presents an example second dead-time tuner, in accordance with one or more embodiments described herein; [0008]
FIG. 5 presents a block diagram of another example power converter system, in accordance with one or more embodiments described herein; [0009]
FIG. 6 presents example timing diagrams associated a digital dead-time correction device, in accordance with one or more embodiments described herein; [0010]
FIG. 7 presents an example timing diagram associated a dead-time generator, in accordance with one or more embodiments described herein; [0011]
FIG. 8 presents an example timing diagram associated a first dead-time tuner, in accordance with one or more embodiments described herein; [0012]
FIG. 9 presents an example timing diagram associated a second dead-time tuner, in accordance with one or more embodiments described herein; [0013]
FIG. 10 presents a flow diagram of an example method for performing a tuning process, in accordance with one or more embodiments described herein; and [0014]
FIG. 11 presents a flow diagram of an example method for generating a control signal to drive a gate of a switching device, in accordance with one or more …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a dead-time generator circuit configured to generate, based on a modulated signal, a control signal for a first switching device that is coupled to a second switching device via a switching node, wherein the control signal is associated with a first dead-time value indicative of an interval of time that is added to a switching operation associated with the first switching device; a first dead-time tuner circuit configured to generate, based on the control signal and a switching signal indicative of a voltage associated with the switching node, a first modified control signal for the first switching device; a second dead-time tuner circuit configured to generate, based on a modified version of the switching signal and a tuning process that repeatedly modifies the control signal until the first dead-time value satisfies a defined criterion, a second modified control signal for the first switching device; and a digital circuit configured to combine the control signal, the first modified control signal and the second modified control signal to generate a gate-drive control signal for the first switching device, wherein the gate-drive control signal is associated with a second dead- time value that is less than the first dead-time value.
The device of claim 1, wherein the voltage is a first voltage, and wherein the first dead-time tuner circuit is configured to generate the first modified control signal based on the control signal, the switching signal and a gate signal indicative of a second voltage associated with a gate node for the second switching device.
The device of claim 1, wherein the control signal is a first control signal, wherein the first dead-time tuner circuit is further configured to generate, based on the switching signal and a second control signal for the second switching device, a third modified control signal for the second switching device, and wherein the second control signal is associated with the first dead-time value.
The device of claim 1, wherein the voltage is a first voltage, and wherein the control signal is a first control signal, wherein the first dead-time tuner circuit is further configured to generate, based on the switching signal, a second control signal for the second switching device and a gate signal indicative of a second voltage associated with a gate node for the second switching device, a third modified control signal for the second switching device, and wherein the second control signal is associated with the first dead-time value.
The device of claim 1, wherein the dead-time generator circuit is further configured to generate a flag signal that indicates a voltage state of the voltage associated with the switching node, and wherein the first dead-time tuner circuit is configured to generate the first modified control signal based on the control signal, the switching signal and the flag signal.
The device of claim 1, wherein the first switching device is a first gallium nitride (GaN) high electron mobility transistor (HEMT) and the second switching device is a second GaN HEMT.
A system, comprising: a buffer amplifier coupled to a first transistor device and a second transistor device, wherein the first transistor device is coupled to the second transistor device via a switching node; a dead-time generator configured to generate, based on a digital signal, a gate-drive signal with a first dead-time value that is indicative of a time period added to a switching operation for the first transistor device; and a dead-time tuner, wherein the dead-time tuner comprises: a first dead-time tuner configured to modify, based on a switching signal indicative of a switching voltage associated with the switching node, the gate-drive signal to generate a first modified gate-drive signal; and a second dead-time tuner configured to modify, based on a modified version of the switching signal and a tuning process that repeatedly modifies the gate-drive signal until the first dead-time value satisfies a defined criterion, the gate-drive signal to generate a second modified gate-drive signal, wherein the gate-drive signal, the first modified gate-drive signal and the second modified gate-drive signal are combined to generate a tuned gate-drive signal for the first transistor device, wherein the tuned gate-drive signal is associated with a second dead-time value that is less than the first dead-time value.
The system of claim 10, wherein the first dead-time tuner is configured to generate the first modified gate-drive signal based on the gate-drive signal, the switching signal and a gate signal indicative of a gate voltage associated with a gate node for the second transistor device.
The system of claim 10, wherein the second dead-time tuner is configured to generate the second modified gate-drive signal based on based on a time-delayed version of the gate- drive signal, the modified version of the switching signal, and the tuning process.
The system of claim 10, wherein the dead-time generator is further configured to generate a flag signal that indicates a voltage state of the switching voltage associated with the switching node, and wherein the second dead-time tuner is configured to generate the second modified gate-drive signal based on the flag signal, the modified version of the switching signal and the tuning process.
The system of claim 10, wherein the first transistor device is a first gallium nitride (GaN) transistor device and the second transistor device is a second GaN transistor device.
The system of claim 10, wherein the buffer amplifier transmits the tuned gate-drive signal to the first transistor device.
A method, comprising: generating, based on a pulse width modulation signal, a control signal for a first switching device that is coupled to a second switching device via a switching node; generating, based on the control signal and a switching signal indicative of a switching voltage associated with the switching node, a first modified control signal for the first switching device; generating a second modified control signal for the first switching device by repeatedly modifying the control signal based on a modified version of the switching signal until the control signal satisfies a defined criterion; and generating a tuned control signal for the first switching device by combining the control signal, the first modified control signal and the second modified control signal.
The method of claim 17, wherein the generating the first modified control signal comprises generating the first modified control signal based on the control signal, the switching signal and a gate signal indicative of a gate voltage associated with a gate node for the second switching device.
The method of claim 17, further comprising modifying a voltage level of the tuned control signal and transmitting the tuned control signal to the first switching device.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT dead-time corrector device
GaN transistor power converter system with tuned dead-time
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example system 100 in accordance with one or more embodiments described herein. The system 100 can be, for example, a power converter …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,075,085Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example system 100 in accordance with one or more embodiments described herein. The system 100 can be, for example, a power converter …
FIG. 2 illustrates the dead-time generator 108 in accordance with one or more embodiments described herein. The dead-time generator 108 can include a dead- …
FIG. 3 presents an example first dead-time tuner, in accordance with one or more embodiments described herein; [0007]
FIG. 4 presents an example second dead-time tuner, in accordance with one or more embodiments described herein; [0008]
FIG. 5 presents a block diagram of another example power converter system, in accordance with one or more embodiments described herein; [0009]
FIG. 6 presents example timing diagrams associated a digital dead-time correction device, in accordance with one or more embodiments described herein; [0010]
FIG. 7 presents an example timing diagram associated a dead-time generator, in accordance with one or more embodiments described herein; [0011]
FIG. 8 presents an example timing diagram associated a first dead-time tuner, in accordance with one or more embodiments described herein; [0012]
FIG. 9 presents an example timing diagram associated a second dead-time tuner, in accordance with one or more embodiments described herein; [0013]
FIG. 10 presents a flow diagram of an example method for performing a tuning process, in accordance with one or more embodiments described herein; and [0014]
FIG. 11 presents a flow diagram of an example method for generating a control signal to drive a gate of a switching device, in accordance with one or more …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a dead-time generator circuit configured to generate, based on a modulated signal, a control signal for a first switching device that is coupled to a second switching device via a switching node, wherein the control signal is associated with a first dead-time value indicative of an interval of time that is added to a switching operation associated with the first switching device; a first dead-time tuner circuit configured to generate, based on the control signal and a switching signal indicative of a voltage associated with the switching node, a first modified control signal for the first switching device; a second dead-time tuner circuit configured to generate, based on a modified version of the switching signal and a tuning process that repeatedly modifies the control signal until the first dead-time value satisfies a defined criterion, a second modified control signal for the first switching device; and a digital circuit configured to combine the control signal, the first modified control signal and the second modified control signal to generate a gate-drive control signal for the first switching device, wherein the gate-drive control signal is associated with a second dead- time value that is less than the first dead-time value.
The device of claim 1, wherein the voltage is a first voltage, and wherein the first dead-time tuner circuit is configured to generate the first modified control signal based on the control signal, the switching signal and a gate signal indicative of a second voltage associated with a gate node for the second switching device.
The device of claim 1, wherein the control signal is a first control signal, wherein the first dead-time tuner circuit is further configured to generate, based on the switching signal and a second control signal for the second switching device, a third modified control signal for the second switching device, and wherein the second control signal is associated with the first dead-time value.
The device of claim 1, wherein the voltage is a first voltage, and wherein the control signal is a first control signal, wherein the first dead-time tuner circuit is further configured to generate, based on the switching signal, a second control signal for the second switching device and a gate signal indicative of a second voltage associated with a gate node for the second switching device, a third modified control signal for the second switching device, and wherein the second control signal is associated with the first dead-time value.
The device of claim 1, wherein the dead-time generator circuit is further configured to generate a flag signal that indicates a voltage state of the voltage associated with the switching node, and wherein the first dead-time tuner circuit is configured to generate the first modified control signal based on the control signal, the switching signal and the flag signal.
The device of claim 1, wherein the first switching device is a first gallium nitride (GaN) high electron mobility transistor (HEMT) and the second switching device is a second GaN HEMT.
A system, comprising: a buffer amplifier coupled to a first transistor device and a second transistor device, wherein the first transistor device is coupled to the second transistor device via a switching node; a dead-time generator configured to generate, based on a digital signal, a gate-drive signal with a first dead-time value that is indicative of a time period added to a switching operation for the first transistor device; and a dead-time tuner, wherein the dead-time tuner comprises: a first dead-time tuner configured to modify, based on a switching signal indicative of a switching voltage associated with the switching node, the gate-drive signal to generate a first modified gate-drive signal; and a second dead-time tuner configured to modify, based on a modified version of the switching signal and a tuning process that repeatedly modifies the gate-drive signal until the first dead-time value satisfies a defined criterion, the gate-drive signal to generate a second modified gate-drive signal, wherein the gate-drive signal, the first modified gate-drive signal and the second modified gate-drive signal are combined to generate a tuned gate-drive signal for the first transistor device, wherein the tuned gate-drive signal is associated with a second dead-time value that is less than the first dead-time value.
The system of claim 10, wherein the first dead-time tuner is configured to generate the first modified gate-drive signal based on the gate-drive signal, the switching signal and a gate signal indicative of a gate voltage associated with a gate node for the second transistor device.
The system of claim 10, wherein the second dead-time tuner is configured to generate the second modified gate-drive signal based on based on a time-delayed version of the gate- drive signal, the modified version of the switching signal, and the tuning process.
The system of claim 10, wherein the dead-time generator is further configured to generate a flag signal that indicates a voltage state of the switching voltage associated with the switching node, and wherein the second dead-time tuner is configured to generate the second modified gate-drive signal based on the flag signal, the modified version of the switching signal and the tuning process.
The system of claim 10, wherein the first transistor device is a first gallium nitride (GaN) transistor device and the second transistor device is a second GaN transistor device.
The system of claim 10, wherein the buffer amplifier transmits the tuned gate-drive signal to the first transistor device.
A method, comprising: generating, based on a pulse width modulation signal, a control signal for a first switching device that is coupled to a second switching device via a switching node; generating, based on the control signal and a switching signal indicative of a switching voltage associated with the switching node, a first modified control signal for the first switching device; generating a second modified control signal for the first switching device by repeatedly modifying the control signal based on a modified version of the switching signal until the control signal satisfies a defined criterion; and generating a tuned control signal for the first switching device by combining the control signal, the first modified control signal and the second modified control signal.
The method of claim 17, wherein the generating the first modified control signal comprises generating the first modified control signal based on the control signal, the switching signal and a gate signal indicative of a gate voltage associated with a gate node for the second switching device.
The method of claim 17, further comprising modifying a voltage level of the tuned control signal and transmitting the tuned control signal to the first switching device.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT dead-time corrector device
GaN transistor power converter system with tuned dead-time
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example system 100 in accordance with one or more embodiments described herein. The system 100 can be, for example, a power converter …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,075,085Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example system 100 in accordance with one or more embodiments described herein. The system 100 can be, for example, a power converter …
FIG. 2 illustrates the dead-time generator 108 in accordance with one or more embodiments described herein. The dead-time generator 108 can include a dead- …
FIG. 3 presents an example first dead-time tuner, in accordance with one or more embodiments described herein; [0007]
FIG. 4 presents an example second dead-time tuner, in accordance with one or more embodiments described herein; [0008]
FIG. 5 presents a block diagram of another example power converter system, in accordance with one or more embodiments described herein; [0009]
FIG. 6 presents example timing diagrams associated a digital dead-time correction device, in accordance with one or more embodiments described herein; [0010]
FIG. 7 presents an example timing diagram associated a dead-time generator, in accordance with one or more embodiments described herein; [0011]
FIG. 8 presents an example timing diagram associated a first dead-time tuner, in accordance with one or more embodiments described herein; [0012]
FIG. 9 presents an example timing diagram associated a second dead-time tuner, in accordance with one or more embodiments described herein; [0013]
FIG. 10 presents a flow diagram of an example method for performing a tuning process, in accordance with one or more embodiments described herein; and [0014]
FIG. 11 presents a flow diagram of an example method for generating a control signal to drive a gate of a switching device, in accordance with one or more …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a dead-time generator circuit configured to generate, based on a modulated signal, a control signal for a first switching device that is coupled to a second switching device via a switching node, wherein the control signal is associated with a first dead-time value indicative of an interval of time that is added to a switching operation associated with the first switching device; a first dead-time tuner circuit configured to generate, based on the control signal and a switching signal indicative of a voltage associated with the switching node, a first modified control signal for the first switching device; a second dead-time tuner circuit configured to generate, based on a modified version of the switching signal and a tuning process that repeatedly modifies the control signal until the first dead-time value satisfies a defined criterion, a second modified control signal for the first switching device; and a digital circuit configured to combine the control signal, the first modified control signal and the second modified control signal to generate a gate-drive control signal for the first switching device, wherein the gate-drive control signal is associated with a second dead- time value that is less than the first dead-time value.
The device of claim 1, wherein the voltage is a first voltage, and wherein the first dead-time tuner circuit is configured to generate the first modified control signal based on the control signal, the switching signal and a gate signal indicative of a second voltage associated with a gate node for the second switching device.
The device of claim 1, wherein the control signal is a first control signal, wherein the first dead-time tuner circuit is further configured to generate, based on the switching signal and a second control signal for the second switching device, a third modified control signal for the second switching device, and wherein the second control signal is associated with the first dead-time value.
The device of claim 1, wherein the voltage is a first voltage, and wherein the control signal is a first control signal, wherein the first dead-time tuner circuit is further configured to generate, based on the switching signal, a second control signal for the second switching device and a gate signal indicative of a second voltage associated with a gate node for the second switching device, a third modified control signal for the second switching device, and wherein the second control signal is associated with the first dead-time value.
The device of claim 1, wherein the dead-time generator circuit is further configured to generate a flag signal that indicates a voltage state of the voltage associated with the switching node, and wherein the first dead-time tuner circuit is configured to generate the first modified control signal based on the control signal, the switching signal and the flag signal.
The device of claim 1, wherein the first switching device is a first gallium nitride (GaN) high electron mobility transistor (HEMT) and the second switching device is a second GaN HEMT.
A system, comprising: a buffer amplifier coupled to a first transistor device and a second transistor device, wherein the first transistor device is coupled to the second transistor device via a switching node; a dead-time generator configured to generate, based on a digital signal, a gate-drive signal with a first dead-time value that is indicative of a time period added to a switching operation for the first transistor device; and a dead-time tuner, wherein the dead-time tuner comprises: a first dead-time tuner configured to modify, based on a switching signal indicative of a switching voltage associated with the switching node, the gate-drive signal to generate a first modified gate-drive signal; and a second dead-time tuner configured to modify, based on a modified version of the switching signal and a tuning process that repeatedly modifies the gate-drive signal until the first dead-time value satisfies a defined criterion, the gate-drive signal to generate a second modified gate-drive signal, wherein the gate-drive signal, the first modified gate-drive signal and the second modified gate-drive signal are combined to generate a tuned gate-drive signal for the first transistor device, wherein the tuned gate-drive signal is associated with a second dead-time value that is less than the first dead-time value.
The system of claim 10, wherein the first dead-time tuner is configured to generate the first modified gate-drive signal based on the gate-drive signal, the switching signal and a gate signal indicative of a gate voltage associated with a gate node for the second transistor device.
The system of claim 10, wherein the second dead-time tuner is configured to generate the second modified gate-drive signal based on based on a time-delayed version of the gate- drive signal, the modified version of the switching signal, and the tuning process.
The system of claim 10, wherein the dead-time generator is further configured to generate a flag signal that indicates a voltage state of the switching voltage associated with the switching node, and wherein the second dead-time tuner is configured to generate the second modified gate-drive signal based on the flag signal, the modified version of the switching signal and the tuning process.
The system of claim 10, wherein the first transistor device is a first gallium nitride (GaN) transistor device and the second transistor device is a second GaN transistor device.
The system of claim 10, wherein the buffer amplifier transmits the tuned gate-drive signal to the first transistor device.
A method, comprising: generating, based on a pulse width modulation signal, a control signal for a first switching device that is coupled to a second switching device via a switching node; generating, based on the control signal and a switching signal indicative of a switching voltage associated with the switching node, a first modified control signal for the first switching device; generating a second modified control signal for the first switching device by repeatedly modifying the control signal based on a modified version of the switching signal until the control signal satisfies a defined criterion; and generating a tuned control signal for the first switching device by combining the control signal, the first modified control signal and the second modified control signal.
The method of claim 17, wherein the generating the first modified control signal comprises generating the first modified control signal based on the control signal, the switching signal and a gate signal indicative of a gate voltage associated with a gate node for the second switching device.
The method of claim 17, further comprising modifying a voltage level of the tuned control signal and transmitting the tuned control signal to the first switching device.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT dead-time corrector device
GaN transistor power converter system with tuned dead-time
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example system 100 in accordance with one or more embodiments described herein. The system 100 can be, for example, a power converter …
Related documents with shared materials, methods, properties, or citations.