Patent
US 12,463,638 B2DRIVER CIRCUIT FOR GAN FET SOLID STATE RELAY
Michael A. de Rooij
Efficient Power Conversion Corporation, El Segundo, CA (US)·Nov. 4, 2025·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 12,463,638 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 is a circuit diagram showing details of certain circuitry of
FIG. 3 is a circuit diagram of the drive circuit for the solid-state relay of the present invention.
FIG. 4 is a waveform diagram showing the power FET conducting current.
FIG. 5 is a block diagram of the single gate driver of the present invention capable of AC operation.
FIG. 6.
FIG. 7 is a circuit diagram of the driver circuit of
FIG. 8 is a circuit diagram of a cascaded embodiment of the driver circuit of
FIG. 9 is a circuit diagram of a cascaded embodiment of the driver circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit for a solid state relay, comprising: a main FET; a depletion mode control transistor; and a split power supply, wherein a positive supply of the split power supply provides a positive voltage applied to a gate of the main FET for supplying power to a load, and a negative supply of the split power supply provides a negative voltage for turning off the depletion mode control transistor, wherein the control transistor prevents the main FET from conducting power to the load when the driver circuit is turned off, wherein the driver circuit further comprises a first capaci-tor, a second capacitor, a first diode, and a second diode, wherein the first diode is configured to positively charge the first capacitor in response to the positive voltage, and the second diode is configured to nega-tively charge the second capacitor, which turns off the depletion mode control transistor.
The driver circuit of claim 1, wherein the FET is a MOSFET.
The driver circuit of claim 1, wherein the FET is a GaN FET.
The driver circuit of claim 1, wherein the control transistor is a JFET.
The driver circuit of claim 1, wherein the control transistor is a depletion mode GaN FET.
The driver circuit of claim 1, wherein the FET com-prises a dual back-to-back FET.
The driver circuit of claim 1, wherein the FET com-prises a bidirectional FET.
The driver circuit of claim 1, wherein the driver circuit initiates the negative side first, prioritizing the turn off of the control transistor, thereby reducing turn-on current.
The driver circuit of claim 1, further comprising circuitry for controlling turn off in the event the FET switches an inductive load, wherein drain voltage is har-vested to turn the FET on to dissipate the inductive energy.
A driver circuit for a solid state relay, comprising a plurality of driver circuits as recited in claim 1 driven by a single oscillator circuit, wherein the FETs of each of the driver circuits are connected in series.
The driver circuit of claim 1, wherein said split power supply comprises a transformer having a split voltage con-figured to provide the voltage and the negative voltage.
The driver circuit of claim 1, wherein the control transistor ensures that the FET is off even absent any power at the split power supply.
The driver circuit of claim 1, wherein the voltage turns on the gate of the FET.
The driver circuit of claim 1, wherein the control transistor when on is configured to short circuit the voltage, and the negative voltage turns off the control transistor to remove any short circuit of the voltage and allow the voltage to turn on the FET.
The driver circuit of claim 1, wherein the control transistor when on is configured to provide a low impedance at the gate of the main FET, and the negative voltage turns off the control transistor to remove any low impedance at the gate of the main FET and allow the voltage to turn on the FET.
The driver circuit of claim 1, wherein the control transistor turns off the main FET, thereby eliminating the need for the negative voltage to be applied to the gate of the main FET to turn off the main FET.
The driver circuit of claim 1, wherein the negative voltage precedes the voltage.
The driver circuit of claim 1, wherein the first diode is parallel with the second diode, and the first capacitor is in series with the second capacitor between the first and second diodes. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
driver circuit for solid state relay with main FET and depletion mode control transistor
No layer stack recorded.
driver circuit for solid state relay with MOSFET as main FET
No layer stack recorded.
driver circuit for solid state relay with GaN FET as main FET
No layer stack recorded.
driver circuit for solid state relay with JFET as control transistor
No layer stack recorded.
driver circuit for solid state relay with depletion mode GaN FET as control transistor
No layer stack recorded.
driver circuit for solid state relay with dual back-to-back FET
No layer stack recorded.
driver circuit for solid state relay with bidirectional FET
No layer stack recorded.
cascaded driver circuit for solid state relay with series-connected FETs driven by single oscillator
No layer stack recorded.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a waveform diagram showing the power FET conducting current.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,463,638 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 is a circuit diagram showing details of certain circuitry of
FIG. 3 is a circuit diagram of the drive circuit for the solid-state relay of the present invention.
FIG. 4 is a waveform diagram showing the power FET conducting current.
FIG. 5 is a block diagram of the single gate driver of the present invention capable of AC operation.
FIG. 6.
FIG. 7 is a circuit diagram of the driver circuit of
FIG. 8 is a circuit diagram of a cascaded embodiment of the driver circuit of
FIG. 9 is a circuit diagram of a cascaded embodiment of the driver circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit for a solid state relay, comprising: a main FET; a depletion mode control transistor; and a split power supply, wherein a positive supply of the split power supply provides a positive voltage applied to a gate of the main FET for supplying power to a load, and a negative supply of the split power supply provides a negative voltage for turning off the depletion mode control transistor, wherein the control transistor prevents the main FET from conducting power to the load when the driver circuit is turned off, wherein the driver circuit further comprises a first capaci-tor, a second capacitor, a first diode, and a second diode, wherein the first diode is configured to positively charge the first capacitor in response to the positive voltage, and the second diode is configured to nega-tively charge the second capacitor, which turns off the depletion mode control transistor.
The driver circuit of claim 1, wherein the FET is a MOSFET.
The driver circuit of claim 1, wherein the FET is a GaN FET.
The driver circuit of claim 1, wherein the control transistor is a JFET.
The driver circuit of claim 1, wherein the control transistor is a depletion mode GaN FET.
The driver circuit of claim 1, wherein the FET com-prises a dual back-to-back FET.
The driver circuit of claim 1, wherein the FET com-prises a bidirectional FET.
The driver circuit of claim 1, wherein the driver circuit initiates the negative side first, prioritizing the turn off of the control transistor, thereby reducing turn-on current.
The driver circuit of claim 1, further comprising circuitry for controlling turn off in the event the FET switches an inductive load, wherein drain voltage is har-vested to turn the FET on to dissipate the inductive energy.
A driver circuit for a solid state relay, comprising a plurality of driver circuits as recited in claim 1 driven by a single oscillator circuit, wherein the FETs of each of the driver circuits are connected in series.
The driver circuit of claim 1, wherein said split power supply comprises a transformer having a split voltage con-figured to provide the voltage and the negative voltage.
The driver circuit of claim 1, wherein the control transistor ensures that the FET is off even absent any power at the split power supply.
The driver circuit of claim 1, wherein the voltage turns on the gate of the FET.
The driver circuit of claim 1, wherein the control transistor when on is configured to short circuit the voltage, and the negative voltage turns off the control transistor to remove any short circuit of the voltage and allow the voltage to turn on the FET.
The driver circuit of claim 1, wherein the control transistor when on is configured to provide a low impedance at the gate of the main FET, and the negative voltage turns off the control transistor to remove any low impedance at the gate of the main FET and allow the voltage to turn on the FET.
The driver circuit of claim 1, wherein the control transistor turns off the main FET, thereby eliminating the need for the negative voltage to be applied to the gate of the main FET to turn off the main FET.
The driver circuit of claim 1, wherein the negative voltage precedes the voltage.
The driver circuit of claim 1, wherein the first diode is parallel with the second diode, and the first capacitor is in series with the second capacitor between the first and second diodes. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
driver circuit for solid state relay with main FET and depletion mode control transistor
No layer stack recorded.
driver circuit for solid state relay with MOSFET as main FET
No layer stack recorded.
driver circuit for solid state relay with GaN FET as main FET
No layer stack recorded.
driver circuit for solid state relay with JFET as control transistor
No layer stack recorded.
driver circuit for solid state relay with depletion mode GaN FET as control transistor
No layer stack recorded.
driver circuit for solid state relay with dual back-to-back FET
No layer stack recorded.
driver circuit for solid state relay with bidirectional FET
No layer stack recorded.
cascaded driver circuit for solid state relay with series-connected FETs driven by single oscillator
No layer stack recorded.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a waveform diagram showing the power FET conducting current.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,463,638 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 is a circuit diagram showing details of certain circuitry of
FIG. 3 is a circuit diagram of the drive circuit for the solid-state relay of the present invention.
FIG. 4 is a waveform diagram showing the power FET conducting current.
FIG. 5 is a block diagram of the single gate driver of the present invention capable of AC operation.
FIG. 6.
FIG. 7 is a circuit diagram of the driver circuit of
FIG. 8 is a circuit diagram of a cascaded embodiment of the driver circuit of
FIG. 9 is a circuit diagram of a cascaded embodiment of the driver circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit for a solid state relay, comprising: a main FET; a depletion mode control transistor; and a split power supply, wherein a positive supply of the split power supply provides a positive voltage applied to a gate of the main FET for supplying power to a load, and a negative supply of the split power supply provides a negative voltage for turning off the depletion mode control transistor, wherein the control transistor prevents the main FET from conducting power to the load when the driver circuit is turned off, wherein the driver circuit further comprises a first capaci-tor, a second capacitor, a first diode, and a second diode, wherein the first diode is configured to positively charge the first capacitor in response to the positive voltage, and the second diode is configured to nega-tively charge the second capacitor, which turns off the depletion mode control transistor.
The driver circuit of claim 1, wherein the FET is a MOSFET.
The driver circuit of claim 1, wherein the FET is a GaN FET.
The driver circuit of claim 1, wherein the control transistor is a JFET.
The driver circuit of claim 1, wherein the control transistor is a depletion mode GaN FET.
The driver circuit of claim 1, wherein the FET com-prises a dual back-to-back FET.
The driver circuit of claim 1, wherein the FET com-prises a bidirectional FET.
The driver circuit of claim 1, wherein the driver circuit initiates the negative side first, prioritizing the turn off of the control transistor, thereby reducing turn-on current.
The driver circuit of claim 1, further comprising circuitry for controlling turn off in the event the FET switches an inductive load, wherein drain voltage is har-vested to turn the FET on to dissipate the inductive energy.
A driver circuit for a solid state relay, comprising a plurality of driver circuits as recited in claim 1 driven by a single oscillator circuit, wherein the FETs of each of the driver circuits are connected in series.
The driver circuit of claim 1, wherein said split power supply comprises a transformer having a split voltage con-figured to provide the voltage and the negative voltage.
The driver circuit of claim 1, wherein the control transistor ensures that the FET is off even absent any power at the split power supply.
The driver circuit of claim 1, wherein the voltage turns on the gate of the FET.
The driver circuit of claim 1, wherein the control transistor when on is configured to short circuit the voltage, and the negative voltage turns off the control transistor to remove any short circuit of the voltage and allow the voltage to turn on the FET.
The driver circuit of claim 1, wherein the control transistor when on is configured to provide a low impedance at the gate of the main FET, and the negative voltage turns off the control transistor to remove any low impedance at the gate of the main FET and allow the voltage to turn on the FET.
The driver circuit of claim 1, wherein the control transistor turns off the main FET, thereby eliminating the need for the negative voltage to be applied to the gate of the main FET to turn off the main FET.
The driver circuit of claim 1, wherein the negative voltage precedes the voltage.
The driver circuit of claim 1, wherein the first diode is parallel with the second diode, and the first capacitor is in series with the second capacitor between the first and second diodes. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
driver circuit for solid state relay with main FET and depletion mode control transistor
No layer stack recorded.
driver circuit for solid state relay with MOSFET as main FET
No layer stack recorded.
driver circuit for solid state relay with GaN FET as main FET
No layer stack recorded.
driver circuit for solid state relay with JFET as control transistor
No layer stack recorded.
driver circuit for solid state relay with depletion mode GaN FET as control transistor
No layer stack recorded.
driver circuit for solid state relay with dual back-to-back FET
No layer stack recorded.
driver circuit for solid state relay with bidirectional FET
No layer stack recorded.
cascaded driver circuit for solid state relay with series-connected FETs driven by single oscillator
No layer stack recorded.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a waveform diagram showing the power FET conducting current.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,463,638 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 is a circuit diagram showing details of certain circuitry of
FIG. 3 is a circuit diagram of the drive circuit for the solid-state relay of the present invention.
FIG. 4 is a waveform diagram showing the power FET conducting current.
FIG. 5 is a block diagram of the single gate driver of the present invention capable of AC operation.
FIG. 6.
FIG. 7 is a circuit diagram of the driver circuit of
FIG. 8 is a circuit diagram of a cascaded embodiment of the driver circuit of
FIG. 9 is a circuit diagram of a cascaded embodiment of the driver circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit for a solid state relay, comprising: a main FET; a depletion mode control transistor; and a split power supply, wherein a positive supply of the split power supply provides a positive voltage applied to a gate of the main FET for supplying power to a load, and a negative supply of the split power supply provides a negative voltage for turning off the depletion mode control transistor, wherein the control transistor prevents the main FET from conducting power to the load when the driver circuit is turned off, wherein the driver circuit further comprises a first capaci-tor, a second capacitor, a first diode, and a second diode, wherein the first diode is configured to positively charge the first capacitor in response to the positive voltage, and the second diode is configured to nega-tively charge the second capacitor, which turns off the depletion mode control transistor.
The driver circuit of claim 1, wherein the FET is a MOSFET.
The driver circuit of claim 1, wherein the FET is a GaN FET.
The driver circuit of claim 1, wherein the control transistor is a JFET.
The driver circuit of claim 1, wherein the control transistor is a depletion mode GaN FET.
The driver circuit of claim 1, wherein the FET com-prises a dual back-to-back FET.
The driver circuit of claim 1, wherein the FET com-prises a bidirectional FET.
The driver circuit of claim 1, wherein the driver circuit initiates the negative side first, prioritizing the turn off of the control transistor, thereby reducing turn-on current.
The driver circuit of claim 1, further comprising circuitry for controlling turn off in the event the FET switches an inductive load, wherein drain voltage is har-vested to turn the FET on to dissipate the inductive energy.
A driver circuit for a solid state relay, comprising a plurality of driver circuits as recited in claim 1 driven by a single oscillator circuit, wherein the FETs of each of the driver circuits are connected in series.
The driver circuit of claim 1, wherein said split power supply comprises a transformer having a split voltage con-figured to provide the voltage and the negative voltage.
The driver circuit of claim 1, wherein the control transistor ensures that the FET is off even absent any power at the split power supply.
The driver circuit of claim 1, wherein the voltage turns on the gate of the FET.
The driver circuit of claim 1, wherein the control transistor when on is configured to short circuit the voltage, and the negative voltage turns off the control transistor to remove any short circuit of the voltage and allow the voltage to turn on the FET.
The driver circuit of claim 1, wherein the control transistor when on is configured to provide a low impedance at the gate of the main FET, and the negative voltage turns off the control transistor to remove any low impedance at the gate of the main FET and allow the voltage to turn on the FET.
The driver circuit of claim 1, wherein the control transistor turns off the main FET, thereby eliminating the need for the negative voltage to be applied to the gate of the main FET to turn off the main FET.
The driver circuit of claim 1, wherein the negative voltage precedes the voltage.
The driver circuit of claim 1, wherein the first diode is parallel with the second diode, and the first capacitor is in series with the second capacitor between the first and second diodes. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
driver circuit for solid state relay with main FET and depletion mode control transistor
No layer stack recorded.
driver circuit for solid state relay with MOSFET as main FET
No layer stack recorded.
driver circuit for solid state relay with GaN FET as main FET
No layer stack recorded.
driver circuit for solid state relay with JFET as control transistor
No layer stack recorded.
driver circuit for solid state relay with depletion mode GaN FET as control transistor
No layer stack recorded.
driver circuit for solid state relay with dual back-to-back FET
No layer stack recorded.
driver circuit for solid state relay with bidirectional FET
No layer stack recorded.
cascaded driver circuit for solid state relay with series-connected FETs driven by single oscillator
No layer stack recorded.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a waveform diagram showing the power FET conducting current.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Related documents with shared materials, methods, properties, or citations.
GaN FET solid state relay driver circuit (preferred embodiment, FIG. 3)
No layer stack recorded.
bidirectional GaN FET solid state relay driver circuit with overvoltage protection (FIG. 5/6)
No layer stack recorded.
dual back-to-back GaN FET solid state relay driver circuit with overvoltage protection (FIG. 7)
No layer stack recorded.
FIG. 5 is a block diagram of the single gate driver of the present invention capable of AC operation.
Cited non-patent literature · 1
GaN FET solid state relay driver circuit (preferred embodiment, FIG. 3)
No layer stack recorded.
bidirectional GaN FET solid state relay driver circuit with overvoltage protection (FIG. 5/6)
No layer stack recorded.
dual back-to-back GaN FET solid state relay driver circuit with overvoltage protection (FIG. 7)
No layer stack recorded.
FIG. 5 is a block diagram of the single gate driver of the present invention capable of AC operation.
Cited non-patent literature · 1
GaN FET solid state relay driver circuit (preferred embodiment, FIG. 3)
No layer stack recorded.
bidirectional GaN FET solid state relay driver circuit with overvoltage protection (FIG. 5/6)
No layer stack recorded.
dual back-to-back GaN FET solid state relay driver circuit with overvoltage protection (FIG. 7)
No layer stack recorded.
FIG. 5 is a block diagram of the single gate driver of the present invention capable of AC operation.
Cited non-patent literature · 1
GaN FET solid state relay driver circuit (preferred embodiment, FIG. 3)
No layer stack recorded.
bidirectional GaN FET solid state relay driver circuit with overvoltage protection (FIG. 5/6)
No layer stack recorded.
dual back-to-back GaN FET solid state relay driver circuit with overvoltage protection (FIG. 7)
No layer stack recorded.
FIG. 5 is a block diagram of the single gate driver of the present invention capable of AC operation.
Cited non-patent literature · 1