Patent
US 11,227,805SYSTEM AND METHOD FOR SURGE-TESTING A GALLIUM NITRIDE TRANSISTOR DEVICE
SANDEEP RAJ BAHL
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,227,805Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example of test system. [0009]
FIG. 2 illustrates an example timing diagram of a surge-strike. [0010]
FIG. 3 illustrates an example of a power supply circuit card. [0011]
FIG. 4 illustrates an example state diagram of a calibration procedure. [0012]
FIG. 5 illustrates an example timing diagram of measurement times of the test system. [0013]
FIG. 6 illustrates an example diagram of a calibration voltage graph. [0014]
FIG. 7 illustrates an example diagram of a calibration inductance graph. [0015]
FIG. 8 illustrates an example diagram of parameter measurement in response to a surge-strike. [0016]
FIG. 9 illustrates an example state diagram of a surge test. [0017]
FIG. 10 illustrates an example of surge testing and margin testing of a GaN transistor DUT. [0018]
FIG. 11 illustrates an example of a diagram of a method for fabricating GaN transistor devices.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for surge-testing a gallium nitride (GaN) transistor device-under-test (DUT), the method comprising: coupling the GaN transistor DUT to a test fixture that includes an inductor that is coupled to the GaN transistor DUT to form a switching power regulator; operating the switching power regulator to provide an output current through the inductor in response to a DUT input voltage and a duty-cycle; controlling an excitation voltage source to provide a voltage surge-strike to the GaN transistor DUT; measuring the output current and the DUT input voltage after the voltage surge-strike; and storing the measured output current and the measured DUT input voltage in a memory. Currently amended
The method of claim 1, further comprising calibrating the test fixture using a calibration GaN transistor device prior to coupling the GaN transistor DUT to the test fixture. Currently amended
The method of claim 1, further comprising measuring the output current and the DUT input voltage at a time prior to the voltage surge-strike, and storing the measured output current and the measured DUT input voltage prior to and subsequent to the voltage surge-strike. Currently amended
The method of claim 1, further comprising: measuring a temperature of the G aN transistor DUT in response to the voltage surge-strike; and controlling a temperature element to maintain a defined temperature of the G aN transistor DUT responsive to the measured temperature. Currently amended
The method of claim 1, wherein controlling the excitation voltage source comprises controlling the excitation voltage source to provide a number of voltage surge strikes to the G aN transistor DUT over a time interval, and wherein measuring the output current and the DUT input voltage comprises measuring the output current and the DUT input voltage after each of the number of voltage surge strikes. Currently amended
The method of claim 1, wherein coupling the G aN transistor DUT to the test fixture includes inserting, into the test fixture, a GaN transistor power supply circuit card that includes the GaN transistor DUT. Currently amended
The method of claim 1, wherein: coupling the GaN transistor DUT to the test fixture includes inserting a first GaN transistor DUT and a second GaN transistor DUT into the test fixture, wherein the first and second GaN transistor DUTs are configured to provide high-side switching and low-side switching, respectively, for the switching power regulator, controlling the excitation voltage source comprises controlling the excitation voltage source to provide the voltage surge-strike to the first and second GaN transistor DUTs, and storing the measured output current and the measured input voltage comprises storing the measured output current and the measured DUT input voltage in the memory. Currently amended
The method of claim 1, further comprising: measuring an input current associated with the GaN transistor DUT and an output voltage associated with the switching power regulator before and during the voltage surge-strike; and storing the measured input current and the measured output voltage in the memory. Currently amended
The method of claim 1, further comprising: fabricating the GaN transistor DUT; measuring a device characteristic of the fabricated GaN transistor DUT; comparing the measured device characteristic of the GaN transistor DUT with a specification; and fabricating a plurality of GaN transistor devices in response to determining that the device characteristic is within the SVG 16656363.08-13-2021.KSAVIVJCLDFLYX9.CLM.1.svg 0.16 5.59 Black and white Currently amended
(Withdrawn Amended) A test system for testing a gallium nitride (GaN) transistor device-under-test (DUT), the system comprising: a test fixture comprising an inductor, a load, and electrical connectors configured to couple to the GaN transistor DUT, wherein the GaN transistor DUT, the load, and the inductor form a switching power regulator when the GaN transistor DUT is coupled to at least one of the electrical connectors; an excitation voltage source coupled to the GaN transistor DUT, and configured to provide a DUT input voltage to the GaN transistor DUT, the switching power regulator providing an output current through the inductor in response to en the DUT input voltage and a duty-cycle, the excitation voltage source being further configured to provide a voltage surge-strike to the GaN transistor DUT; a test controller configured to measure the output current and the DUT input voltage in response to the voltage surge-strike; and a memory configured to store the measured output current and the measured DUT input voltage. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the test controller is further configured to measure an input current and an output voltage associated with the GaN transistor DUT after the voltage surge-strike, and store the measured input current and the measured output voltage in the memory. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the excitation voltage source is configured to provide a number of voltage surge strikes to the GaN transistor DUT, and wherein the test controller is configured to measure the output current and the DUT input voltage in response to each of the voltage surge strikes. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the test controller is configured to _ determine if the measured output current and the measured DUT input voltage are within a range of specifications defined by calibration values associated with the output current and the DUT input voltage., change a voltage surge-strike set point in response to the measured DUT input voltage being outside of the range of specifications; and, change an amplitude of an inductance of the inductor in response to the measured output current being outside of the range of specifications. Currently amended
(Withdrawn Amended) A power supply circuit comprising: a gallium nitride (GaN) transistor device; a first set of electrical connectors adapted to be coupled to respective connectors of a surge-test fixture, and configured to communicate electrical signals to the surge-test fixture for performing surge-testing of the G aN transistor device by the surge-test fixture; and a second set of electrical connectors adapted to be coupled to respective connectors of a parametric-test fixture, and configured to communicate electrical signals to the parametric-test fixture for performing device-relevant parametric characteristic testing of the G aN transistor device by the parametric-test fixture. Currently amended
(Withdrawn Amended) The power supply circuit of claim 20, wherein the characteristics being tested comprise at least one of threshold voltage, on-resistance, and terminal leakage currents associated with the GaN transistor device. Currently amended
(Withdrawn Amended) The power supply circuit of claim 20, wherein the first set of electrical connectors are electrically coupled to the G aN transistor device to enable measurement of input voltage, output voltage, input current, and output current of the G aN transistor device during the surge-testing of the GaN transistor device. Currently amended
(Withdrawn Amended) A method comprising: fabricating a G aN transistor device-under-test (DUT) based on at least one fabrication parameter; surge-testing the G aN transistor DUT comprising: coupling the G aN transistor DUT to a test fixture that includes an inductor coupled to the G aN transistor DUT to form a switching power regulator; operating the switching power regulator at a DUT operating voltage to provide an output current through the inductor responsive to a DUT input voltage and a duty-cycle; controlling an excitation voltage source to provide a voltage surge-strike to the G aN transistor DUT; measuring the output current and the DUT input voltage at a time after the voltage surge-strike; and storing the measured output current and the measured DUT input voltage in a memory; comparing the specified device characteristics of the G aN transistor DUT with a at specification; and fabricating a plurality of G aN transistor devices based on the fabrication parameter in response to determining that the specified device characteristics of the GaN transistor DUT meets the at least one specification. Currently amended
(Withdrawn Amended) The method of claim 23, further comprising: determining a cause of failure in response to determining that the specified device characteristics of the G aN transistor DUT does not meet the specification; adjusting at least one of the at least one fabrication parameter; and fabricating an additional G aN transistor DUT based on the adjusted at least one of the at least one fabrication parameter and repeating the surge-testing on the additional GaN transistor DUT. Currently amended
The method of claim 23, further comprising fabricating the plurality of G aN transistor devices on a wafer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
switching power regulator (GaN transistor DUT + inductor + load)
GaN transistor power supply circuit card
surge-test system
Materials described outside the worked examples.
gallium nitride (GaN) transistor device
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 10 illustrates an example of surge testing and margin testing of a GaN transistor DUT. [0018]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,227,805Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example of test system. [0009]
FIG. 2 illustrates an example timing diagram of a surge-strike. [0010]
FIG. 3 illustrates an example of a power supply circuit card. [0011]
FIG. 4 illustrates an example state diagram of a calibration procedure. [0012]
FIG. 5 illustrates an example timing diagram of measurement times of the test system. [0013]
FIG. 6 illustrates an example diagram of a calibration voltage graph. [0014]
FIG. 7 illustrates an example diagram of a calibration inductance graph. [0015]
FIG. 8 illustrates an example diagram of parameter measurement in response to a surge-strike. [0016]
FIG. 9 illustrates an example state diagram of a surge test. [0017]
FIG. 10 illustrates an example of surge testing and margin testing of a GaN transistor DUT. [0018]
FIG. 11 illustrates an example of a diagram of a method for fabricating GaN transistor devices.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for surge-testing a gallium nitride (GaN) transistor device-under-test (DUT), the method comprising: coupling the GaN transistor DUT to a test fixture that includes an inductor that is coupled to the GaN transistor DUT to form a switching power regulator; operating the switching power regulator to provide an output current through the inductor in response to a DUT input voltage and a duty-cycle; controlling an excitation voltage source to provide a voltage surge-strike to the GaN transistor DUT; measuring the output current and the DUT input voltage after the voltage surge-strike; and storing the measured output current and the measured DUT input voltage in a memory. Currently amended
The method of claim 1, further comprising calibrating the test fixture using a calibration GaN transistor device prior to coupling the GaN transistor DUT to the test fixture. Currently amended
The method of claim 1, further comprising measuring the output current and the DUT input voltage at a time prior to the voltage surge-strike, and storing the measured output current and the measured DUT input voltage prior to and subsequent to the voltage surge-strike. Currently amended
The method of claim 1, further comprising: measuring a temperature of the G aN transistor DUT in response to the voltage surge-strike; and controlling a temperature element to maintain a defined temperature of the G aN transistor DUT responsive to the measured temperature. Currently amended
The method of claim 1, wherein controlling the excitation voltage source comprises controlling the excitation voltage source to provide a number of voltage surge strikes to the G aN transistor DUT over a time interval, and wherein measuring the output current and the DUT input voltage comprises measuring the output current and the DUT input voltage after each of the number of voltage surge strikes. Currently amended
The method of claim 1, wherein coupling the G aN transistor DUT to the test fixture includes inserting, into the test fixture, a GaN transistor power supply circuit card that includes the GaN transistor DUT. Currently amended
The method of claim 1, wherein: coupling the GaN transistor DUT to the test fixture includes inserting a first GaN transistor DUT and a second GaN transistor DUT into the test fixture, wherein the first and second GaN transistor DUTs are configured to provide high-side switching and low-side switching, respectively, for the switching power regulator, controlling the excitation voltage source comprises controlling the excitation voltage source to provide the voltage surge-strike to the first and second GaN transistor DUTs, and storing the measured output current and the measured input voltage comprises storing the measured output current and the measured DUT input voltage in the memory. Currently amended
The method of claim 1, further comprising: measuring an input current associated with the GaN transistor DUT and an output voltage associated with the switching power regulator before and during the voltage surge-strike; and storing the measured input current and the measured output voltage in the memory. Currently amended
The method of claim 1, further comprising: fabricating the GaN transistor DUT; measuring a device characteristic of the fabricated GaN transistor DUT; comparing the measured device characteristic of the GaN transistor DUT with a specification; and fabricating a plurality of GaN transistor devices in response to determining that the device characteristic is within the SVG 16656363.08-13-2021.KSAVIVJCLDFLYX9.CLM.1.svg 0.16 5.59 Black and white Currently amended
(Withdrawn Amended) A test system for testing a gallium nitride (GaN) transistor device-under-test (DUT), the system comprising: a test fixture comprising an inductor, a load, and electrical connectors configured to couple to the GaN transistor DUT, wherein the GaN transistor DUT, the load, and the inductor form a switching power regulator when the GaN transistor DUT is coupled to at least one of the electrical connectors; an excitation voltage source coupled to the GaN transistor DUT, and configured to provide a DUT input voltage to the GaN transistor DUT, the switching power regulator providing an output current through the inductor in response to en the DUT input voltage and a duty-cycle, the excitation voltage source being further configured to provide a voltage surge-strike to the GaN transistor DUT; a test controller configured to measure the output current and the DUT input voltage in response to the voltage surge-strike; and a memory configured to store the measured output current and the measured DUT input voltage. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the test controller is further configured to measure an input current and an output voltage associated with the GaN transistor DUT after the voltage surge-strike, and store the measured input current and the measured output voltage in the memory. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the excitation voltage source is configured to provide a number of voltage surge strikes to the GaN transistor DUT, and wherein the test controller is configured to measure the output current and the DUT input voltage in response to each of the voltage surge strikes. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the test controller is configured to _ determine if the measured output current and the measured DUT input voltage are within a range of specifications defined by calibration values associated with the output current and the DUT input voltage., change a voltage surge-strike set point in response to the measured DUT input voltage being outside of the range of specifications; and, change an amplitude of an inductance of the inductor in response to the measured output current being outside of the range of specifications. Currently amended
(Withdrawn Amended) A power supply circuit comprising: a gallium nitride (GaN) transistor device; a first set of electrical connectors adapted to be coupled to respective connectors of a surge-test fixture, and configured to communicate electrical signals to the surge-test fixture for performing surge-testing of the G aN transistor device by the surge-test fixture; and a second set of electrical connectors adapted to be coupled to respective connectors of a parametric-test fixture, and configured to communicate electrical signals to the parametric-test fixture for performing device-relevant parametric characteristic testing of the G aN transistor device by the parametric-test fixture. Currently amended
(Withdrawn Amended) The power supply circuit of claim 20, wherein the characteristics being tested comprise at least one of threshold voltage, on-resistance, and terminal leakage currents associated with the GaN transistor device. Currently amended
(Withdrawn Amended) The power supply circuit of claim 20, wherein the first set of electrical connectors are electrically coupled to the G aN transistor device to enable measurement of input voltage, output voltage, input current, and output current of the G aN transistor device during the surge-testing of the GaN transistor device. Currently amended
(Withdrawn Amended) A method comprising: fabricating a G aN transistor device-under-test (DUT) based on at least one fabrication parameter; surge-testing the G aN transistor DUT comprising: coupling the G aN transistor DUT to a test fixture that includes an inductor coupled to the G aN transistor DUT to form a switching power regulator; operating the switching power regulator at a DUT operating voltage to provide an output current through the inductor responsive to a DUT input voltage and a duty-cycle; controlling an excitation voltage source to provide a voltage surge-strike to the G aN transistor DUT; measuring the output current and the DUT input voltage at a time after the voltage surge-strike; and storing the measured output current and the measured DUT input voltage in a memory; comparing the specified device characteristics of the G aN transistor DUT with a at specification; and fabricating a plurality of G aN transistor devices based on the fabrication parameter in response to determining that the specified device characteristics of the GaN transistor DUT meets the at least one specification. Currently amended
(Withdrawn Amended) The method of claim 23, further comprising: determining a cause of failure in response to determining that the specified device characteristics of the G aN transistor DUT does not meet the specification; adjusting at least one of the at least one fabrication parameter; and fabricating an additional G aN transistor DUT based on the adjusted at least one of the at least one fabrication parameter and repeating the surge-testing on the additional GaN transistor DUT. Currently amended
The method of claim 23, further comprising fabricating the plurality of G aN transistor devices on a wafer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
switching power regulator (GaN transistor DUT + inductor + load)
GaN transistor power supply circuit card
surge-test system
Materials described outside the worked examples.
gallium nitride (GaN) transistor device
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 10 illustrates an example of surge testing and margin testing of a GaN transistor DUT. [0018]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,227,805Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example of test system. [0009]
FIG. 2 illustrates an example timing diagram of a surge-strike. [0010]
FIG. 3 illustrates an example of a power supply circuit card. [0011]
FIG. 4 illustrates an example state diagram of a calibration procedure. [0012]
FIG. 5 illustrates an example timing diagram of measurement times of the test system. [0013]
FIG. 6 illustrates an example diagram of a calibration voltage graph. [0014]
FIG. 7 illustrates an example diagram of a calibration inductance graph. [0015]
FIG. 8 illustrates an example diagram of parameter measurement in response to a surge-strike. [0016]
FIG. 9 illustrates an example state diagram of a surge test. [0017]
FIG. 10 illustrates an example of surge testing and margin testing of a GaN transistor DUT. [0018]
FIG. 11 illustrates an example of a diagram of a method for fabricating GaN transistor devices.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for surge-testing a gallium nitride (GaN) transistor device-under-test (DUT), the method comprising: coupling the GaN transistor DUT to a test fixture that includes an inductor that is coupled to the GaN transistor DUT to form a switching power regulator; operating the switching power regulator to provide an output current through the inductor in response to a DUT input voltage and a duty-cycle; controlling an excitation voltage source to provide a voltage surge-strike to the GaN transistor DUT; measuring the output current and the DUT input voltage after the voltage surge-strike; and storing the measured output current and the measured DUT input voltage in a memory. Currently amended
The method of claim 1, further comprising calibrating the test fixture using a calibration GaN transistor device prior to coupling the GaN transistor DUT to the test fixture. Currently amended
The method of claim 1, further comprising measuring the output current and the DUT input voltage at a time prior to the voltage surge-strike, and storing the measured output current and the measured DUT input voltage prior to and subsequent to the voltage surge-strike. Currently amended
The method of claim 1, further comprising: measuring a temperature of the G aN transistor DUT in response to the voltage surge-strike; and controlling a temperature element to maintain a defined temperature of the G aN transistor DUT responsive to the measured temperature. Currently amended
The method of claim 1, wherein controlling the excitation voltage source comprises controlling the excitation voltage source to provide a number of voltage surge strikes to the G aN transistor DUT over a time interval, and wherein measuring the output current and the DUT input voltage comprises measuring the output current and the DUT input voltage after each of the number of voltage surge strikes. Currently amended
The method of claim 1, wherein coupling the G aN transistor DUT to the test fixture includes inserting, into the test fixture, a GaN transistor power supply circuit card that includes the GaN transistor DUT. Currently amended
The method of claim 1, wherein: coupling the GaN transistor DUT to the test fixture includes inserting a first GaN transistor DUT and a second GaN transistor DUT into the test fixture, wherein the first and second GaN transistor DUTs are configured to provide high-side switching and low-side switching, respectively, for the switching power regulator, controlling the excitation voltage source comprises controlling the excitation voltage source to provide the voltage surge-strike to the first and second GaN transistor DUTs, and storing the measured output current and the measured input voltage comprises storing the measured output current and the measured DUT input voltage in the memory. Currently amended
The method of claim 1, further comprising: measuring an input current associated with the GaN transistor DUT and an output voltage associated with the switching power regulator before and during the voltage surge-strike; and storing the measured input current and the measured output voltage in the memory. Currently amended
The method of claim 1, further comprising: fabricating the GaN transistor DUT; measuring a device characteristic of the fabricated GaN transistor DUT; comparing the measured device characteristic of the GaN transistor DUT with a specification; and fabricating a plurality of GaN transistor devices in response to determining that the device characteristic is within the SVG 16656363.08-13-2021.KSAVIVJCLDFLYX9.CLM.1.svg 0.16 5.59 Black and white Currently amended
(Withdrawn Amended) A test system for testing a gallium nitride (GaN) transistor device-under-test (DUT), the system comprising: a test fixture comprising an inductor, a load, and electrical connectors configured to couple to the GaN transistor DUT, wherein the GaN transistor DUT, the load, and the inductor form a switching power regulator when the GaN transistor DUT is coupled to at least one of the electrical connectors; an excitation voltage source coupled to the GaN transistor DUT, and configured to provide a DUT input voltage to the GaN transistor DUT, the switching power regulator providing an output current through the inductor in response to en the DUT input voltage and a duty-cycle, the excitation voltage source being further configured to provide a voltage surge-strike to the GaN transistor DUT; a test controller configured to measure the output current and the DUT input voltage in response to the voltage surge-strike; and a memory configured to store the measured output current and the measured DUT input voltage. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the test controller is further configured to measure an input current and an output voltage associated with the GaN transistor DUT after the voltage surge-strike, and store the measured input current and the measured output voltage in the memory. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the excitation voltage source is configured to provide a number of voltage surge strikes to the GaN transistor DUT, and wherein the test controller is configured to measure the output current and the DUT input voltage in response to each of the voltage surge strikes. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the test controller is configured to _ determine if the measured output current and the measured DUT input voltage are within a range of specifications defined by calibration values associated with the output current and the DUT input voltage., change a voltage surge-strike set point in response to the measured DUT input voltage being outside of the range of specifications; and, change an amplitude of an inductance of the inductor in response to the measured output current being outside of the range of specifications. Currently amended
(Withdrawn Amended) A power supply circuit comprising: a gallium nitride (GaN) transistor device; a first set of electrical connectors adapted to be coupled to respective connectors of a surge-test fixture, and configured to communicate electrical signals to the surge-test fixture for performing surge-testing of the G aN transistor device by the surge-test fixture; and a second set of electrical connectors adapted to be coupled to respective connectors of a parametric-test fixture, and configured to communicate electrical signals to the parametric-test fixture for performing device-relevant parametric characteristic testing of the G aN transistor device by the parametric-test fixture. Currently amended
(Withdrawn Amended) The power supply circuit of claim 20, wherein the characteristics being tested comprise at least one of threshold voltage, on-resistance, and terminal leakage currents associated with the GaN transistor device. Currently amended
(Withdrawn Amended) The power supply circuit of claim 20, wherein the first set of electrical connectors are electrically coupled to the G aN transistor device to enable measurement of input voltage, output voltage, input current, and output current of the G aN transistor device during the surge-testing of the GaN transistor device. Currently amended
(Withdrawn Amended) A method comprising: fabricating a G aN transistor device-under-test (DUT) based on at least one fabrication parameter; surge-testing the G aN transistor DUT comprising: coupling the G aN transistor DUT to a test fixture that includes an inductor coupled to the G aN transistor DUT to form a switching power regulator; operating the switching power regulator at a DUT operating voltage to provide an output current through the inductor responsive to a DUT input voltage and a duty-cycle; controlling an excitation voltage source to provide a voltage surge-strike to the G aN transistor DUT; measuring the output current and the DUT input voltage at a time after the voltage surge-strike; and storing the measured output current and the measured DUT input voltage in a memory; comparing the specified device characteristics of the G aN transistor DUT with a at specification; and fabricating a plurality of G aN transistor devices based on the fabrication parameter in response to determining that the specified device characteristics of the GaN transistor DUT meets the at least one specification. Currently amended
(Withdrawn Amended) The method of claim 23, further comprising: determining a cause of failure in response to determining that the specified device characteristics of the G aN transistor DUT does not meet the specification; adjusting at least one of the at least one fabrication parameter; and fabricating an additional G aN transistor DUT based on the adjusted at least one of the at least one fabrication parameter and repeating the surge-testing on the additional GaN transistor DUT. Currently amended
The method of claim 23, further comprising fabricating the plurality of G aN transistor devices on a wafer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
switching power regulator (GaN transistor DUT + inductor + load)
GaN transistor power supply circuit card
surge-test system
Materials described outside the worked examples.
gallium nitride (GaN) transistor device
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 10 illustrates an example of surge testing and margin testing of a GaN transistor DUT. [0018]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,227,805Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example of test system. [0009]
FIG. 2 illustrates an example timing diagram of a surge-strike. [0010]
FIG. 3 illustrates an example of a power supply circuit card. [0011]
FIG. 4 illustrates an example state diagram of a calibration procedure. [0012]
FIG. 5 illustrates an example timing diagram of measurement times of the test system. [0013]
FIG. 6 illustrates an example diagram of a calibration voltage graph. [0014]
FIG. 7 illustrates an example diagram of a calibration inductance graph. [0015]
FIG. 8 illustrates an example diagram of parameter measurement in response to a surge-strike. [0016]
FIG. 9 illustrates an example state diagram of a surge test. [0017]
FIG. 10 illustrates an example of surge testing and margin testing of a GaN transistor DUT. [0018]
FIG. 11 illustrates an example of a diagram of a method for fabricating GaN transistor devices.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for surge-testing a gallium nitride (GaN) transistor device-under-test (DUT), the method comprising: coupling the GaN transistor DUT to a test fixture that includes an inductor that is coupled to the GaN transistor DUT to form a switching power regulator; operating the switching power regulator to provide an output current through the inductor in response to a DUT input voltage and a duty-cycle; controlling an excitation voltage source to provide a voltage surge-strike to the GaN transistor DUT; measuring the output current and the DUT input voltage after the voltage surge-strike; and storing the measured output current and the measured DUT input voltage in a memory. Currently amended
The method of claim 1, further comprising calibrating the test fixture using a calibration GaN transistor device prior to coupling the GaN transistor DUT to the test fixture. Currently amended
The method of claim 1, further comprising measuring the output current and the DUT input voltage at a time prior to the voltage surge-strike, and storing the measured output current and the measured DUT input voltage prior to and subsequent to the voltage surge-strike. Currently amended
The method of claim 1, further comprising: measuring a temperature of the G aN transistor DUT in response to the voltage surge-strike; and controlling a temperature element to maintain a defined temperature of the G aN transistor DUT responsive to the measured temperature. Currently amended
The method of claim 1, wherein controlling the excitation voltage source comprises controlling the excitation voltage source to provide a number of voltage surge strikes to the G aN transistor DUT over a time interval, and wherein measuring the output current and the DUT input voltage comprises measuring the output current and the DUT input voltage after each of the number of voltage surge strikes. Currently amended
The method of claim 1, wherein coupling the G aN transistor DUT to the test fixture includes inserting, into the test fixture, a GaN transistor power supply circuit card that includes the GaN transistor DUT. Currently amended
The method of claim 1, wherein: coupling the GaN transistor DUT to the test fixture includes inserting a first GaN transistor DUT and a second GaN transistor DUT into the test fixture, wherein the first and second GaN transistor DUTs are configured to provide high-side switching and low-side switching, respectively, for the switching power regulator, controlling the excitation voltage source comprises controlling the excitation voltage source to provide the voltage surge-strike to the first and second GaN transistor DUTs, and storing the measured output current and the measured input voltage comprises storing the measured output current and the measured DUT input voltage in the memory. Currently amended
The method of claim 1, further comprising: measuring an input current associated with the GaN transistor DUT and an output voltage associated with the switching power regulator before and during the voltage surge-strike; and storing the measured input current and the measured output voltage in the memory. Currently amended
The method of claim 1, further comprising: fabricating the GaN transistor DUT; measuring a device characteristic of the fabricated GaN transistor DUT; comparing the measured device characteristic of the GaN transistor DUT with a specification; and fabricating a plurality of GaN transistor devices in response to determining that the device characteristic is within the SVG 16656363.08-13-2021.KSAVIVJCLDFLYX9.CLM.1.svg 0.16 5.59 Black and white Currently amended
(Withdrawn Amended) A test system for testing a gallium nitride (GaN) transistor device-under-test (DUT), the system comprising: a test fixture comprising an inductor, a load, and electrical connectors configured to couple to the GaN transistor DUT, wherein the GaN transistor DUT, the load, and the inductor form a switching power regulator when the GaN transistor DUT is coupled to at least one of the electrical connectors; an excitation voltage source coupled to the GaN transistor DUT, and configured to provide a DUT input voltage to the GaN transistor DUT, the switching power regulator providing an output current through the inductor in response to en the DUT input voltage and a duty-cycle, the excitation voltage source being further configured to provide a voltage surge-strike to the GaN transistor DUT; a test controller configured to measure the output current and the DUT input voltage in response to the voltage surge-strike; and a memory configured to store the measured output current and the measured DUT input voltage. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the test controller is further configured to measure an input current and an output voltage associated with the GaN transistor DUT after the voltage surge-strike, and store the measured input current and the measured output voltage in the memory. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the excitation voltage source is configured to provide a number of voltage surge strikes to the GaN transistor DUT, and wherein the test controller is configured to measure the output current and the DUT input voltage in response to each of the voltage surge strikes. Currently amended
(Withdrawn Amended) The system of claim 15, wherein the test controller is configured to _ determine if the measured output current and the measured DUT input voltage are within a range of specifications defined by calibration values associated with the output current and the DUT input voltage., change a voltage surge-strike set point in response to the measured DUT input voltage being outside of the range of specifications; and, change an amplitude of an inductance of the inductor in response to the measured output current being outside of the range of specifications. Currently amended
(Withdrawn Amended) A power supply circuit comprising: a gallium nitride (GaN) transistor device; a first set of electrical connectors adapted to be coupled to respective connectors of a surge-test fixture, and configured to communicate electrical signals to the surge-test fixture for performing surge-testing of the G aN transistor device by the surge-test fixture; and a second set of electrical connectors adapted to be coupled to respective connectors of a parametric-test fixture, and configured to communicate electrical signals to the parametric-test fixture for performing device-relevant parametric characteristic testing of the G aN transistor device by the parametric-test fixture. Currently amended
(Withdrawn Amended) The power supply circuit of claim 20, wherein the characteristics being tested comprise at least one of threshold voltage, on-resistance, and terminal leakage currents associated with the GaN transistor device. Currently amended
(Withdrawn Amended) The power supply circuit of claim 20, wherein the first set of electrical connectors are electrically coupled to the G aN transistor device to enable measurement of input voltage, output voltage, input current, and output current of the G aN transistor device during the surge-testing of the GaN transistor device. Currently amended
(Withdrawn Amended) A method comprising: fabricating a G aN transistor device-under-test (DUT) based on at least one fabrication parameter; surge-testing the G aN transistor DUT comprising: coupling the G aN transistor DUT to a test fixture that includes an inductor coupled to the G aN transistor DUT to form a switching power regulator; operating the switching power regulator at a DUT operating voltage to provide an output current through the inductor responsive to a DUT input voltage and a duty-cycle; controlling an excitation voltage source to provide a voltage surge-strike to the G aN transistor DUT; measuring the output current and the DUT input voltage at a time after the voltage surge-strike; and storing the measured output current and the measured DUT input voltage in a memory; comparing the specified device characteristics of the G aN transistor DUT with a at specification; and fabricating a plurality of G aN transistor devices based on the fabrication parameter in response to determining that the specified device characteristics of the GaN transistor DUT meets the at least one specification. Currently amended
(Withdrawn Amended) The method of claim 23, further comprising: determining a cause of failure in response to determining that the specified device characteristics of the G aN transistor DUT does not meet the specification; adjusting at least one of the at least one fabrication parameter; and fabricating an additional G aN transistor DUT based on the adjusted at least one of the at least one fabrication parameter and repeating the surge-testing on the additional GaN transistor DUT. Currently amended
The method of claim 23, further comprising fabricating the plurality of G aN transistor devices on a wafer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
switching power regulator (GaN transistor DUT + inductor + load)
GaN transistor power supply circuit card
surge-test system
Materials described outside the worked examples.
gallium nitride (GaN) transistor device
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 10 illustrates an example of surge testing and margin testing of a GaN transistor DUT. [0018]
Related documents with shared materials, methods, properties, or citations.
FIG. 11 illustrates an example of a diagram of a method for fabricating GaN transistor devices.
durability of the GaN transistor device in response to spurious overvoltage conditions that may occur during operation of the resulting switching power regulator in which the GaN transistor device is included. The surge-testing can be conducted a number of tim
FIG. 11 illustrates an example of a diagram of a method for fabricating GaN transistor devices.
durability of the GaN transistor device in response to spurious overvoltage conditions that may occur during operation of the resulting switching power regulator in which the GaN transistor device is included. The surge-testing can be conducted a number of tim
FIG. 11 illustrates an example of a diagram of a method for fabricating GaN transistor devices.
durability of the GaN transistor device in response to spurious overvoltage conditions that may occur during operation of the resulting switching power regulator in which the GaN transistor device is included. The surge-testing can be conducted a number of tim
FIG. 11 illustrates an example of a diagram of a method for fabricating GaN transistor devices.
durability of the GaN transistor device in response to spurious overvoltage conditions that may occur during operation of the resulting switching power regulator in which the GaN transistor device is included. The surge-testing can be conducted a number of tim