GEOMETRIC MANIPULATION OF 2DEG REGION IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR | Matter42 Literature
Patent
Atlas literature
Patent
US 10,804,359
GEOMETRIC MANIPULATION OF 2DEG REGION IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR
Marko RADOSAVLJEVIC, Han Wui THEN, Sansaptak DASGUPTA, Sanaz GARDNER
INTEL CORPORATION·22 June 2017·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 3
FIG. 3A Description GEOMETR T C MAN I PULATION OF 2DEG REG I ON IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR BACKGROUND In the manufacture of integrated …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
4
Dependent← claim 2
The application has been amended as follows: a. In claim 2, line 1, replace "the vertical thickness" with -the thinnest vertical thickness--. b. In claim 2, line 2, replace "the vertical thickness" with -the thickest vertical thickness--. c. In claim 10, line 1, replace "the vertical thickness" with -the first vertical thickness--. d. In claim 10, line 2, replace "the vertical thickness" with -the second vertical thickness--. SVG 15772742.09-14-2020.KF₃₄Z₉NJRXEAPX2.CLM.1.svg 0.25 6.93 Black and white d ocument, thickness--. + 2020 f. In claim 36, line $, replace "the thickest vertical thickness" with -the second vertical thickness--.
5
Dependent← claim 1, claim 2
Claims 1-2, 6, 9-10, 14, 26-27, 30 and 32-42 are allowed.
6
Dependent← claim 1III-N compoundGaN transistor with 2DEG source/drain extension
The following is an examiner's statement of reasons for allowance: the prior art of record fails to disclose/suggest (claim 1) wherein a bottom surface of the first source or drain region is lower than a top surface of the first layer, wherein a bottom surface of the second source or drain region is lower than the top surface of the first layer, and, a second layer over the top surface of the first layer and adjacent one side of the gate such that the second layer is between the gate and the first source or drain region, the second layer comprising a I ll -N compound, wherein the second layer has a thinnest vertical thickness at a point closest to the gate and a thickest vertical thickness at a point farthest from the gate as recited within the context of the claim, (claim 9) wherein a bottom surface of the first source or drain region is lower than a top surface of the first region, wherein a bottom surface of the second source or drain region is lower than the to p surface of the first region, and, a second region com p rising a I II-N
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with 2DEG source/drain extension
III-N compoundpolarization/barrier layer
GaNchannel
Materials
Materials described outside the worked examples.
III-N compound
Polarization/Barrier Layer
GaN
Semiconductor Channel
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 3A Description GEOMETR T C MAN I PULATION OF 2DEG REG I ON IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR BACKGROUND In the manufacture of integrated …
GEOMETRIC MANIPULATION OF 2DEG REGION IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR
Marko RADOSAVLJEVIC, Han Wui THEN, Sansaptak DASGUPTA, Sanaz GARDNER
INTEL CORPORATION·22 June 2017·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 3
FIG. 3A Description GEOMETR T C MAN I PULATION OF 2DEG REG I ON IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR BACKGROUND In the manufacture of integrated …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
4
Dependent← claim 2
The application has been amended as follows: a. In claim 2, line 1, replace "the vertical thickness" with -the thinnest vertical thickness--. b. In claim 2, line 2, replace "the vertical thickness" with -the thickest vertical thickness--. c. In claim 10, line 1, replace "the vertical thickness" with -the first vertical thickness--. d. In claim 10, line 2, replace "the vertical thickness" with -the second vertical thickness--. SVG 15772742.09-14-2020.KF₃₄Z₉NJRXEAPX2.CLM.1.svg 0.25 6.93 Black and white d ocument, thickness--. + 2020 f. In claim 36, line $, replace "the thickest vertical thickness" with -the second vertical thickness--.
5
Dependent← claim 1, claim 2
Claims 1-2, 6, 9-10, 14, 26-27, 30 and 32-42 are allowed.
6
Dependent← claim 1III-N compoundGaN transistor with 2DEG source/drain extension
The following is an examiner's statement of reasons for allowance: the prior art of record fails to disclose/suggest (claim 1) wherein a bottom surface of the first source or drain region is lower than a top surface of the first layer, wherein a bottom surface of the second source or drain region is lower than the top surface of the first layer, and, a second layer over the top surface of the first layer and adjacent one side of the gate such that the second layer is between the gate and the first source or drain region, the second layer comprising a I ll -N compound, wherein the second layer has a thinnest vertical thickness at a point closest to the gate and a thickest vertical thickness at a point farthest from the gate as recited within the context of the claim, (claim 9) wherein a bottom surface of the first source or drain region is lower than a top surface of the first region, wherein a bottom surface of the second source or drain region is lower than the to p surface of the first region, and, a second region com p rising a I II-N
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with 2DEG source/drain extension
III-N compoundpolarization/barrier layer
GaNchannel
Materials
Materials described outside the worked examples.
III-N compound
Polarization/Barrier Layer
GaN
Semiconductor Channel
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 3A Description GEOMETR T C MAN I PULATION OF 2DEG REG I ON IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR BACKGROUND In the manufacture of integrated …
GEOMETRIC MANIPULATION OF 2DEG REGION IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR
Marko RADOSAVLJEVIC, Han Wui THEN, Sansaptak DASGUPTA, Sanaz GARDNER
INTEL CORPORATION·22 June 2017·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 3
FIG. 3A Description GEOMETR T C MAN I PULATION OF 2DEG REG I ON IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR BACKGROUND In the manufacture of integrated …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
4
Dependent← claim 2
The application has been amended as follows: a. In claim 2, line 1, replace "the vertical thickness" with -the thinnest vertical thickness--. b. In claim 2, line 2, replace "the vertical thickness" with -the thickest vertical thickness--. c. In claim 10, line 1, replace "the vertical thickness" with -the first vertical thickness--. d. In claim 10, line 2, replace "the vertical thickness" with -the second vertical thickness--. SVG 15772742.09-14-2020.KF₃₄Z₉NJRXEAPX2.CLM.1.svg 0.25 6.93 Black and white d ocument, thickness--. + 2020 f. In claim 36, line $, replace "the thickest vertical thickness" with -the second vertical thickness--.
5
Dependent← claim 1, claim 2
Claims 1-2, 6, 9-10, 14, 26-27, 30 and 32-42 are allowed.
6
Dependent← claim 1III-N compoundGaN transistor with 2DEG source/drain extension
The following is an examiner's statement of reasons for allowance: the prior art of record fails to disclose/suggest (claim 1) wherein a bottom surface of the first source or drain region is lower than a top surface of the first layer, wherein a bottom surface of the second source or drain region is lower than the top surface of the first layer, and, a second layer over the top surface of the first layer and adjacent one side of the gate such that the second layer is between the gate and the first source or drain region, the second layer comprising a I ll -N compound, wherein the second layer has a thinnest vertical thickness at a point closest to the gate and a thickest vertical thickness at a point farthest from the gate as recited within the context of the claim, (claim 9) wherein a bottom surface of the first source or drain region is lower than a top surface of the first region, wherein a bottom surface of the second source or drain region is lower than the to p surface of the first region, and, a second region com p rising a I II-N
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with 2DEG source/drain extension
III-N compoundpolarization/barrier layer
GaNchannel
Materials
Materials described outside the worked examples.
III-N compound
Polarization/Barrier Layer
GaN
Semiconductor Channel
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 3A Description GEOMETR T C MAN I PULATION OF 2DEG REG I ON IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR BACKGROUND In the manufacture of integrated …
GEOMETRIC MANIPULATION OF 2DEG REGION IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR
Marko RADOSAVLJEVIC, Han Wui THEN, Sansaptak DASGUPTA, Sanaz GARDNER
INTEL CORPORATION·22 June 2017·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 3
FIG. 3A Description GEOMETR T C MAN I PULATION OF 2DEG REG I ON IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR BACKGROUND In the manufacture of integrated …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
4
Dependent← claim 2
The application has been amended as follows: a. In claim 2, line 1, replace "the vertical thickness" with -the thinnest vertical thickness--. b. In claim 2, line 2, replace "the vertical thickness" with -the thickest vertical thickness--. c. In claim 10, line 1, replace "the vertical thickness" with -the first vertical thickness--. d. In claim 10, line 2, replace "the vertical thickness" with -the second vertical thickness--. SVG 15772742.09-14-2020.KF₃₄Z₉NJRXEAPX2.CLM.1.svg 0.25 6.93 Black and white d ocument, thickness--. + 2020 f. In claim 36, line $, replace "the thickest vertical thickness" with -the second vertical thickness--.
5
Dependent← claim 1, claim 2
Claims 1-2, 6, 9-10, 14, 26-27, 30 and 32-42 are allowed.
6
Dependent← claim 1III-N compoundGaN transistor with 2DEG source/drain extension
The following is an examiner's statement of reasons for allowance: the prior art of record fails to disclose/suggest (claim 1) wherein a bottom surface of the first source or drain region is lower than a top surface of the first layer, wherein a bottom surface of the second source or drain region is lower than the top surface of the first layer, and, a second layer over the top surface of the first layer and adjacent one side of the gate such that the second layer is between the gate and the first source or drain region, the second layer comprising a I ll -N compound, wherein the second layer has a thinnest vertical thickness at a point closest to the gate and a thickest vertical thickness at a point farthest from the gate as recited within the context of the claim, (claim 9) wherein a bottom surface of the first source or drain region is lower than a top surface of the first region, wherein a bottom surface of the second source or drain region is lower than the to p surface of the first region, and, a second region com p rising a I II-N
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with 2DEG source/drain extension
III-N compoundpolarization/barrier layer
GaNchannel
Materials
Materials described outside the worked examples.
III-N compound
Polarization/Barrier Layer
GaN
Semiconductor Channel
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 3A Description GEOMETR T C MAN I PULATION OF 2DEG REG I ON IN SOURCE/DRAIN EXTENSION OF GAN TRANSISTOR BACKGROUND In the manufacture of integrated …