Patent
Atlas literature
Patent
US 12,163,995 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example of a built-in self-test circuit formed on a testing printed circuit board (PCB) for a power amplification stage that employs low …
FIG. 2B illustrates a timing diagram showing operating conditions of the built-in self-test circuit of
FIG. 3B illustrates a timing diagram showing operating conditions of the built-in self-test circuit of
FIG. 4B illustrates a block and operational diagram of a pulse generating circuity, in accordance with some embodi- ments. 10
FIG. 5 illustrates a flow chart of a method for reliability testing one or more GaN FETs, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A reliability testing apparatus for stacked transistors, comprising: a high side transistor; a low side transistor; a high side driver coupled to the high side transistor; a low side driver coupled to the low side transistor; an integrated driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side tran-sistors, wherein the high and low side transistors are connected to a plurality of monitoring pads, wherein the plurality of monitoring pads are configured to measure dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein the high and low side transistors, the high and low side drivers, and the integrated driver circuit are all fabricated on a same semiconductor device layer, and wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer.
The apparatus of claim 1, wherein the integrated driver circuit comprises an integrated chopper circuit and an inte-grated pulse generator circuit configured to generate the drive signals.
The apparatus of claim 1, wherein the integrated driver circuit is further configured to set duty cycles of the drive signals based on testing parameters of the high and low side transistors.
The apparatus of claim 1 further comprises a voltage level shifter (VLS) coupled to an input of the high side driver.
The apparatus of claim 1, wherein the LC filter com-prises an inductor and a capacitor.
The apparatus of claim 1, wherein the plurality of monitoring pads are installed at a drain, a source, and a gate of the high side transistor.
A built-in self-test circuit for testing reliability of one or more transistors, comprising: a transistor test switch; 15 a driver circuit coupled to a gate of the transistor test switch; an integrated chopper circuit coupled to the driver circuit and configured to generate a drive signal capable of driving the transistor test switch, wherein the transistor test switch is connected to a plu-rality of monitoring pads, wherein the plurality of monitoring pads are configured to measure a dynamic on-state resistance (Rdson) of the transistor test switch, wherein the dynamic on-state resistance (Rdson) is determined by: a first voltage probe configured to measure drain to source voltages of the transistor test switch, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein the transistor test switch, the driver circuit, and the integrated chopper circuit are all fabricated on a same device semiconductor layer, and wherein interconnections that couple the integrated chop-per circuit, the driver circuit, and the transistor test switch are patterned on a same metallization layer.
The built-in self-test circuit of claim 9, wherein the drive signal is a pulse width modulated signal with a predetermined duty cycle.
The built-in self-test circuit of claim 9, wherein the integrated chopper circuit is further configured to set the duty cycle of the drive signal based on a testing parameter.
The built-in self-test circuit of claim 9, wherein the LC filter comprises an inductor and a capacitor.
The built-in self-test circuit of claim 9, the integrated chopper circuit comprises a delay line based on an even number of inverter gates and a comparator.
A method for reliability testing one or more transis-tors, the method comprising: generating drive signals by an integrated driver circuit; driving gates of high and low side transistors by a high and low side drivers, respectively, wherein the high and low side transistors are connected to a plurality of monitoring pads and wherein the high and low side drivers receive the drive signals from the integrated driver circuit; fabricating the high and low side transistors, the high and low side drivers, and the integrated driver circuit on a same device semiconductor layer; and measuring dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) of the high and low side transistors are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer.
The method of claim 15, wherein the drive signals are pulse width modulated signals.
The method of claim 15 further comprising sensing a relationship between junction temperatures of the high side and low side transistors and the corresponding dynamic on-state resistances.
Layer stacks claimed or described, ordered top of device to substrate.
reliability testing apparatus for stacked GaN transistors (half-bridge)
built-in self-test circuit for transistor reliability testing
GaN bidirectional switch half-bridge BIST circuit on PCB (FIG. 1 embodiment)
Materials described outside the worked examples.
Gallium Nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example of a built-in self-test circuit formed on a testing printed circuit board (PCB) for a power amplification stage that employs low …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
dynamic on-state resistance (Rdson) degradation factor due to current collapse | — | GaN |
VDD supply voltage range for BIST circuit | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,163,995 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example of a built-in self-test circuit formed on a testing printed circuit board (PCB) for a power amplification stage that employs low …
FIG. 2B illustrates a timing diagram showing operating conditions of the built-in self-test circuit of
FIG. 3B illustrates a timing diagram showing operating conditions of the built-in self-test circuit of
FIG. 4B illustrates a block and operational diagram of a pulse generating circuity, in accordance with some embodi- ments. 10
FIG. 5 illustrates a flow chart of a method for reliability testing one or more GaN FETs, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A reliability testing apparatus for stacked transistors, comprising: a high side transistor; a low side transistor; a high side driver coupled to the high side transistor; a low side driver coupled to the low side transistor; an integrated driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side tran-sistors, wherein the high and low side transistors are connected to a plurality of monitoring pads, wherein the plurality of monitoring pads are configured to measure dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein the high and low side transistors, the high and low side drivers, and the integrated driver circuit are all fabricated on a same semiconductor device layer, and wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer.
The apparatus of claim 1, wherein the integrated driver circuit comprises an integrated chopper circuit and an inte-grated pulse generator circuit configured to generate the drive signals.
The apparatus of claim 1, wherein the integrated driver circuit is further configured to set duty cycles of the drive signals based on testing parameters of the high and low side transistors.
The apparatus of claim 1 further comprises a voltage level shifter (VLS) coupled to an input of the high side driver.
The apparatus of claim 1, wherein the LC filter com-prises an inductor and a capacitor.
The apparatus of claim 1, wherein the plurality of monitoring pads are installed at a drain, a source, and a gate of the high side transistor.
A built-in self-test circuit for testing reliability of one or more transistors, comprising: a transistor test switch; 15 a driver circuit coupled to a gate of the transistor test switch; an integrated chopper circuit coupled to the driver circuit and configured to generate a drive signal capable of driving the transistor test switch, wherein the transistor test switch is connected to a plu-rality of monitoring pads, wherein the plurality of monitoring pads are configured to measure a dynamic on-state resistance (Rdson) of the transistor test switch, wherein the dynamic on-state resistance (Rdson) is determined by: a first voltage probe configured to measure drain to source voltages of the transistor test switch, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein the transistor test switch, the driver circuit, and the integrated chopper circuit are all fabricated on a same device semiconductor layer, and wherein interconnections that couple the integrated chop-per circuit, the driver circuit, and the transistor test switch are patterned on a same metallization layer.
The built-in self-test circuit of claim 9, wherein the drive signal is a pulse width modulated signal with a predetermined duty cycle.
The built-in self-test circuit of claim 9, wherein the integrated chopper circuit is further configured to set the duty cycle of the drive signal based on a testing parameter.
The built-in self-test circuit of claim 9, wherein the LC filter comprises an inductor and a capacitor.
The built-in self-test circuit of claim 9, the integrated chopper circuit comprises a delay line based on an even number of inverter gates and a comparator.
A method for reliability testing one or more transis-tors, the method comprising: generating drive signals by an integrated driver circuit; driving gates of high and low side transistors by a high and low side drivers, respectively, wherein the high and low side transistors are connected to a plurality of monitoring pads and wherein the high and low side drivers receive the drive signals from the integrated driver circuit; fabricating the high and low side transistors, the high and low side drivers, and the integrated driver circuit on a same device semiconductor layer; and measuring dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) of the high and low side transistors are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer.
The method of claim 15, wherein the drive signals are pulse width modulated signals.
The method of claim 15 further comprising sensing a relationship between junction temperatures of the high side and low side transistors and the corresponding dynamic on-state resistances.
Layer stacks claimed or described, ordered top of device to substrate.
reliability testing apparatus for stacked GaN transistors (half-bridge)
built-in self-test circuit for transistor reliability testing
GaN bidirectional switch half-bridge BIST circuit on PCB (FIG. 1 embodiment)
Materials described outside the worked examples.
Gallium Nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example of a built-in self-test circuit formed on a testing printed circuit board (PCB) for a power amplification stage that employs low …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
dynamic on-state resistance (Rdson) degradation factor due to current collapse | — | GaN |
VDD supply voltage range for BIST circuit | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,163,995 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example of a built-in self-test circuit formed on a testing printed circuit board (PCB) for a power amplification stage that employs low …
FIG. 2B illustrates a timing diagram showing operating conditions of the built-in self-test circuit of
FIG. 3B illustrates a timing diagram showing operating conditions of the built-in self-test circuit of
FIG. 4B illustrates a block and operational diagram of a pulse generating circuity, in accordance with some embodi- ments. 10
FIG. 5 illustrates a flow chart of a method for reliability testing one or more GaN FETs, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A reliability testing apparatus for stacked transistors, comprising: a high side transistor; a low side transistor; a high side driver coupled to the high side transistor; a low side driver coupled to the low side transistor; an integrated driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side tran-sistors, wherein the high and low side transistors are connected to a plurality of monitoring pads, wherein the plurality of monitoring pads are configured to measure dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein the high and low side transistors, the high and low side drivers, and the integrated driver circuit are all fabricated on a same semiconductor device layer, and wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer.
The apparatus of claim 1, wherein the integrated driver circuit comprises an integrated chopper circuit and an inte-grated pulse generator circuit configured to generate the drive signals.
The apparatus of claim 1, wherein the integrated driver circuit is further configured to set duty cycles of the drive signals based on testing parameters of the high and low side transistors.
The apparatus of claim 1 further comprises a voltage level shifter (VLS) coupled to an input of the high side driver.
The apparatus of claim 1, wherein the LC filter com-prises an inductor and a capacitor.
The apparatus of claim 1, wherein the plurality of monitoring pads are installed at a drain, a source, and a gate of the high side transistor.
A built-in self-test circuit for testing reliability of one or more transistors, comprising: a transistor test switch; 15 a driver circuit coupled to a gate of the transistor test switch; an integrated chopper circuit coupled to the driver circuit and configured to generate a drive signal capable of driving the transistor test switch, wherein the transistor test switch is connected to a plu-rality of monitoring pads, wherein the plurality of monitoring pads are configured to measure a dynamic on-state resistance (Rdson) of the transistor test switch, wherein the dynamic on-state resistance (Rdson) is determined by: a first voltage probe configured to measure drain to source voltages of the transistor test switch, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein the transistor test switch, the driver circuit, and the integrated chopper circuit are all fabricated on a same device semiconductor layer, and wherein interconnections that couple the integrated chop-per circuit, the driver circuit, and the transistor test switch are patterned on a same metallization layer.
The built-in self-test circuit of claim 9, wherein the drive signal is a pulse width modulated signal with a predetermined duty cycle.
The built-in self-test circuit of claim 9, wherein the integrated chopper circuit is further configured to set the duty cycle of the drive signal based on a testing parameter.
The built-in self-test circuit of claim 9, wherein the LC filter comprises an inductor and a capacitor.
The built-in self-test circuit of claim 9, the integrated chopper circuit comprises a delay line based on an even number of inverter gates and a comparator.
A method for reliability testing one or more transis-tors, the method comprising: generating drive signals by an integrated driver circuit; driving gates of high and low side transistors by a high and low side drivers, respectively, wherein the high and low side transistors are connected to a plurality of monitoring pads and wherein the high and low side drivers receive the drive signals from the integrated driver circuit; fabricating the high and low side transistors, the high and low side drivers, and the integrated driver circuit on a same device semiconductor layer; and measuring dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) of the high and low side transistors are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer.
The method of claim 15, wherein the drive signals are pulse width modulated signals.
The method of claim 15 further comprising sensing a relationship between junction temperatures of the high side and low side transistors and the corresponding dynamic on-state resistances.
Layer stacks claimed or described, ordered top of device to substrate.
reliability testing apparatus for stacked GaN transistors (half-bridge)
built-in self-test circuit for transistor reliability testing
GaN bidirectional switch half-bridge BIST circuit on PCB (FIG. 1 embodiment)
Materials described outside the worked examples.
Gallium Nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example of a built-in self-test circuit formed on a testing printed circuit board (PCB) for a power amplification stage that employs low …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
dynamic on-state resistance (Rdson) degradation factor due to current collapse | — | GaN |
VDD supply voltage range for BIST circuit | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,163,995 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example of a built-in self-test circuit formed on a testing printed circuit board (PCB) for a power amplification stage that employs low …
FIG. 2B illustrates a timing diagram showing operating conditions of the built-in self-test circuit of
FIG. 3B illustrates a timing diagram showing operating conditions of the built-in self-test circuit of
FIG. 4B illustrates a block and operational diagram of a pulse generating circuity, in accordance with some embodi- ments. 10
FIG. 5 illustrates a flow chart of a method for reliability testing one or more GaN FETs, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A reliability testing apparatus for stacked transistors, comprising: a high side transistor; a low side transistor; a high side driver coupled to the high side transistor; a low side driver coupled to the low side transistor; an integrated driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side tran-sistors, wherein the high and low side transistors are connected to a plurality of monitoring pads, wherein the plurality of monitoring pads are configured to measure dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein the high and low side transistors, the high and low side drivers, and the integrated driver circuit are all fabricated on a same semiconductor device layer, and wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer.
The apparatus of claim 1, wherein the integrated driver circuit comprises an integrated chopper circuit and an inte-grated pulse generator circuit configured to generate the drive signals.
The apparatus of claim 1, wherein the integrated driver circuit is further configured to set duty cycles of the drive signals based on testing parameters of the high and low side transistors.
The apparatus of claim 1 further comprises a voltage level shifter (VLS) coupled to an input of the high side driver.
The apparatus of claim 1, wherein the LC filter com-prises an inductor and a capacitor.
The apparatus of claim 1, wherein the plurality of monitoring pads are installed at a drain, a source, and a gate of the high side transistor.
A built-in self-test circuit for testing reliability of one or more transistors, comprising: a transistor test switch; 15 a driver circuit coupled to a gate of the transistor test switch; an integrated chopper circuit coupled to the driver circuit and configured to generate a drive signal capable of driving the transistor test switch, wherein the transistor test switch is connected to a plu-rality of monitoring pads, wherein the plurality of monitoring pads are configured to measure a dynamic on-state resistance (Rdson) of the transistor test switch, wherein the dynamic on-state resistance (Rdson) is determined by: a first voltage probe configured to measure drain to source voltages of the transistor test switch, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein the transistor test switch, the driver circuit, and the integrated chopper circuit are all fabricated on a same device semiconductor layer, and wherein interconnections that couple the integrated chop-per circuit, the driver circuit, and the transistor test switch are patterned on a same metallization layer.
The built-in self-test circuit of claim 9, wherein the drive signal is a pulse width modulated signal with a predetermined duty cycle.
The built-in self-test circuit of claim 9, wherein the integrated chopper circuit is further configured to set the duty cycle of the drive signal based on a testing parameter.
The built-in self-test circuit of claim 9, wherein the LC filter comprises an inductor and a capacitor.
The built-in self-test circuit of claim 9, the integrated chopper circuit comprises a delay line based on an even number of inverter gates and a comparator.
A method for reliability testing one or more transis-tors, the method comprising: generating drive signals by an integrated driver circuit; driving gates of high and low side transistors by a high and low side drivers, respectively, wherein the high and low side transistors are connected to a plurality of monitoring pads and wherein the high and low side drivers receive the drive signals from the integrated driver circuit; fabricating the high and low side transistors, the high and low side drivers, and the integrated driver circuit on a same device semiconductor layer; and measuring dynamic on-state resistances (Rdson) of the high and low side transistors, wherein the dynamic on-state resistances (Rdson) of the high and low side transistors are determined by: a first voltage probe configured to measure drain to source voltages of the high and low side transistors, and a second voltage probe configured to measure a voltage drop across a load resistor, wherein the load resistor is connected to an inductor and capacitor (LC) filter, wherein interconnections that couple the integrated driver circuit, the high side driver, the low side driver, the high side transistor, and the low side transistor are patterned on a same metallization layer.
The method of claim 15, wherein the drive signals are pulse width modulated signals.
The method of claim 15 further comprising sensing a relationship between junction temperatures of the high side and low side transistors and the corresponding dynamic on-state resistances.
Layer stacks claimed or described, ordered top of device to substrate.
reliability testing apparatus for stacked GaN transistors (half-bridge)
built-in self-test circuit for transistor reliability testing
GaN bidirectional switch half-bridge BIST circuit on PCB (FIG. 1 embodiment)
Materials described outside the worked examples.
Gallium Nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates an example of a built-in self-test circuit formed on a testing printed circuit board (PCB) for a power amplification stage that employs low …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
dynamic on-state resistance (Rdson) degradation factor due to current collapse | — | GaN |
VDD supply voltage range for BIST circuit | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
GaN BIST circuit on semiconductor wafer (FIG. 2A embodiment)
FIG. 5 illustrates a flow chart of a method for reliability testing one or more GaN FETs, in accordance with some embodiments.
drive signal duty cycle for low side GaN FET switch (drive signal 111) | — | — |
drive signal duty cycle for high side GaN FET switch (drive signal 113) | — | — |
Voltage | 0–400 V | — |
GaN BIST circuit on semiconductor wafer (FIG. 2A embodiment)
FIG. 5 illustrates a flow chart of a method for reliability testing one or more GaN FETs, in accordance with some embodiments.
drive signal duty cycle for low side GaN FET switch (drive signal 111) | — | — |
drive signal duty cycle for high side GaN FET switch (drive signal 113) | — | — |
Voltage | 0–400 V | — |
GaN BIST circuit on semiconductor wafer (FIG. 2A embodiment)
FIG. 5 illustrates a flow chart of a method for reliability testing one or more GaN FETs, in accordance with some embodiments.
drive signal duty cycle for low side GaN FET switch (drive signal 111) | — | — |
drive signal duty cycle for high side GaN FET switch (drive signal 113) | — | — |
Voltage | 0–400 V | — |
GaN BIST circuit on semiconductor wafer (FIG. 2A embodiment)
FIG. 5 illustrates a flow chart of a method for reliability testing one or more GaN FETs, in accordance with some embodiments.
drive signal duty cycle for low side GaN FET switch (drive signal 111) | — | — |
drive signal duty cycle for high side GaN FET switch (drive signal 113) | — | — |
Voltage | 0–400 V | — |
