Patent
Atlas literature
Patent
US 12,027,516 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a structural diagram and an equivalent circuit diagram of a traditional GaN device with a P-type 10 GaN cap layer;
FIG. 2 illustrates a structural diagram and an equivalent circuit diagram of a traditional GaN device with a hybrid gate structure;
FIG. 3A illustrates a threshold voltage comparison dia- gram of the traditional GaN device and the traditional GaN device with the hybrid gate structure under …
FIG. 4 illustrates a structural diagram and an equivalent circuit diagram of a GaN power semiconductor device integrated with a self-feedback gate control …
FIG. 5B illustrates the regulation effect of the ratio on a turn-on voltage of a Schottky gate-contact type enhance- ment-mode GaN transistor in a gate control …
FIG. 6B illustrates an equivalent schematic diagram when V8a is less than the threshold of the Schottky gate-contact type enhancement-mode GaN transis- tor in …
FIG. 7B illustrates a gate leaking current comparison diagram of the invention, a traditional ohmic gate-contact type GaN device and the traditional Schottky …
FIG. 8B illustrates an equivalent schematic diagram when a negative voltage applied to a gate of a Schottky gate-contact type GaN transistor in an active …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN power semiconductor device integrated with a self-feedback gate control structure, structurally comprising: a substrate, a buffer layer, a channel layer and a barrier layer which are stacked from bottom to top, a heterojunction channel with a high electron mobility being generated between the channel layer and the barrier layer due to a polarization effect, and a gate control area and an active working area being disposed on an upper surface of the barrier layer; wherein, in the gate control area, a first metal source electrode, a first P-type GaN cap layer, a first metal drain electrode and a second P-type GaN cap layer are sequentially arranged on the upper surface of the bar-rier layer at intervals, wherein a first metal gate elec-trode is arranged on an upper surface of the first P-type GaN cap layer, a second metal gate electrode is arranged on an upper surface of the second P-type GaN B₁ cap layer, the first metal source electrode are connected through a first resistance region, the first P-type GaN cap layer and the second P-type GaN cap layer are connected through a second resistance region, and the first metal drain electrode and the second P-type GaN cap layer are connected through a third resistance region; in the active working area, the first metal source electrode, a third P-type GaN cap layer, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode are sequentially arranged on the upper surface of the barrier layer at intervals, wherein a third metal gate electrode is arranged on an upper surface of the third P-type GaN cap layer, and a second metal gate electrode is arranged on an upper surface of the second P-type GaN cap layer; the gate control area and the active working region share the first metal source electrode in the gate control area is connected with the third metal gate electrode in the active working area through a connecting metal, and the gate control area and the active working area share the second P-type GaN cap layer and the second metal gate electrode.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal gate electrode is in Schottky contact with the first P-type GaN cap layer, the second metal gate electrode is in Schottky contact with the second P-type GaN cap layer, the third metal gate electrode is in ohmic contact with the third P-type GaN cap layer, and the first metal source electrode, the second metal source electrode, the first metal drain electrode and the second metal drain electrode are in ohmic contact with the barrier layer.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal source electrode, the first metal gate electrode and the first metal drain electrode in the gate control area form a Schottky gate-contact type enhance-ment-mode GaN transistor; and the first metal source elec-trode, the third metal gate electrode and the second metal drain electrode in the active working area form an ohmic gate-contact type GaN transistor, and the second metal drain electrode, the second metal gate electrode and the second metal source electrode form a Schottky gate-contact type GaN transistor.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first resistance region, the second resistance region and the third resistance region are one or more of a high-electron mobility resistor, a dielectric resistor and a drift-region bulk resistor formed by the heterojunction chan-nel, and is in one or more of an S shape, a hollow-square shape and a linear shape.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein a resistance of the first resistance region, the second resistance region and the third resistance region is regulated by changing a length-width ratio of the resistance regions; the third resistance region is configured to regulate an overall leaking current of the device and has a resistance of 1 mΩ-1 kΩ; and a resistance ratio of the first resistance region to the second resistance region is used to regulate a turn-on voltage of a Schottky gate-contact type enhance-ment-mode GaN transistor in the gate control area to 9 decrease a gate voltage of the third metal gate electrode under a high gate voltage, thus realizing self-feedback control of a gate leakage.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal gate electrode and the second metal gate electrode in the gate control area adopt a same process, a gate width and gate length of the first metal gate electrode are 1 µm⁻¹⁰⁰ µm, and a gate length of the second metal gate electrode is 1000 µm⁻¹⁰⁰⁰⁰⁰ µm.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein a Schottky contact type depletion-mode GaN tran-sistor is formed in the gate control area. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN power semiconductor device integrated with self-feedback gate control structure
Materials described outside the worked examples.
GaN
AlGaN barrier layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A illustrates a threshold voltage comparison dia- gram of the traditional GaN device and the traditional GaN device with the hybrid gate structure under …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
third resistance region resistance range | 0.001–1000 | — |
first metal gate electrode gate width and gate length range | 1–100 | — |
second metal gate electrode gate length range |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,027,516 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a structural diagram and an equivalent circuit diagram of a traditional GaN device with a P-type 10 GaN cap layer;
FIG. 2 illustrates a structural diagram and an equivalent circuit diagram of a traditional GaN device with a hybrid gate structure;
FIG. 3A illustrates a threshold voltage comparison dia- gram of the traditional GaN device and the traditional GaN device with the hybrid gate structure under …
FIG. 4 illustrates a structural diagram and an equivalent circuit diagram of a GaN power semiconductor device integrated with a self-feedback gate control …
FIG. 5B illustrates the regulation effect of the ratio on a turn-on voltage of a Schottky gate-contact type enhance- ment-mode GaN transistor in a gate control …
FIG. 6B illustrates an equivalent schematic diagram when V8a is less than the threshold of the Schottky gate-contact type enhancement-mode GaN transis- tor in …
FIG. 7B illustrates a gate leaking current comparison diagram of the invention, a traditional ohmic gate-contact type GaN device and the traditional Schottky …
FIG. 8B illustrates an equivalent schematic diagram when a negative voltage applied to a gate of a Schottky gate-contact type GaN transistor in an active …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN power semiconductor device integrated with a self-feedback gate control structure, structurally comprising: a substrate, a buffer layer, a channel layer and a barrier layer which are stacked from bottom to top, a heterojunction channel with a high electron mobility being generated between the channel layer and the barrier layer due to a polarization effect, and a gate control area and an active working area being disposed on an upper surface of the barrier layer; wherein, in the gate control area, a first metal source electrode, a first P-type GaN cap layer, a first metal drain electrode and a second P-type GaN cap layer are sequentially arranged on the upper surface of the bar-rier layer at intervals, wherein a first metal gate elec-trode is arranged on an upper surface of the first P-type GaN cap layer, a second metal gate electrode is arranged on an upper surface of the second P-type GaN B₁ cap layer, the first metal source electrode are connected through a first resistance region, the first P-type GaN cap layer and the second P-type GaN cap layer are connected through a second resistance region, and the first metal drain electrode and the second P-type GaN cap layer are connected through a third resistance region; in the active working area, the first metal source electrode, a third P-type GaN cap layer, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode are sequentially arranged on the upper surface of the barrier layer at intervals, wherein a third metal gate electrode is arranged on an upper surface of the third P-type GaN cap layer, and a second metal gate electrode is arranged on an upper surface of the second P-type GaN cap layer; the gate control area and the active working region share the first metal source electrode in the gate control area is connected with the third metal gate electrode in the active working area through a connecting metal, and the gate control area and the active working area share the second P-type GaN cap layer and the second metal gate electrode.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal gate electrode is in Schottky contact with the first P-type GaN cap layer, the second metal gate electrode is in Schottky contact with the second P-type GaN cap layer, the third metal gate electrode is in ohmic contact with the third P-type GaN cap layer, and the first metal source electrode, the second metal source electrode, the first metal drain electrode and the second metal drain electrode are in ohmic contact with the barrier layer.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal source electrode, the first metal gate electrode and the first metal drain electrode in the gate control area form a Schottky gate-contact type enhance-ment-mode GaN transistor; and the first metal source elec-trode, the third metal gate electrode and the second metal drain electrode in the active working area form an ohmic gate-contact type GaN transistor, and the second metal drain electrode, the second metal gate electrode and the second metal source electrode form a Schottky gate-contact type GaN transistor.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first resistance region, the second resistance region and the third resistance region are one or more of a high-electron mobility resistor, a dielectric resistor and a drift-region bulk resistor formed by the heterojunction chan-nel, and is in one or more of an S shape, a hollow-square shape and a linear shape.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein a resistance of the first resistance region, the second resistance region and the third resistance region is regulated by changing a length-width ratio of the resistance regions; the third resistance region is configured to regulate an overall leaking current of the device and has a resistance of 1 mΩ-1 kΩ; and a resistance ratio of the first resistance region to the second resistance region is used to regulate a turn-on voltage of a Schottky gate-contact type enhance-ment-mode GaN transistor in the gate control area to 9 decrease a gate voltage of the third metal gate electrode under a high gate voltage, thus realizing self-feedback control of a gate leakage.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal gate electrode and the second metal gate electrode in the gate control area adopt a same process, a gate width and gate length of the first metal gate electrode are 1 µm⁻¹⁰⁰ µm, and a gate length of the second metal gate electrode is 1000 µm⁻¹⁰⁰⁰⁰⁰ µm.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein a Schottky contact type depletion-mode GaN tran-sistor is formed in the gate control area. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN power semiconductor device integrated with self-feedback gate control structure
Materials described outside the worked examples.
GaN
AlGaN barrier layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A illustrates a threshold voltage comparison dia- gram of the traditional GaN device and the traditional GaN device with the hybrid gate structure under …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
third resistance region resistance range | 0.001–1000 | — |
first metal gate electrode gate width and gate length range | 1–100 | — |
second metal gate electrode gate length range |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,027,516 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a structural diagram and an equivalent circuit diagram of a traditional GaN device with a P-type 10 GaN cap layer;
FIG. 2 illustrates a structural diagram and an equivalent circuit diagram of a traditional GaN device with a hybrid gate structure;
FIG. 3A illustrates a threshold voltage comparison dia- gram of the traditional GaN device and the traditional GaN device with the hybrid gate structure under …
FIG. 4 illustrates a structural diagram and an equivalent circuit diagram of a GaN power semiconductor device integrated with a self-feedback gate control …
FIG. 5B illustrates the regulation effect of the ratio on a turn-on voltage of a Schottky gate-contact type enhance- ment-mode GaN transistor in a gate control …
FIG. 6B illustrates an equivalent schematic diagram when V8a is less than the threshold of the Schottky gate-contact type enhancement-mode GaN transis- tor in …
FIG. 7B illustrates a gate leaking current comparison diagram of the invention, a traditional ohmic gate-contact type GaN device and the traditional Schottky …
FIG. 8B illustrates an equivalent schematic diagram when a negative voltage applied to a gate of a Schottky gate-contact type GaN transistor in an active …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN power semiconductor device integrated with a self-feedback gate control structure, structurally comprising: a substrate, a buffer layer, a channel layer and a barrier layer which are stacked from bottom to top, a heterojunction channel with a high electron mobility being generated between the channel layer and the barrier layer due to a polarization effect, and a gate control area and an active working area being disposed on an upper surface of the barrier layer; wherein, in the gate control area, a first metal source electrode, a first P-type GaN cap layer, a first metal drain electrode and a second P-type GaN cap layer are sequentially arranged on the upper surface of the bar-rier layer at intervals, wherein a first metal gate elec-trode is arranged on an upper surface of the first P-type GaN cap layer, a second metal gate electrode is arranged on an upper surface of the second P-type GaN B₁ cap layer, the first metal source electrode are connected through a first resistance region, the first P-type GaN cap layer and the second P-type GaN cap layer are connected through a second resistance region, and the first metal drain electrode and the second P-type GaN cap layer are connected through a third resistance region; in the active working area, the first metal source electrode, a third P-type GaN cap layer, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode are sequentially arranged on the upper surface of the barrier layer at intervals, wherein a third metal gate electrode is arranged on an upper surface of the third P-type GaN cap layer, and a second metal gate electrode is arranged on an upper surface of the second P-type GaN cap layer; the gate control area and the active working region share the first metal source electrode in the gate control area is connected with the third metal gate electrode in the active working area through a connecting metal, and the gate control area and the active working area share the second P-type GaN cap layer and the second metal gate electrode.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal gate electrode is in Schottky contact with the first P-type GaN cap layer, the second metal gate electrode is in Schottky contact with the second P-type GaN cap layer, the third metal gate electrode is in ohmic contact with the third P-type GaN cap layer, and the first metal source electrode, the second metal source electrode, the first metal drain electrode and the second metal drain electrode are in ohmic contact with the barrier layer.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal source electrode, the first metal gate electrode and the first metal drain electrode in the gate control area form a Schottky gate-contact type enhance-ment-mode GaN transistor; and the first metal source elec-trode, the third metal gate electrode and the second metal drain electrode in the active working area form an ohmic gate-contact type GaN transistor, and the second metal drain electrode, the second metal gate electrode and the second metal source electrode form a Schottky gate-contact type GaN transistor.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first resistance region, the second resistance region and the third resistance region are one or more of a high-electron mobility resistor, a dielectric resistor and a drift-region bulk resistor formed by the heterojunction chan-nel, and is in one or more of an S shape, a hollow-square shape and a linear shape.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein a resistance of the first resistance region, the second resistance region and the third resistance region is regulated by changing a length-width ratio of the resistance regions; the third resistance region is configured to regulate an overall leaking current of the device and has a resistance of 1 mΩ-1 kΩ; and a resistance ratio of the first resistance region to the second resistance region is used to regulate a turn-on voltage of a Schottky gate-contact type enhance-ment-mode GaN transistor in the gate control area to 9 decrease a gate voltage of the third metal gate electrode under a high gate voltage, thus realizing self-feedback control of a gate leakage.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal gate electrode and the second metal gate electrode in the gate control area adopt a same process, a gate width and gate length of the first metal gate electrode are 1 µm⁻¹⁰⁰ µm, and a gate length of the second metal gate electrode is 1000 µm⁻¹⁰⁰⁰⁰⁰ µm.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein a Schottky contact type depletion-mode GaN tran-sistor is formed in the gate control area. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN power semiconductor device integrated with self-feedback gate control structure
Materials described outside the worked examples.
GaN
AlGaN barrier layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A illustrates a threshold voltage comparison dia- gram of the traditional GaN device and the traditional GaN device with the hybrid gate structure under …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
third resistance region resistance range | 0.001–1000 | — |
first metal gate electrode gate width and gate length range | 1–100 | — |
second metal gate electrode gate length range |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,027,516 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a structural diagram and an equivalent circuit diagram of a traditional GaN device with a P-type 10 GaN cap layer;
FIG. 2 illustrates a structural diagram and an equivalent circuit diagram of a traditional GaN device with a hybrid gate structure;
FIG. 3A illustrates a threshold voltage comparison dia- gram of the traditional GaN device and the traditional GaN device with the hybrid gate structure under …
FIG. 4 illustrates a structural diagram and an equivalent circuit diagram of a GaN power semiconductor device integrated with a self-feedback gate control …
FIG. 5B illustrates the regulation effect of the ratio on a turn-on voltage of a Schottky gate-contact type enhance- ment-mode GaN transistor in a gate control …
FIG. 6B illustrates an equivalent schematic diagram when V8a is less than the threshold of the Schottky gate-contact type enhancement-mode GaN transis- tor in …
FIG. 7B illustrates a gate leaking current comparison diagram of the invention, a traditional ohmic gate-contact type GaN device and the traditional Schottky …
FIG. 8B illustrates an equivalent schematic diagram when a negative voltage applied to a gate of a Schottky gate-contact type GaN transistor in an active …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN power semiconductor device integrated with a self-feedback gate control structure, structurally comprising: a substrate, a buffer layer, a channel layer and a barrier layer which are stacked from bottom to top, a heterojunction channel with a high electron mobility being generated between the channel layer and the barrier layer due to a polarization effect, and a gate control area and an active working area being disposed on an upper surface of the barrier layer; wherein, in the gate control area, a first metal source electrode, a first P-type GaN cap layer, a first metal drain electrode and a second P-type GaN cap layer are sequentially arranged on the upper surface of the bar-rier layer at intervals, wherein a first metal gate elec-trode is arranged on an upper surface of the first P-type GaN cap layer, a second metal gate electrode is arranged on an upper surface of the second P-type GaN B₁ cap layer, the first metal source electrode are connected through a first resistance region, the first P-type GaN cap layer and the second P-type GaN cap layer are connected through a second resistance region, and the first metal drain electrode and the second P-type GaN cap layer are connected through a third resistance region; in the active working area, the first metal source electrode, a third P-type GaN cap layer, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode are sequentially arranged on the upper surface of the barrier layer at intervals, wherein a third metal gate electrode is arranged on an upper surface of the third P-type GaN cap layer, and a second metal gate electrode is arranged on an upper surface of the second P-type GaN cap layer; the gate control area and the active working region share the first metal source electrode in the gate control area is connected with the third metal gate electrode in the active working area through a connecting metal, and the gate control area and the active working area share the second P-type GaN cap layer and the second metal gate electrode.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal gate electrode is in Schottky contact with the first P-type GaN cap layer, the second metal gate electrode is in Schottky contact with the second P-type GaN cap layer, the third metal gate electrode is in ohmic contact with the third P-type GaN cap layer, and the first metal source electrode, the second metal source electrode, the first metal drain electrode and the second metal drain electrode are in ohmic contact with the barrier layer.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal source electrode, the first metal gate electrode and the first metal drain electrode in the gate control area form a Schottky gate-contact type enhance-ment-mode GaN transistor; and the first metal source elec-trode, the third metal gate electrode and the second metal drain electrode in the active working area form an ohmic gate-contact type GaN transistor, and the second metal drain electrode, the second metal gate electrode and the second metal source electrode form a Schottky gate-contact type GaN transistor.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first resistance region, the second resistance region and the third resistance region are one or more of a high-electron mobility resistor, a dielectric resistor and a drift-region bulk resistor formed by the heterojunction chan-nel, and is in one or more of an S shape, a hollow-square shape and a linear shape.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein a resistance of the first resistance region, the second resistance region and the third resistance region is regulated by changing a length-width ratio of the resistance regions; the third resistance region is configured to regulate an overall leaking current of the device and has a resistance of 1 mΩ-1 kΩ; and a resistance ratio of the first resistance region to the second resistance region is used to regulate a turn-on voltage of a Schottky gate-contact type enhance-ment-mode GaN transistor in the gate control area to 9 decrease a gate voltage of the third metal gate electrode under a high gate voltage, thus realizing self-feedback control of a gate leakage.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein the first metal gate electrode and the second metal gate electrode in the gate control area adopt a same process, a gate width and gate length of the first metal gate electrode are 1 µm⁻¹⁰⁰ µm, and a gate length of the second metal gate electrode is 1000 µm⁻¹⁰⁰⁰⁰⁰ µm.
The GaN power semiconductor device integrated with the self-feedback gate control structure according to claim 1, wherein a Schottky contact type depletion-mode GaN tran-sistor is formed in the gate control area. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN power semiconductor device integrated with self-feedback gate control structure
Materials described outside the worked examples.
GaN
AlGaN barrier layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A illustrates a threshold voltage comparison dia- gram of the traditional GaN device and the traditional GaN device with the hybrid gate structure under …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
third resistance region resistance range | 0.001–1000 | — |
first metal gate electrode gate width and gate length range | 1–100 | — |
second metal gate electrode gate length range |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Schottky gate-contact type enhancement-mode GaN transistor (gate control area)
No layer stack recorded.
ohmic gate-contact type GaN transistor (active working area)
No layer stack recorded.
Schottky gate-contact type GaN transistor (active working area)
No layer stack recorded.
Schottky contact type depletion-mode GaN transistor (gate control area)
No layer stack recorded.
AlGaN/GaN heterojunction channel (2DEG)
FIG. 5B illustrates the regulation effect of the ratio on a turn-on voltage of a Schottky gate-contact type enhance- ment-mode GaN transistor in a gate control …
FIG. 6B illustrates an equivalent schematic diagram when V8a is less than the threshold of the Schottky gate-contact type enhancement-mode GaN transis- tor in …
FIG. 7B illustrates a gate leaking current comparison diagram of the invention, a traditional ohmic gate-contact type GaN device and the traditional Schottky …
FIG. 8B illustrates an equivalent schematic diagram when a negative voltage applied to a gate of a Schottky gate-contact type GaN transistor in an active …
| 1000–100000 |
| — |
Schottky gate-contact type enhancement-mode GaN transistor (gate control area)
No layer stack recorded.
ohmic gate-contact type GaN transistor (active working area)
No layer stack recorded.
Schottky gate-contact type GaN transistor (active working area)
No layer stack recorded.
Schottky contact type depletion-mode GaN transistor (gate control area)
No layer stack recorded.
AlGaN/GaN heterojunction channel (2DEG)
FIG. 5B illustrates the regulation effect of the ratio on a turn-on voltage of a Schottky gate-contact type enhance- ment-mode GaN transistor in a gate control …
FIG. 6B illustrates an equivalent schematic diagram when V8a is less than the threshold of the Schottky gate-contact type enhancement-mode GaN transis- tor in …
FIG. 7B illustrates a gate leaking current comparison diagram of the invention, a traditional ohmic gate-contact type GaN device and the traditional Schottky …
FIG. 8B illustrates an equivalent schematic diagram when a negative voltage applied to a gate of a Schottky gate-contact type GaN transistor in an active …
| 1000–100000 |
| — |
Schottky gate-contact type enhancement-mode GaN transistor (gate control area)
No layer stack recorded.
ohmic gate-contact type GaN transistor (active working area)
No layer stack recorded.
Schottky gate-contact type GaN transistor (active working area)
No layer stack recorded.
Schottky contact type depletion-mode GaN transistor (gate control area)
No layer stack recorded.
AlGaN/GaN heterojunction channel (2DEG)
FIG. 5B illustrates the regulation effect of the ratio on a turn-on voltage of a Schottky gate-contact type enhance- ment-mode GaN transistor in a gate control …
FIG. 6B illustrates an equivalent schematic diagram when V8a is less than the threshold of the Schottky gate-contact type enhancement-mode GaN transis- tor in …
FIG. 7B illustrates a gate leaking current comparison diagram of the invention, a traditional ohmic gate-contact type GaN device and the traditional Schottky …
FIG. 8B illustrates an equivalent schematic diagram when a negative voltage applied to a gate of a Schottky gate-contact type GaN transistor in an active …
| 1000–100000 |
| — |
Schottky gate-contact type enhancement-mode GaN transistor (gate control area)
No layer stack recorded.
ohmic gate-contact type GaN transistor (active working area)
No layer stack recorded.
Schottky gate-contact type GaN transistor (active working area)
No layer stack recorded.
Schottky contact type depletion-mode GaN transistor (gate control area)
No layer stack recorded.
AlGaN/GaN heterojunction channel (2DEG)
FIG. 5B illustrates the regulation effect of the ratio on a turn-on voltage of a Schottky gate-contact type enhance- ment-mode GaN transistor in a gate control …
FIG. 6B illustrates an equivalent schematic diagram when V8a is less than the threshold of the Schottky gate-contact type enhancement-mode GaN transis- tor in …
FIG. 7B illustrates a gate leaking current comparison diagram of the invention, a traditional ohmic gate-contact type GaN device and the traditional Schottky …
FIG. 8B illustrates an equivalent schematic diagram when a negative voltage applied to a gate of a Schottky gate-contact type GaN transistor in an active …
| 1000–100000 |
| — |
