Patent
US 10,680,069SYSTEM AND METHOD FOR A GAN-BASED START-UP CIRCUIT
Oliver Haeberlen
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 10,680,069Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A illustrates a schematic of an embodiment start-up circuit;
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
Figures 1C and 1D illustrate waveform diagrams demonstrating the operation of the embodiment start-up circuit of
Figure 2 illustrates a schematic of a start-up circuit according to an alternative embodiment;
Figure 3 illustrates a schematic diagram of an embodiment gate drive system;
Figures 4A and 4B illustrate schematic diagrams of a switched-mode power converters that incorporate embodiment start-up circuits;
Figures 5 illustrates a schematic cross-section of an embodiment GaN enhancement mode transistor cell;
Figures 6A, 6B and 6C illustrate schematic cross-sections of embodiment GaN depletion mode transistor cells; and
Figure 7 illustrates a layout view of an embodiment start-up circuit cell. [001 6] Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments …
Figure 1 D and described further below. Once the voltage is applied to drain node VD, the voltage of power supply node VDD starts increasing due to capacitor C being charged via the load path of normally-on start-up transistor M2. The voltage of power supply VDD increases to a voltage of -V T M2, …
Figure 1. Normally-off switch transistor M i, normally-on start-up transistors M₂A and M₂B and diode D₃ may be implemented on a single semiconductor substrate and/or package 202. However, in alternative embodiments, the various components shown in
Figure 4B, which shows a switched-mode power converter 450 that incorporates an embodiment start-up circuit 102. Similar to switched-mode power converter 40 0 depicted in
Figure 6B illustrates a schematic cross section of a GaN depletion mode transistor cell 620 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6C illustrates a schematic cross section of a GaN depletion mode transistor cell 640 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6. [0062] As shown, the drain metallization for both transistors M i and M₂ coupled to drain node VD is represented by layer 702; the source metallization for transistor M i coupled to ground node GND is represented by layer 704, the gate layer for transistor M i coupled to gate node VG is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Withdrawn-Currently Amended) A method of starting a circuit, the method comprising: receiving a first voltage at a drain node of a start-up circuit comprising a first gallium nitride (GaN) transistor having a drain coupled to the drain node, a source coupled to a source node, and a gate coupled to a gate node, a second GaN transistor having a drain coupled to the drain node, a source, and a gate coupled to a reference node, wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device, and a first capacitor coupled to a source of the second GaN transistor at a power source node; charging the first capacitor via the second GaN transistor; providing energy from the first capacitor to a driver circuit coupled to a gate of the first GaN transistor; and turning-off the second GaN transistor when a voltage of the first capacitor reaches a threshold. Currently amended
The method of claim 1, further comprising providing, by the driver circuit, a switching signal to the gate of the first GaN transistor. Withdrawn
The method of claim 1, wherein the first GaN transistor is shut-off prior to receiving the first voltage. Withdrawn
The method of claim 1, further comprising: providing power to a primary winding of a transformer, wherein the primary winding of the transformer is coupled to the drain node of the start-up circuit; and transferring power from an auxiliary winding of the transformer to the driver circuit after turning-off the second GaN transistor. Withdrawn
The method of claim 1, wherein the first GaN transistor and the second GaN transistor are integrated on a single semiconductor substrate. Withdrawn
The method of claim 1, wherein the start-up circuit further comprises: a third GaN transistor having a drain coupled to the gate of the second GaN transistor and to the first capacitor, and a gate coupled to the reference node, wherein the gate of the second GaN transistor is coupled to the reference node via a load path of the third GaN transistor; and a second capacitor coupled between a source of the third GaN transistor and the reference node. Withdrawn
Canceled
A circuit comprising: a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, and a source coupled to a first power source node configured to be coupled to a first capacitor, wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device. Currently amended
The circuit of claim 8, wherein the second GaN transistor comprises a gate coupled to the source node. Original
10. The circuit of claim 8, wherein the first GaN transistor and the second GaN transistor are integrated on a same semiconductor substrate. Original
The circuit of claim 8, further comprising a gate driving circuit having a power supply input coupled to the first power source node and an output coupled to the gate node. Original
1 8. The circuit of claim 8, further comprising a transformer having a first winding coupled to the drain node and an auxiliary winding coupled to the first power source node. Original
The circuit of claim 8, further comprising a third GaN transistor comprising a drain coupled to a gate of the second GaN transistor and to a second power source node configured to be coupled to the first capacitor, a source coupled to a third power source node configured to be coupled to a second capacitor, and a gate coupled to the source node. Original
Canceled
The circuit of claim [[11,]] wherein: the gate of the first GaN transistor comprises a fully recessed gate comprising a p-doped GaN material on top of a second A l GaN layer that extends through a first A l GaN layer, wherein the first A l GaN layer is disposed over a channel layer comprising undoped GaN material. Currently amended
The circuit of claim 12, wherein the gate of the second GaN transistor is disposed over surfaces of the first and second A l GaN layers without extending through the first AlGaN layer. Original
The circuit of claim 12, wherein the gate of the second GaN transistor comprises the p-doped GaN material. Original
The circuit of claim [[1 1,]] 8 wherein the gate of the second GaN transistor comprises a Scho t tky gate. Currently amended
1 6. The circuit of claim 15, further comprising a dielectric layer disposed between the gate of the second GaN transistor and a first A l GaN layer, wherein a threshold of the second GaN transistor is proportional to a thickness of the dielectric layer. Original
A switched-mode power supply comprising: an integrated circuit comprising a first gallium nitride (GaN) transistor having a drain coupled to a drain node and a source coupled to a reference node, a second GaN transistor having a drain coupled to the drain node and a gate coupled to the reference node, wherein the first GaN transistor and the second GaN transistor are disposed on a same semiconductor substrate, and wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device; a capacitor coupled to a source of the second GaN transistor; and a driver circuit comprising a gate driver output coupled to a gate of the first GaN transistor, and a power supply input coupled to the capacitor. Currently amended
The switched-mode power supply of claim 21, further comprising: a transformer having a primary winding coupled to the drain node of the integrated circuit and an auxiliary winding coupled to the capacitor; and a diode coupled between the auxiliary winding and the capacitor. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based start-up circuit (method claim)
No layer stack recorded.
GaN start-up circuit with normally-off and normally-on transistors
No layer stack recorded.
GaN transistor with fully recessed p-GaN gate on AlGaN/GaN stack
switched-mode power supply with integrated GaN IC
No layer stack recorded.
Materials described outside the worked examples.
first GaN transistor (normally-off)
GaN
first AlGaN layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
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US 10,680,069Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A illustrates a schematic of an embodiment start-up circuit;
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
Figures 1C and 1D illustrate waveform diagrams demonstrating the operation of the embodiment start-up circuit of
Figure 2 illustrates a schematic of a start-up circuit according to an alternative embodiment;
Figure 3 illustrates a schematic diagram of an embodiment gate drive system;
Figures 4A and 4B illustrate schematic diagrams of a switched-mode power converters that incorporate embodiment start-up circuits;
Figures 5 illustrates a schematic cross-section of an embodiment GaN enhancement mode transistor cell;
Figures 6A, 6B and 6C illustrate schematic cross-sections of embodiment GaN depletion mode transistor cells; and
Figure 7 illustrates a layout view of an embodiment start-up circuit cell. [001 6] Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments …
Figure 1 D and described further below. Once the voltage is applied to drain node VD, the voltage of power supply node VDD starts increasing due to capacitor C being charged via the load path of normally-on start-up transistor M2. The voltage of power supply VDD increases to a voltage of -V T M2, …
Figure 1. Normally-off switch transistor M i, normally-on start-up transistors M₂A and M₂B and diode D₃ may be implemented on a single semiconductor substrate and/or package 202. However, in alternative embodiments, the various components shown in
Figure 4B, which shows a switched-mode power converter 450 that incorporates an embodiment start-up circuit 102. Similar to switched-mode power converter 40 0 depicted in
Figure 6B illustrates a schematic cross section of a GaN depletion mode transistor cell 620 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6C illustrates a schematic cross section of a GaN depletion mode transistor cell 640 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6. [0062] As shown, the drain metallization for both transistors M i and M₂ coupled to drain node VD is represented by layer 702; the source metallization for transistor M i coupled to ground node GND is represented by layer 704, the gate layer for transistor M i coupled to gate node VG is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Withdrawn-Currently Amended) A method of starting a circuit, the method comprising: receiving a first voltage at a drain node of a start-up circuit comprising a first gallium nitride (GaN) transistor having a drain coupled to the drain node, a source coupled to a source node, and a gate coupled to a gate node, a second GaN transistor having a drain coupled to the drain node, a source, and a gate coupled to a reference node, wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device, and a first capacitor coupled to a source of the second GaN transistor at a power source node; charging the first capacitor via the second GaN transistor; providing energy from the first capacitor to a driver circuit coupled to a gate of the first GaN transistor; and turning-off the second GaN transistor when a voltage of the first capacitor reaches a threshold. Currently amended
The method of claim 1, further comprising providing, by the driver circuit, a switching signal to the gate of the first GaN transistor. Withdrawn
The method of claim 1, wherein the first GaN transistor is shut-off prior to receiving the first voltage. Withdrawn
The method of claim 1, further comprising: providing power to a primary winding of a transformer, wherein the primary winding of the transformer is coupled to the drain node of the start-up circuit; and transferring power from an auxiliary winding of the transformer to the driver circuit after turning-off the second GaN transistor. Withdrawn
The method of claim 1, wherein the first GaN transistor and the second GaN transistor are integrated on a single semiconductor substrate. Withdrawn
The method of claim 1, wherein the start-up circuit further comprises: a third GaN transistor having a drain coupled to the gate of the second GaN transistor and to the first capacitor, and a gate coupled to the reference node, wherein the gate of the second GaN transistor is coupled to the reference node via a load path of the third GaN transistor; and a second capacitor coupled between a source of the third GaN transistor and the reference node. Withdrawn
Canceled
A circuit comprising: a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, and a source coupled to a first power source node configured to be coupled to a first capacitor, wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device. Currently amended
The circuit of claim 8, wherein the second GaN transistor comprises a gate coupled to the source node. Original
10. The circuit of claim 8, wherein the first GaN transistor and the second GaN transistor are integrated on a same semiconductor substrate. Original
The circuit of claim 8, further comprising a gate driving circuit having a power supply input coupled to the first power source node and an output coupled to the gate node. Original
1 8. The circuit of claim 8, further comprising a transformer having a first winding coupled to the drain node and an auxiliary winding coupled to the first power source node. Original
The circuit of claim 8, further comprising a third GaN transistor comprising a drain coupled to a gate of the second GaN transistor and to a second power source node configured to be coupled to the first capacitor, a source coupled to a third power source node configured to be coupled to a second capacitor, and a gate coupled to the source node. Original
Canceled
The circuit of claim [[11,]] wherein: the gate of the first GaN transistor comprises a fully recessed gate comprising a p-doped GaN material on top of a second A l GaN layer that extends through a first A l GaN layer, wherein the first A l GaN layer is disposed over a channel layer comprising undoped GaN material. Currently amended
The circuit of claim 12, wherein the gate of the second GaN transistor is disposed over surfaces of the first and second A l GaN layers without extending through the first AlGaN layer. Original
The circuit of claim 12, wherein the gate of the second GaN transistor comprises the p-doped GaN material. Original
The circuit of claim [[1 1,]] 8 wherein the gate of the second GaN transistor comprises a Scho t tky gate. Currently amended
1 6. The circuit of claim 15, further comprising a dielectric layer disposed between the gate of the second GaN transistor and a first A l GaN layer, wherein a threshold of the second GaN transistor is proportional to a thickness of the dielectric layer. Original
A switched-mode power supply comprising: an integrated circuit comprising a first gallium nitride (GaN) transistor having a drain coupled to a drain node and a source coupled to a reference node, a second GaN transistor having a drain coupled to the drain node and a gate coupled to the reference node, wherein the first GaN transistor and the second GaN transistor are disposed on a same semiconductor substrate, and wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device; a capacitor coupled to a source of the second GaN transistor; and a driver circuit comprising a gate driver output coupled to a gate of the first GaN transistor, and a power supply input coupled to the capacitor. Currently amended
The switched-mode power supply of claim 21, further comprising: a transformer having a primary winding coupled to the drain node of the integrated circuit and an auxiliary winding coupled to the capacitor; and a diode coupled between the auxiliary winding and the capacitor. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based start-up circuit (method claim)
No layer stack recorded.
GaN start-up circuit with normally-off and normally-on transistors
No layer stack recorded.
GaN transistor with fully recessed p-GaN gate on AlGaN/GaN stack
switched-mode power supply with integrated GaN IC
No layer stack recorded.
Materials described outside the worked examples.
first GaN transistor (normally-off)
GaN
first AlGaN layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
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US 10,680,069Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A illustrates a schematic of an embodiment start-up circuit;
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
Figures 1C and 1D illustrate waveform diagrams demonstrating the operation of the embodiment start-up circuit of
Figure 2 illustrates a schematic of a start-up circuit according to an alternative embodiment;
Figure 3 illustrates a schematic diagram of an embodiment gate drive system;
Figures 4A and 4B illustrate schematic diagrams of a switched-mode power converters that incorporate embodiment start-up circuits;
Figures 5 illustrates a schematic cross-section of an embodiment GaN enhancement mode transistor cell;
Figures 6A, 6B and 6C illustrate schematic cross-sections of embodiment GaN depletion mode transistor cells; and
Figure 7 illustrates a layout view of an embodiment start-up circuit cell. [001 6] Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments …
Figure 1 D and described further below. Once the voltage is applied to drain node VD, the voltage of power supply node VDD starts increasing due to capacitor C being charged via the load path of normally-on start-up transistor M2. The voltage of power supply VDD increases to a voltage of -V T M2, …
Figure 1. Normally-off switch transistor M i, normally-on start-up transistors M₂A and M₂B and diode D₃ may be implemented on a single semiconductor substrate and/or package 202. However, in alternative embodiments, the various components shown in
Figure 4B, which shows a switched-mode power converter 450 that incorporates an embodiment start-up circuit 102. Similar to switched-mode power converter 40 0 depicted in
Figure 6B illustrates a schematic cross section of a GaN depletion mode transistor cell 620 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6C illustrates a schematic cross section of a GaN depletion mode transistor cell 640 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6. [0062] As shown, the drain metallization for both transistors M i and M₂ coupled to drain node VD is represented by layer 702; the source metallization for transistor M i coupled to ground node GND is represented by layer 704, the gate layer for transistor M i coupled to gate node VG is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Withdrawn-Currently Amended) A method of starting a circuit, the method comprising: receiving a first voltage at a drain node of a start-up circuit comprising a first gallium nitride (GaN) transistor having a drain coupled to the drain node, a source coupled to a source node, and a gate coupled to a gate node, a second GaN transistor having a drain coupled to the drain node, a source, and a gate coupled to a reference node, wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device, and a first capacitor coupled to a source of the second GaN transistor at a power source node; charging the first capacitor via the second GaN transistor; providing energy from the first capacitor to a driver circuit coupled to a gate of the first GaN transistor; and turning-off the second GaN transistor when a voltage of the first capacitor reaches a threshold. Currently amended
The method of claim 1, further comprising providing, by the driver circuit, a switching signal to the gate of the first GaN transistor. Withdrawn
The method of claim 1, wherein the first GaN transistor is shut-off prior to receiving the first voltage. Withdrawn
The method of claim 1, further comprising: providing power to a primary winding of a transformer, wherein the primary winding of the transformer is coupled to the drain node of the start-up circuit; and transferring power from an auxiliary winding of the transformer to the driver circuit after turning-off the second GaN transistor. Withdrawn
The method of claim 1, wherein the first GaN transistor and the second GaN transistor are integrated on a single semiconductor substrate. Withdrawn
The method of claim 1, wherein the start-up circuit further comprises: a third GaN transistor having a drain coupled to the gate of the second GaN transistor and to the first capacitor, and a gate coupled to the reference node, wherein the gate of the second GaN transistor is coupled to the reference node via a load path of the third GaN transistor; and a second capacitor coupled between a source of the third GaN transistor and the reference node. Withdrawn
Canceled
A circuit comprising: a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, and a source coupled to a first power source node configured to be coupled to a first capacitor, wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device. Currently amended
The circuit of claim 8, wherein the second GaN transistor comprises a gate coupled to the source node. Original
10. The circuit of claim 8, wherein the first GaN transistor and the second GaN transistor are integrated on a same semiconductor substrate. Original
The circuit of claim 8, further comprising a gate driving circuit having a power supply input coupled to the first power source node and an output coupled to the gate node. Original
1 8. The circuit of claim 8, further comprising a transformer having a first winding coupled to the drain node and an auxiliary winding coupled to the first power source node. Original
The circuit of claim 8, further comprising a third GaN transistor comprising a drain coupled to a gate of the second GaN transistor and to a second power source node configured to be coupled to the first capacitor, a source coupled to a third power source node configured to be coupled to a second capacitor, and a gate coupled to the source node. Original
Canceled
The circuit of claim [[11,]] wherein: the gate of the first GaN transistor comprises a fully recessed gate comprising a p-doped GaN material on top of a second A l GaN layer that extends through a first A l GaN layer, wherein the first A l GaN layer is disposed over a channel layer comprising undoped GaN material. Currently amended
The circuit of claim 12, wherein the gate of the second GaN transistor is disposed over surfaces of the first and second A l GaN layers without extending through the first AlGaN layer. Original
The circuit of claim 12, wherein the gate of the second GaN transistor comprises the p-doped GaN material. Original
The circuit of claim [[1 1,]] 8 wherein the gate of the second GaN transistor comprises a Scho t tky gate. Currently amended
1 6. The circuit of claim 15, further comprising a dielectric layer disposed between the gate of the second GaN transistor and a first A l GaN layer, wherein a threshold of the second GaN transistor is proportional to a thickness of the dielectric layer. Original
A switched-mode power supply comprising: an integrated circuit comprising a first gallium nitride (GaN) transistor having a drain coupled to a drain node and a source coupled to a reference node, a second GaN transistor having a drain coupled to the drain node and a gate coupled to the reference node, wherein the first GaN transistor and the second GaN transistor are disposed on a same semiconductor substrate, and wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device; a capacitor coupled to a source of the second GaN transistor; and a driver circuit comprising a gate driver output coupled to a gate of the first GaN transistor, and a power supply input coupled to the capacitor. Currently amended
The switched-mode power supply of claim 21, further comprising: a transformer having a primary winding coupled to the drain node of the integrated circuit and an auxiliary winding coupled to the capacitor; and a diode coupled between the auxiliary winding and the capacitor. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based start-up circuit (method claim)
No layer stack recorded.
GaN start-up circuit with normally-off and normally-on transistors
No layer stack recorded.
GaN transistor with fully recessed p-GaN gate on AlGaN/GaN stack
switched-mode power supply with integrated GaN IC
No layer stack recorded.
Materials described outside the worked examples.
first GaN transistor (normally-off)
GaN
first AlGaN layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
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Atlas literature
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US 10,680,069Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A illustrates a schematic of an embodiment start-up circuit;
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
Figures 1C and 1D illustrate waveform diagrams demonstrating the operation of the embodiment start-up circuit of
Figure 2 illustrates a schematic of a start-up circuit according to an alternative embodiment;
Figure 3 illustrates a schematic diagram of an embodiment gate drive system;
Figures 4A and 4B illustrate schematic diagrams of a switched-mode power converters that incorporate embodiment start-up circuits;
Figures 5 illustrates a schematic cross-section of an embodiment GaN enhancement mode transistor cell;
Figures 6A, 6B and 6C illustrate schematic cross-sections of embodiment GaN depletion mode transistor cells; and
Figure 7 illustrates a layout view of an embodiment start-up circuit cell. [001 6] Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments …
Figure 1 D and described further below. Once the voltage is applied to drain node VD, the voltage of power supply node VDD starts increasing due to capacitor C being charged via the load path of normally-on start-up transistor M2. The voltage of power supply VDD increases to a voltage of -V T M2, …
Figure 1. Normally-off switch transistor M i, normally-on start-up transistors M₂A and M₂B and diode D₃ may be implemented on a single semiconductor substrate and/or package 202. However, in alternative embodiments, the various components shown in
Figure 4B, which shows a switched-mode power converter 450 that incorporates an embodiment start-up circuit 102. Similar to switched-mode power converter 40 0 depicted in
Figure 6B illustrates a schematic cross section of a GaN depletion mode transistor cell 620 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6C illustrates a schematic cross section of a GaN depletion mode transistor cell 640 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6. [0062] As shown, the drain metallization for both transistors M i and M₂ coupled to drain node VD is represented by layer 702; the source metallization for transistor M i coupled to ground node GND is represented by layer 704, the gate layer for transistor M i coupled to gate node VG is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Withdrawn-Currently Amended) A method of starting a circuit, the method comprising: receiving a first voltage at a drain node of a start-up circuit comprising a first gallium nitride (GaN) transistor having a drain coupled to the drain node, a source coupled to a source node, and a gate coupled to a gate node, a second GaN transistor having a drain coupled to the drain node, a source, and a gate coupled to a reference node, wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device, and a first capacitor coupled to a source of the second GaN transistor at a power source node; charging the first capacitor via the second GaN transistor; providing energy from the first capacitor to a driver circuit coupled to a gate of the first GaN transistor; and turning-off the second GaN transistor when a voltage of the first capacitor reaches a threshold. Currently amended
The method of claim 1, further comprising providing, by the driver circuit, a switching signal to the gate of the first GaN transistor. Withdrawn
The method of claim 1, wherein the first GaN transistor is shut-off prior to receiving the first voltage. Withdrawn
The method of claim 1, further comprising: providing power to a primary winding of a transformer, wherein the primary winding of the transformer is coupled to the drain node of the start-up circuit; and transferring power from an auxiliary winding of the transformer to the driver circuit after turning-off the second GaN transistor. Withdrawn
The method of claim 1, wherein the first GaN transistor and the second GaN transistor are integrated on a single semiconductor substrate. Withdrawn
The method of claim 1, wherein the start-up circuit further comprises: a third GaN transistor having a drain coupled to the gate of the second GaN transistor and to the first capacitor, and a gate coupled to the reference node, wherein the gate of the second GaN transistor is coupled to the reference node via a load path of the third GaN transistor; and a second capacitor coupled between a source of the third GaN transistor and the reference node. Withdrawn
Canceled
A circuit comprising: a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, and a source coupled to a first power source node configured to be coupled to a first capacitor, wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device. Currently amended
The circuit of claim 8, wherein the second GaN transistor comprises a gate coupled to the source node. Original
10. The circuit of claim 8, wherein the first GaN transistor and the second GaN transistor are integrated on a same semiconductor substrate. Original
The circuit of claim 8, further comprising a gate driving circuit having a power supply input coupled to the first power source node and an output coupled to the gate node. Original
1 8. The circuit of claim 8, further comprising a transformer having a first winding coupled to the drain node and an auxiliary winding coupled to the first power source node. Original
The circuit of claim 8, further comprising a third GaN transistor comprising a drain coupled to a gate of the second GaN transistor and to a second power source node configured to be coupled to the first capacitor, a source coupled to a third power source node configured to be coupled to a second capacitor, and a gate coupled to the source node. Original
Canceled
The circuit of claim [[11,]] wherein: the gate of the first GaN transistor comprises a fully recessed gate comprising a p-doped GaN material on top of a second A l GaN layer that extends through a first A l GaN layer, wherein the first A l GaN layer is disposed over a channel layer comprising undoped GaN material. Currently amended
The circuit of claim 12, wherein the gate of the second GaN transistor is disposed over surfaces of the first and second A l GaN layers without extending through the first AlGaN layer. Original
The circuit of claim 12, wherein the gate of the second GaN transistor comprises the p-doped GaN material. Original
The circuit of claim [[1 1,]] 8 wherein the gate of the second GaN transistor comprises a Scho t tky gate. Currently amended
1 6. The circuit of claim 15, further comprising a dielectric layer disposed between the gate of the second GaN transistor and a first A l GaN layer, wherein a threshold of the second GaN transistor is proportional to a thickness of the dielectric layer. Original
A switched-mode power supply comprising: an integrated circuit comprising a first gallium nitride (GaN) transistor having a drain coupled to a drain node and a source coupled to a reference node, a second GaN transistor having a drain coupled to the drain node and a gate coupled to the reference node, wherein the first GaN transistor and the second GaN transistor are disposed on a same semiconductor substrate, and wherein the first GaN transistor is a normally-off device, and the second GaN transistor is a normally-on device; a capacitor coupled to a source of the second GaN transistor; and a driver circuit comprising a gate driver output coupled to a gate of the first GaN transistor, and a power supply input coupled to the capacitor. Currently amended
The switched-mode power supply of claim 21, further comprising: a transformer having a primary winding coupled to the drain node of the integrated circuit and an auxiliary winding coupled to the capacitor; and a diode coupled between the auxiliary winding and the capacitor. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based start-up circuit (method claim)
No layer stack recorded.
GaN start-up circuit with normally-off and normally-on transistors
No layer stack recorded.
GaN transistor with fully recessed p-GaN gate on AlGaN/GaN stack
switched-mode power supply with integrated GaN IC
No layer stack recorded.
Materials described outside the worked examples.
first GaN transistor (normally-off)
GaN
first AlGaN layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
Related documents with shared materials, methods, properties, or citations.
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
Figures 5 illustrates a schematic cross-section of an embodiment GaN enhancement mode transistor cell;
Figures 6A, 6B and 6C illustrate schematic cross-sections of embodiment GaN depletion mode transistor cells; and
Figure 1 D and described further below. Once the voltage is applied to drain node VD, the voltage of power supply node VDD starts increasing due to capacitor C being charged via the load path of normally-on start-up transistor M2. The voltage of power supply VDD increases to a voltage of -V T M2, …
Figure 1. Normally-off switch transistor M i, normally-on start-up transistors M₂A and M₂B and diode D₃ may be implemented on a single semiconductor substrate and/or package 202. However, in alternative embodiments, the various components shown in
Figure 6B illustrates a schematic cross section of a GaN depletion mode transistor cell 620 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6C illustrates a schematic cross section of a GaN depletion mode transistor cell 640 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6. [0062] As shown, the drain metallization for both transistors M i and M₂ coupled to drain node VD is represented by layer 702; the source metallization for transistor M i coupled to ground node GND is represented by layer 704, the gate layer for transistor M i coupled to gate node VG is …
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
Figures 5 illustrates a schematic cross-section of an embodiment GaN enhancement mode transistor cell;
Figures 6A, 6B and 6C illustrate schematic cross-sections of embodiment GaN depletion mode transistor cells; and
Figure 1 D and described further below. Once the voltage is applied to drain node VD, the voltage of power supply node VDD starts increasing due to capacitor C being charged via the load path of normally-on start-up transistor M2. The voltage of power supply VDD increases to a voltage of -V T M2, …
Figure 1. Normally-off switch transistor M i, normally-on start-up transistors M₂A and M₂B and diode D₃ may be implemented on a single semiconductor substrate and/or package 202. However, in alternative embodiments, the various components shown in
Figure 6B illustrates a schematic cross section of a GaN depletion mode transistor cell 620 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6C illustrates a schematic cross section of a GaN depletion mode transistor cell 640 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6. [0062] As shown, the drain metallization for both transistors M i and M₂ coupled to drain node VD is represented by layer 702; the source metallization for transistor M i coupled to ground node GND is represented by layer 704, the gate layer for transistor M i coupled to gate node VG is …
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
Figures 5 illustrates a schematic cross-section of an embodiment GaN enhancement mode transistor cell;
Figures 6A, 6B and 6C illustrate schematic cross-sections of embodiment GaN depletion mode transistor cells; and
Figure 1 D and described further below. Once the voltage is applied to drain node VD, the voltage of power supply node VDD starts increasing due to capacitor C being charged via the load path of normally-on start-up transistor M2. The voltage of power supply VDD increases to a voltage of -V T M2, …
Figure 1. Normally-off switch transistor M i, normally-on start-up transistors M₂A and M₂B and diode D₃ may be implemented on a single semiconductor substrate and/or package 202. However, in alternative embodiments, the various components shown in
Figure 6B illustrates a schematic cross section of a GaN depletion mode transistor cell 620 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6C illustrates a schematic cross section of a GaN depletion mode transistor cell 640 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6. [0062] As shown, the drain metallization for both transistors M i and M₂ coupled to drain node VD is represented by layer 702; the source metallization for transistor M i coupled to ground node GND is represented by layer 704, the gate layer for transistor M i coupled to gate node VG is …
Figure 1B illustrates an I-V curve of depletion mode transistor used in the embodiment start-up circuit of
Figures 5 illustrates a schematic cross-section of an embodiment GaN enhancement mode transistor cell;
Figures 6A, 6B and 6C illustrate schematic cross-sections of embodiment GaN depletion mode transistor cells; and
Figure 1 D and described further below. Once the voltage is applied to drain node VD, the voltage of power supply node VDD starts increasing due to capacitor C being charged via the load path of normally-on start-up transistor M2. The voltage of power supply VDD increases to a voltage of -V T M2, …
Figure 1. Normally-off switch transistor M i, normally-on start-up transistors M₂A and M₂B and diode D₃ may be implemented on a single semiconductor substrate and/or package 202. However, in alternative embodiments, the various components shown in
Figure 6B illustrates a schematic cross section of a GaN depletion mode transistor cell 620 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6C illustrates a schematic cross section of a GaN depletion mode transistor cell 640 that may be used to implement normally-on switch transistors M2, M₂A and M₂B as described above. The structure of GaN depletion mode transistor cell 600 is similar in structure to GaN depletion mode …
Figure 6. [0062] As shown, the drain metallization for both transistors M i and M₂ coupled to drain node VD is represented by layer 702; the source metallization for transistor M i coupled to ground node GND is represented by layer 704, the gate layer for transistor M i coupled to gate node VG is …