Patent
US 12,212,310 B2GATE BIAS CIRCUIT FOR A DRIVER MONOLITHICALLY INTEGRATED WITH A GAN POWER FET
Manish Shah, Rajesh Ghosh, Syed Asif Eqbal, Firdos Khan et al.
Jan. 28, 2025·US
Copyright © 2026 Matter42. All rights reserved.
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US 12,212,310 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of an electronic device comprising a first embodiment of a gate bias circuit for a GaN driver.
FIG. 2 is a simplified schematic of an electronic device comprising a second embodiment of a gate bias circuit for a GaN driver.
FIG. 3 is a simplified schematic of an electronic device comprising a third embodiment of a gate bias circuit for a GaN driver.
FIG. 4 is a simplified schematic of an electronic device comprising a fourth embodiment of a gate bias circuit for a GaN driver.
FIG. 5 is a simplified schematic of an electronic device comprising a fifth embodiment of a gate bias circuit for a GaN driver.
FIG. 6 is a simplified schematic of an electronic device comprising a sixth embodiment of a gate bias circuit for a GaN driver.
FIG. 7 is a simplified schematic of an electronic device comprising a seventh embodiment of a gate bias circuit for a GaN driver.
FIG. 8 is a simplified schematic of an electronic device comprising an eighth embodiment of a gate bias circuit for a GaN driver.
FIG. 9 is a simplified schematic of an electronic device comprising a ninth embodiment of a gate bias circuit for a GaN driver.
FIG. 10 is a simplified schematic of an electronic device comprising a tenth embodiment of a gate bias circuit for a GaN driver.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: a GaN power FET; a GaN driver coupled to the GaN power FET; and 25 a gate bias circuit including: a linear regulator having an output terminal for output-ting a VHI voltage to the GaN driver, a first GaN resistor having one end coupled to a ground supply terminal and another end coupled to one end of a second GaN resistor, and a node, between the first GaN resistor and the second GaN resistor, coupled to an input terminal of the linear regulator, wherein another end of the second GaN resistor is coupled to a cathode of a GaN diode and to one end of a bypass capacitor, the other end of the bypass capacitor coupled to the ground supply terminal, wherein an anode of the GaN diode is coupled to the output terminal, and wherein a voltage VREG at the cathode of the GaN diode is coupled to the GaN driver, wherein the GaN power FET and the GaN driver are monolithically integrated on a die, and B₂ wherein the gate bias circuit is predominately monolithi-cally integrated on the die and includes only one active component external to the die.
The electronic device of claim 1, wherein a drain terminal of the GaN power FET is coupled to a high-voltage positive power supply terminal, a source terminal of the GaN power FET is coupled to a ground supply terminal, and a gate terminal of the GaN power FET is coupled to the GaN driver.
The electronic circuit of claim 1, wherein the GaN driver includes a pre-driver stage coupled to a final stage, and wherein the final stage is coupled to the GaN power FET.
The electronic device of claim 1, wherein the only one active component is a shunt regulator.
The electronic device of claim 1, wherein the only one active component is a Zener diode.
The electronic circuit of claim 1, wherein the only one active component external to the die consists of the linear regulator.
The electronic circuit of claim 1, wherein a fraction of the VHI voltage occurs at the node between the first GaN resistor and the second GaN resistor based on a resistance ratio of said resistors, and the fraction is fed back to the linear regulator as a voltage VFB. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN power FET with monolithically integrated GaN driver and gate bias circuit
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
GaN resistor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a simplified schematic of an electronic device comprising a first embodiment of a gate bias circuit for a GaN driver.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 200–600 V | — |
Voltage | 7.5–20 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,212,310 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of an electronic device comprising a first embodiment of a gate bias circuit for a GaN driver.
FIG. 2 is a simplified schematic of an electronic device comprising a second embodiment of a gate bias circuit for a GaN driver.
FIG. 3 is a simplified schematic of an electronic device comprising a third embodiment of a gate bias circuit for a GaN driver.
FIG. 4 is a simplified schematic of an electronic device comprising a fourth embodiment of a gate bias circuit for a GaN driver.
FIG. 5 is a simplified schematic of an electronic device comprising a fifth embodiment of a gate bias circuit for a GaN driver.
FIG. 6 is a simplified schematic of an electronic device comprising a sixth embodiment of a gate bias circuit for a GaN driver.
FIG. 7 is a simplified schematic of an electronic device comprising a seventh embodiment of a gate bias circuit for a GaN driver.
FIG. 8 is a simplified schematic of an electronic device comprising an eighth embodiment of a gate bias circuit for a GaN driver.
FIG. 9 is a simplified schematic of an electronic device comprising a ninth embodiment of a gate bias circuit for a GaN driver.
FIG. 10 is a simplified schematic of an electronic device comprising a tenth embodiment of a gate bias circuit for a GaN driver.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: a GaN power FET; a GaN driver coupled to the GaN power FET; and 25 a gate bias circuit including: a linear regulator having an output terminal for output-ting a VHI voltage to the GaN driver, a first GaN resistor having one end coupled to a ground supply terminal and another end coupled to one end of a second GaN resistor, and a node, between the first GaN resistor and the second GaN resistor, coupled to an input terminal of the linear regulator, wherein another end of the second GaN resistor is coupled to a cathode of a GaN diode and to one end of a bypass capacitor, the other end of the bypass capacitor coupled to the ground supply terminal, wherein an anode of the GaN diode is coupled to the output terminal, and wherein a voltage VREG at the cathode of the GaN diode is coupled to the GaN driver, wherein the GaN power FET and the GaN driver are monolithically integrated on a die, and B₂ wherein the gate bias circuit is predominately monolithi-cally integrated on the die and includes only one active component external to the die.
The electronic device of claim 1, wherein a drain terminal of the GaN power FET is coupled to a high-voltage positive power supply terminal, a source terminal of the GaN power FET is coupled to a ground supply terminal, and a gate terminal of the GaN power FET is coupled to the GaN driver.
The electronic circuit of claim 1, wherein the GaN driver includes a pre-driver stage coupled to a final stage, and wherein the final stage is coupled to the GaN power FET.
The electronic device of claim 1, wherein the only one active component is a shunt regulator.
The electronic device of claim 1, wherein the only one active component is a Zener diode.
The electronic circuit of claim 1, wherein the only one active component external to the die consists of the linear regulator.
The electronic circuit of claim 1, wherein a fraction of the VHI voltage occurs at the node between the first GaN resistor and the second GaN resistor based on a resistance ratio of said resistors, and the fraction is fed back to the linear regulator as a voltage VFB. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN power FET with monolithically integrated GaN driver and gate bias circuit
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
GaN resistor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a simplified schematic of an electronic device comprising a first embodiment of a gate bias circuit for a GaN driver.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 200–600 V | — |
Voltage | 7.5–20 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,212,310 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of an electronic device comprising a first embodiment of a gate bias circuit for a GaN driver.
FIG. 2 is a simplified schematic of an electronic device comprising a second embodiment of a gate bias circuit for a GaN driver.
FIG. 3 is a simplified schematic of an electronic device comprising a third embodiment of a gate bias circuit for a GaN driver.
FIG. 4 is a simplified schematic of an electronic device comprising a fourth embodiment of a gate bias circuit for a GaN driver.
FIG. 5 is a simplified schematic of an electronic device comprising a fifth embodiment of a gate bias circuit for a GaN driver.
FIG. 6 is a simplified schematic of an electronic device comprising a sixth embodiment of a gate bias circuit for a GaN driver.
FIG. 7 is a simplified schematic of an electronic device comprising a seventh embodiment of a gate bias circuit for a GaN driver.
FIG. 8 is a simplified schematic of an electronic device comprising an eighth embodiment of a gate bias circuit for a GaN driver.
FIG. 9 is a simplified schematic of an electronic device comprising a ninth embodiment of a gate bias circuit for a GaN driver.
FIG. 10 is a simplified schematic of an electronic device comprising a tenth embodiment of a gate bias circuit for a GaN driver.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: a GaN power FET; a GaN driver coupled to the GaN power FET; and 25 a gate bias circuit including: a linear regulator having an output terminal for output-ting a VHI voltage to the GaN driver, a first GaN resistor having one end coupled to a ground supply terminal and another end coupled to one end of a second GaN resistor, and a node, between the first GaN resistor and the second GaN resistor, coupled to an input terminal of the linear regulator, wherein another end of the second GaN resistor is coupled to a cathode of a GaN diode and to one end of a bypass capacitor, the other end of the bypass capacitor coupled to the ground supply terminal, wherein an anode of the GaN diode is coupled to the output terminal, and wherein a voltage VREG at the cathode of the GaN diode is coupled to the GaN driver, wherein the GaN power FET and the GaN driver are monolithically integrated on a die, and B₂ wherein the gate bias circuit is predominately monolithi-cally integrated on the die and includes only one active component external to the die.
The electronic device of claim 1, wherein a drain terminal of the GaN power FET is coupled to a high-voltage positive power supply terminal, a source terminal of the GaN power FET is coupled to a ground supply terminal, and a gate terminal of the GaN power FET is coupled to the GaN driver.
The electronic circuit of claim 1, wherein the GaN driver includes a pre-driver stage coupled to a final stage, and wherein the final stage is coupled to the GaN power FET.
The electronic device of claim 1, wherein the only one active component is a shunt regulator.
The electronic device of claim 1, wherein the only one active component is a Zener diode.
The electronic circuit of claim 1, wherein the only one active component external to the die consists of the linear regulator.
The electronic circuit of claim 1, wherein a fraction of the VHI voltage occurs at the node between the first GaN resistor and the second GaN resistor based on a resistance ratio of said resistors, and the fraction is fed back to the linear regulator as a voltage VFB. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN power FET with monolithically integrated GaN driver and gate bias circuit
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
GaN resistor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a simplified schematic of an electronic device comprising a first embodiment of a gate bias circuit for a GaN driver.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 200–600 V | — |
Voltage | 7.5–20 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,212,310 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of an electronic device comprising a first embodiment of a gate bias circuit for a GaN driver.
FIG. 2 is a simplified schematic of an electronic device comprising a second embodiment of a gate bias circuit for a GaN driver.
FIG. 3 is a simplified schematic of an electronic device comprising a third embodiment of a gate bias circuit for a GaN driver.
FIG. 4 is a simplified schematic of an electronic device comprising a fourth embodiment of a gate bias circuit for a GaN driver.
FIG. 5 is a simplified schematic of an electronic device comprising a fifth embodiment of a gate bias circuit for a GaN driver.
FIG. 6 is a simplified schematic of an electronic device comprising a sixth embodiment of a gate bias circuit for a GaN driver.
FIG. 7 is a simplified schematic of an electronic device comprising a seventh embodiment of a gate bias circuit for a GaN driver.
FIG. 8 is a simplified schematic of an electronic device comprising an eighth embodiment of a gate bias circuit for a GaN driver.
FIG. 9 is a simplified schematic of an electronic device comprising a ninth embodiment of a gate bias circuit for a GaN driver.
FIG. 10 is a simplified schematic of an electronic device comprising a tenth embodiment of a gate bias circuit for a GaN driver.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: a GaN power FET; a GaN driver coupled to the GaN power FET; and 25 a gate bias circuit including: a linear regulator having an output terminal for output-ting a VHI voltage to the GaN driver, a first GaN resistor having one end coupled to a ground supply terminal and another end coupled to one end of a second GaN resistor, and a node, between the first GaN resistor and the second GaN resistor, coupled to an input terminal of the linear regulator, wherein another end of the second GaN resistor is coupled to a cathode of a GaN diode and to one end of a bypass capacitor, the other end of the bypass capacitor coupled to the ground supply terminal, wherein an anode of the GaN diode is coupled to the output terminal, and wherein a voltage VREG at the cathode of the GaN diode is coupled to the GaN driver, wherein the GaN power FET and the GaN driver are monolithically integrated on a die, and B₂ wherein the gate bias circuit is predominately monolithi-cally integrated on the die and includes only one active component external to the die.
The electronic device of claim 1, wherein a drain terminal of the GaN power FET is coupled to a high-voltage positive power supply terminal, a source terminal of the GaN power FET is coupled to a ground supply terminal, and a gate terminal of the GaN power FET is coupled to the GaN driver.
The electronic circuit of claim 1, wherein the GaN driver includes a pre-driver stage coupled to a final stage, and wherein the final stage is coupled to the GaN power FET.
The electronic device of claim 1, wherein the only one active component is a shunt regulator.
The electronic device of claim 1, wherein the only one active component is a Zener diode.
The electronic circuit of claim 1, wherein the only one active component external to the die consists of the linear regulator.
The electronic circuit of claim 1, wherein a fraction of the VHI voltage occurs at the node between the first GaN resistor and the second GaN resistor based on a resistance ratio of said resistors, and the fraction is fed back to the linear regulator as a voltage VFB. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN power FET with monolithically integrated GaN driver and gate bias circuit
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
GaN resistor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a simplified schematic of an electronic device comprising a first embodiment of a gate bias circuit for a GaN driver.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 200–600 V | — |
Voltage | 7.5–20 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
GaN diode
bypass capacitor
FIG. 2 is a simplified schematic of an electronic device comprising a second embodiment of a gate bias circuit for a GaN driver.
FIG. 3 is a simplified schematic of an electronic device comprising a third embodiment of a gate bias circuit for a GaN driver.
FIG. 4 is a simplified schematic of an electronic device comprising a fourth embodiment of a gate bias circuit for a GaN driver.
FIG. 5 is a simplified schematic of an electronic device comprising a fifth embodiment of a gate bias circuit for a GaN driver.
FIG. 6 is a simplified schematic of an electronic device comprising a sixth embodiment of a gate bias circuit for a GaN driver.
FIG. 7 is a simplified schematic of an electronic device comprising a seventh embodiment of a gate bias circuit for a GaN driver.
FIG. 8 is a simplified schematic of an electronic device comprising an eighth embodiment of a gate bias circuit for a GaN driver.
FIG. 9 is a simplified schematic of an electronic device comprising a ninth embodiment of a gate bias circuit for a GaN driver.
FIG. 10 is a simplified schematic of an electronic device comprising a tenth embodiment of a gate bias circuit for a GaN driver.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
| — |
Voltage | 0–20 V | — |
Voltage | ≤ 30 V | — |
GaN diode
bypass capacitor
FIG. 2 is a simplified schematic of an electronic device comprising a second embodiment of a gate bias circuit for a GaN driver.
FIG. 3 is a simplified schematic of an electronic device comprising a third embodiment of a gate bias circuit for a GaN driver.
FIG. 4 is a simplified schematic of an electronic device comprising a fourth embodiment of a gate bias circuit for a GaN driver.
FIG. 5 is a simplified schematic of an electronic device comprising a fifth embodiment of a gate bias circuit for a GaN driver.
FIG. 6 is a simplified schematic of an electronic device comprising a sixth embodiment of a gate bias circuit for a GaN driver.
FIG. 7 is a simplified schematic of an electronic device comprising a seventh embodiment of a gate bias circuit for a GaN driver.
FIG. 8 is a simplified schematic of an electronic device comprising an eighth embodiment of a gate bias circuit for a GaN driver.
FIG. 9 is a simplified schematic of an electronic device comprising a ninth embodiment of a gate bias circuit for a GaN driver.
FIG. 10 is a simplified schematic of an electronic device comprising a tenth embodiment of a gate bias circuit for a GaN driver.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
| — |
Voltage | 0–20 V | — |
Voltage | ≤ 30 V | — |
GaN diode
bypass capacitor
FIG. 2 is a simplified schematic of an electronic device comprising a second embodiment of a gate bias circuit for a GaN driver.
FIG. 3 is a simplified schematic of an electronic device comprising a third embodiment of a gate bias circuit for a GaN driver.
FIG. 4 is a simplified schematic of an electronic device comprising a fourth embodiment of a gate bias circuit for a GaN driver.
FIG. 5 is a simplified schematic of an electronic device comprising a fifth embodiment of a gate bias circuit for a GaN driver.
FIG. 6 is a simplified schematic of an electronic device comprising a sixth embodiment of a gate bias circuit for a GaN driver.
FIG. 7 is a simplified schematic of an electronic device comprising a seventh embodiment of a gate bias circuit for a GaN driver.
FIG. 8 is a simplified schematic of an electronic device comprising an eighth embodiment of a gate bias circuit for a GaN driver.
FIG. 9 is a simplified schematic of an electronic device comprising a ninth embodiment of a gate bias circuit for a GaN driver.
FIG. 10 is a simplified schematic of an electronic device comprising a tenth embodiment of a gate bias circuit for a GaN driver.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
| — |
Voltage | 0–20 V | — |
Voltage | ≤ 30 V | — |
GaN diode
bypass capacitor
FIG. 2 is a simplified schematic of an electronic device comprising a second embodiment of a gate bias circuit for a GaN driver.
FIG. 3 is a simplified schematic of an electronic device comprising a third embodiment of a gate bias circuit for a GaN driver.
FIG. 4 is a simplified schematic of an electronic device comprising a fourth embodiment of a gate bias circuit for a GaN driver.
FIG. 5 is a simplified schematic of an electronic device comprising a fifth embodiment of a gate bias circuit for a GaN driver.
FIG. 6 is a simplified schematic of an electronic device comprising a sixth embodiment of a gate bias circuit for a GaN driver.
FIG. 7 is a simplified schematic of an electronic device comprising a seventh embodiment of a gate bias circuit for a GaN driver.
FIG. 8 is a simplified schematic of an electronic device comprising an eighth embodiment of a gate bias circuit for a GaN driver.
FIG. 9 is a simplified schematic of an electronic device comprising a ninth embodiment of a gate bias circuit for a GaN driver.
FIG. 10 is a simplified schematic of an electronic device comprising a tenth embodiment of a gate bias circuit for a GaN driver.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 11 is a first graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 12 is a second graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
FIG. 13 is a third graph of signals in a simulation of the gate bias circuit in accordance with the invention.
| — |
Voltage | 0–20 V | — |
Voltage | ≤ 30 V | — |