Patent
US 11,081,618BURIED ACTIVATED p-(Al,In)GaN LAYERS
Ian MANN, SATYANARAYAN BARIK, JOSHUA DAVID BROWN, DANYU LIU
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 11,081,618Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Again, additional semiconductor layers 240 have been grown in between the n-GaN layer 230 and p-GaN layer 250. In the embodiment shown, the additional …
FIGS. 2A to 2E are schematic representations of a number of representative semiconductor structures which may be formed according to the method of the first …
FIGS. 3A-3C show schematic representations of a number of semiconductor structures, employing an n-InGaN cap, which were tested using electroluminescent …
FIGS. 4A-4C show schematic representations of a number of semiconductor structures, without an n-InGaN cap, which were tested using electroluminescent methods …
FIGS. 5A-5 D and Table 1, to display higher Vf and lower LOP indicating poor hole injection efficiency and high series resistance which are associated with a …
FIGS. 6A-6D, and in Tables 1 and 2, indicate that the TJ structure grown under RPCVD conditions according to the present invention (Structure 3 in each …
FIG. 7. SVG 16724855.12-23-2019.K₄IRK₁GIRXEAPX0.SPEC.36.2.580.300.1969.1131.svg 2.77 4.63 Chemistry Black and white 1 N 2 flow excludes N 2 plasma flow. [256] …
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
FIG. 9 show device structures used to evaluate the performance of n/p-(A l,In)GaN tunnel junctions and buried activated p--(A l,In)GaN layers fabricated using …
FIG. 10 shows an IV curve for the n/p-GaN tunnel junction shown in
FIG. 11 shows a schematic of an example of a buried activated n/p-GaN tunnel junction provided by the present disclosure. [29]
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 15 demonstrate that tunnel junctions fabricated using process conditions B and fabricated according to methods provided by the present disclosure …
FIGS. 16A and 16B show photographs of electroluminescence images of an LED with an overlying n/p-GaN tunnel junction fabricated according to methods provided …
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer, comprising: (a) exposing a magnesium-doped p-(A l,I n)GaN layer to a gaseous mixture comprising H2, N H3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr, to provide an exposed magnesium-doped p-(A l,I n)GaN layer; and (b) growing an n-(A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD, to provide a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer. Previously presented
The method of claim 2, wherein (b) growing the n- (Al, I n)GaN layer comprises growing the n- (A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of H₂ is greater than the partial pressure of N2. Previously presented
The method of claim 2, wherein (b) growing the n- (Al, I n)GaN layer comprises growing the n- (A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2. Previously presented
The method of claim 2, wherein step (b) comprises: (b1) growing a first n-(A l,I n)GaN layer on the exposed magnesium-doped p- (Al, I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing a second n-(A l,I n)GaN layer on the first n-(Al, I n)GaN layer by RPCVD. Previously presented
The method of claim 2, wherein step (b) comprises: (b1) growing an (Al, I n)GaN layer on the exposed magnesium-doped p-(Al, I n)GaN layer in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing the n-(A l,I n)GaN layer on the (A l,I n)GaN layer by RPCVD. Previously presented
The method of claim 2, wherein in step (a) exposing the magnesium-doped p-(Al, I n)GaN layer comprises exposing the magnesium-doped p-(Al, I n)GaN layer to a N₂ plasma. Currently amended
The method of claim 2, wherein step (b) is performed after step (a) without any intervening steps. Previously presented
The method of claim 2, wherein exposing comprises exposing the magnesium-doped p-(Al, I n)GaN layer to a partial pressure of H₂ less than 300 Torr and to a temperature greater than 700 0 C. Currently amended
The method of claim 2, wherein, in step (a) the partial pressure of H₂ is from 1 Torr to 300 Torr; or in step (b) the partial pressure of H₂ is from 0.1 Torr to 300 Torr. Currently amended
The method of claim 2, wherein step (a) further comprises growing the a magnesium-doped p-(Al, I n)GaN layer using a gaseous mixture comprising H2, NH 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr, to provide the a magnesium-doped p-(A l,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor structure fabricated by the method of claim 2. Previously presented
A semiconductor structure fabricated by the method of claim 2. Previously presented
Canceled
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN la y er, comprising: a) growing a magnesium-doped p-(A l,I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD,, wherein growing the n-(Al, I n)GaN layer consists of growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor structure fabricated by the method of claim 13 4-2. Currently amended
A semiconductor structure fabricated by the method of claim 13 4-2. Currently amended structure fabricated by the method of method of claim 14. New structure fabricated by the method of method of claim 15. New
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer, comprising: a) growing a magnesium-doped p-(A l,I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD,, wherein growing the n-(Al, I n)GaN layer consists of growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of H₂ is greater than the partial pressure of N2, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor claim 14. New
A method of fabricating a semiconductor structure comprising a buried activated p-(Al, I n)GaN la y er, comprising: a) growing a magnesium-doped p-(Al, I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(A l,I n)GaN layer on the magnesium-doped p-(Al, I n)GaN layer by RPCVD,, wherein step (b) comprises: (b1) growing an (A l,I n)GaN layer on the magnesium-doped p-(Al, I n)GaN layer in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing the n-(A l,I n)GaN layer on the (A l,I n)GaN layer by RPCVD, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al, I n)GaN la y er. Currently amended
A semiconductor device comprising a semiconductor claim 15. New
A semiconductor structure fabricated by the
A semiconductor structure fabricated by the
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials2 process steps
Semiconductor structures comprising a p-GaN layer with an n-InGaN cap were tested using electroluminescent methods. Three variants were compared: (A) MOCVD-grown blue LED baseline, (B) MOCVD-completed structure, and (C) RPCVD-completed structure. IV curves and electroluminescent imaging were used to assess device performance.
2 materials2 process steps
Semiconductor structures comprising a p-GaN layer without an n-InGaN cap were tested using electroluminescent methods. Two variants were compared: (A) MOCVD-grown blue LED baseline and (C) RPCVD-completed structure. IV curves were measured.
2 materials1 process step
A commercial LED was overgrown with a buried activated n/p-GaN tunnel junction. IV curves for the resulting structure were measured and are shown in FIG. 10.
3 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a NH3:N₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured.
3 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a NH3:H₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured. LOP as a function of input current was also characterized (FIG. 15).
2 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a N₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured.
Layer stacks claimed or described, ordered top of device to substrate.
buried activated n/p-(Al,In)GaN tunnel junction semiconductor structure
commercial LED with buried n/p-GaN tunnel junction
Materials described outside the worked examples.
H₂
NH₃
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 400–1000 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,081,618Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Again, additional semiconductor layers 240 have been grown in between the n-GaN layer 230 and p-GaN layer 250. In the embodiment shown, the additional …
FIGS. 2A to 2E are schematic representations of a number of representative semiconductor structures which may be formed according to the method of the first …
FIGS. 3A-3C show schematic representations of a number of semiconductor structures, employing an n-InGaN cap, which were tested using electroluminescent …
FIGS. 4A-4C show schematic representations of a number of semiconductor structures, without an n-InGaN cap, which were tested using electroluminescent methods …
FIGS. 5A-5 D and Table 1, to display higher Vf and lower LOP indicating poor hole injection efficiency and high series resistance which are associated with a …
FIGS. 6A-6D, and in Tables 1 and 2, indicate that the TJ structure grown under RPCVD conditions according to the present invention (Structure 3 in each …
FIG. 7. SVG 16724855.12-23-2019.K₄IRK₁GIRXEAPX0.SPEC.36.2.580.300.1969.1131.svg 2.77 4.63 Chemistry Black and white 1 N 2 flow excludes N 2 plasma flow. [256] …
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
FIG. 9 show device structures used to evaluate the performance of n/p-(A l,In)GaN tunnel junctions and buried activated p--(A l,In)GaN layers fabricated using …
FIG. 10 shows an IV curve for the n/p-GaN tunnel junction shown in
FIG. 11 shows a schematic of an example of a buried activated n/p-GaN tunnel junction provided by the present disclosure. [29]
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 15 demonstrate that tunnel junctions fabricated using process conditions B and fabricated according to methods provided by the present disclosure …
FIGS. 16A and 16B show photographs of electroluminescence images of an LED with an overlying n/p-GaN tunnel junction fabricated according to methods provided …
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer, comprising: (a) exposing a magnesium-doped p-(A l,I n)GaN layer to a gaseous mixture comprising H2, N H3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr, to provide an exposed magnesium-doped p-(A l,I n)GaN layer; and (b) growing an n-(A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD, to provide a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer. Previously presented
The method of claim 2, wherein (b) growing the n- (Al, I n)GaN layer comprises growing the n- (A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of H₂ is greater than the partial pressure of N2. Previously presented
The method of claim 2, wherein (b) growing the n- (Al, I n)GaN layer comprises growing the n- (A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2. Previously presented
The method of claim 2, wherein step (b) comprises: (b1) growing a first n-(A l,I n)GaN layer on the exposed magnesium-doped p- (Al, I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing a second n-(A l,I n)GaN layer on the first n-(Al, I n)GaN layer by RPCVD. Previously presented
The method of claim 2, wherein step (b) comprises: (b1) growing an (Al, I n)GaN layer on the exposed magnesium-doped p-(Al, I n)GaN layer in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing the n-(A l,I n)GaN layer on the (A l,I n)GaN layer by RPCVD. Previously presented
The method of claim 2, wherein in step (a) exposing the magnesium-doped p-(Al, I n)GaN layer comprises exposing the magnesium-doped p-(Al, I n)GaN layer to a N₂ plasma. Currently amended
The method of claim 2, wherein step (b) is performed after step (a) without any intervening steps. Previously presented
The method of claim 2, wherein exposing comprises exposing the magnesium-doped p-(Al, I n)GaN layer to a partial pressure of H₂ less than 300 Torr and to a temperature greater than 700 0 C. Currently amended
The method of claim 2, wherein, in step (a) the partial pressure of H₂ is from 1 Torr to 300 Torr; or in step (b) the partial pressure of H₂ is from 0.1 Torr to 300 Torr. Currently amended
The method of claim 2, wherein step (a) further comprises growing the a magnesium-doped p-(Al, I n)GaN layer using a gaseous mixture comprising H2, NH 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr, to provide the a magnesium-doped p-(A l,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor structure fabricated by the method of claim 2. Previously presented
A semiconductor structure fabricated by the method of claim 2. Previously presented
Canceled
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN la y er, comprising: a) growing a magnesium-doped p-(A l,I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD,, wherein growing the n-(Al, I n)GaN layer consists of growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor structure fabricated by the method of claim 13 4-2. Currently amended
A semiconductor structure fabricated by the method of claim 13 4-2. Currently amended structure fabricated by the method of method of claim 14. New structure fabricated by the method of method of claim 15. New
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer, comprising: a) growing a magnesium-doped p-(A l,I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD,, wherein growing the n-(Al, I n)GaN layer consists of growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of H₂ is greater than the partial pressure of N2, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor claim 14. New
A method of fabricating a semiconductor structure comprising a buried activated p-(Al, I n)GaN la y er, comprising: a) growing a magnesium-doped p-(Al, I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(A l,I n)GaN layer on the magnesium-doped p-(Al, I n)GaN layer by RPCVD,, wherein step (b) comprises: (b1) growing an (A l,I n)GaN layer on the magnesium-doped p-(Al, I n)GaN layer in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing the n-(A l,I n)GaN layer on the (A l,I n)GaN layer by RPCVD, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al, I n)GaN la y er. Currently amended
A semiconductor device comprising a semiconductor claim 15. New
A semiconductor structure fabricated by the
A semiconductor structure fabricated by the
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials2 process steps
Semiconductor structures comprising a p-GaN layer with an n-InGaN cap were tested using electroluminescent methods. Three variants were compared: (A) MOCVD-grown blue LED baseline, (B) MOCVD-completed structure, and (C) RPCVD-completed structure. IV curves and electroluminescent imaging were used to assess device performance.
2 materials2 process steps
Semiconductor structures comprising a p-GaN layer without an n-InGaN cap were tested using electroluminescent methods. Two variants were compared: (A) MOCVD-grown blue LED baseline and (C) RPCVD-completed structure. IV curves were measured.
2 materials1 process step
A commercial LED was overgrown with a buried activated n/p-GaN tunnel junction. IV curves for the resulting structure were measured and are shown in FIG. 10.
3 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a NH3:N₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured.
3 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a NH3:H₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured. LOP as a function of input current was also characterized (FIG. 15).
2 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a N₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured.
Layer stacks claimed or described, ordered top of device to substrate.
buried activated n/p-(Al,In)GaN tunnel junction semiconductor structure
commercial LED with buried n/p-GaN tunnel junction
Materials described outside the worked examples.
H₂
NH₃
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 400–1000 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,081,618Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Again, additional semiconductor layers 240 have been grown in between the n-GaN layer 230 and p-GaN layer 250. In the embodiment shown, the additional …
FIGS. 2A to 2E are schematic representations of a number of representative semiconductor structures which may be formed according to the method of the first …
FIGS. 3A-3C show schematic representations of a number of semiconductor structures, employing an n-InGaN cap, which were tested using electroluminescent …
FIGS. 4A-4C show schematic representations of a number of semiconductor structures, without an n-InGaN cap, which were tested using electroluminescent methods …
FIGS. 5A-5 D and Table 1, to display higher Vf and lower LOP indicating poor hole injection efficiency and high series resistance which are associated with a …
FIGS. 6A-6D, and in Tables 1 and 2, indicate that the TJ structure grown under RPCVD conditions according to the present invention (Structure 3 in each …
FIG. 7. SVG 16724855.12-23-2019.K₄IRK₁GIRXEAPX0.SPEC.36.2.580.300.1969.1131.svg 2.77 4.63 Chemistry Black and white 1 N 2 flow excludes N 2 plasma flow. [256] …
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
FIG. 9 show device structures used to evaluate the performance of n/p-(A l,In)GaN tunnel junctions and buried activated p--(A l,In)GaN layers fabricated using …
FIG. 10 shows an IV curve for the n/p-GaN tunnel junction shown in
FIG. 11 shows a schematic of an example of a buried activated n/p-GaN tunnel junction provided by the present disclosure. [29]
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 15 demonstrate that tunnel junctions fabricated using process conditions B and fabricated according to methods provided by the present disclosure …
FIGS. 16A and 16B show photographs of electroluminescence images of an LED with an overlying n/p-GaN tunnel junction fabricated according to methods provided …
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer, comprising: (a) exposing a magnesium-doped p-(A l,I n)GaN layer to a gaseous mixture comprising H2, N H3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr, to provide an exposed magnesium-doped p-(A l,I n)GaN layer; and (b) growing an n-(A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD, to provide a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer. Previously presented
The method of claim 2, wherein (b) growing the n- (Al, I n)GaN layer comprises growing the n- (A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of H₂ is greater than the partial pressure of N2. Previously presented
The method of claim 2, wherein (b) growing the n- (Al, I n)GaN layer comprises growing the n- (A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2. Previously presented
The method of claim 2, wherein step (b) comprises: (b1) growing a first n-(A l,I n)GaN layer on the exposed magnesium-doped p- (Al, I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing a second n-(A l,I n)GaN layer on the first n-(Al, I n)GaN layer by RPCVD. Previously presented
The method of claim 2, wherein step (b) comprises: (b1) growing an (Al, I n)GaN layer on the exposed magnesium-doped p-(Al, I n)GaN layer in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing the n-(A l,I n)GaN layer on the (A l,I n)GaN layer by RPCVD. Previously presented
The method of claim 2, wherein in step (a) exposing the magnesium-doped p-(Al, I n)GaN layer comprises exposing the magnesium-doped p-(Al, I n)GaN layer to a N₂ plasma. Currently amended
The method of claim 2, wherein step (b) is performed after step (a) without any intervening steps. Previously presented
The method of claim 2, wherein exposing comprises exposing the magnesium-doped p-(Al, I n)GaN layer to a partial pressure of H₂ less than 300 Torr and to a temperature greater than 700 0 C. Currently amended
The method of claim 2, wherein, in step (a) the partial pressure of H₂ is from 1 Torr to 300 Torr; or in step (b) the partial pressure of H₂ is from 0.1 Torr to 300 Torr. Currently amended
The method of claim 2, wherein step (a) further comprises growing the a magnesium-doped p-(Al, I n)GaN layer using a gaseous mixture comprising H2, NH 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr, to provide the a magnesium-doped p-(A l,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor structure fabricated by the method of claim 2. Previously presented
A semiconductor structure fabricated by the method of claim 2. Previously presented
Canceled
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN la y er, comprising: a) growing a magnesium-doped p-(A l,I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD,, wherein growing the n-(Al, I n)GaN layer consists of growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor structure fabricated by the method of claim 13 4-2. Currently amended
A semiconductor structure fabricated by the method of claim 13 4-2. Currently amended structure fabricated by the method of method of claim 14. New structure fabricated by the method of method of claim 15. New
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer, comprising: a) growing a magnesium-doped p-(A l,I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD,, wherein growing the n-(Al, I n)GaN layer consists of growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of H₂ is greater than the partial pressure of N2, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor claim 14. New
A method of fabricating a semiconductor structure comprising a buried activated p-(Al, I n)GaN la y er, comprising: a) growing a magnesium-doped p-(Al, I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(A l,I n)GaN layer on the magnesium-doped p-(Al, I n)GaN layer by RPCVD,, wherein step (b) comprises: (b1) growing an (A l,I n)GaN layer on the magnesium-doped p-(Al, I n)GaN layer in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing the n-(A l,I n)GaN layer on the (A l,I n)GaN layer by RPCVD, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al, I n)GaN la y er. Currently amended
A semiconductor device comprising a semiconductor claim 15. New
A semiconductor structure fabricated by the
A semiconductor structure fabricated by the
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials2 process steps
Semiconductor structures comprising a p-GaN layer with an n-InGaN cap were tested using electroluminescent methods. Three variants were compared: (A) MOCVD-grown blue LED baseline, (B) MOCVD-completed structure, and (C) RPCVD-completed structure. IV curves and electroluminescent imaging were used to assess device performance.
2 materials2 process steps
Semiconductor structures comprising a p-GaN layer without an n-InGaN cap were tested using electroluminescent methods. Two variants were compared: (A) MOCVD-grown blue LED baseline and (C) RPCVD-completed structure. IV curves were measured.
2 materials1 process step
A commercial LED was overgrown with a buried activated n/p-GaN tunnel junction. IV curves for the resulting structure were measured and are shown in FIG. 10.
3 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a NH3:N₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured.
3 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a NH3:H₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured. LOP as a function of input current was also characterized (FIG. 15).
2 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a N₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured.
Layer stacks claimed or described, ordered top of device to substrate.
buried activated n/p-(Al,In)GaN tunnel junction semiconductor structure
commercial LED with buried n/p-GaN tunnel junction
Materials described outside the worked examples.
H₂
NH₃
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 400–1000 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,081,618Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Again, additional semiconductor layers 240 have been grown in between the n-GaN layer 230 and p-GaN layer 250. In the embodiment shown, the additional …
FIGS. 2A to 2E are schematic representations of a number of representative semiconductor structures which may be formed according to the method of the first …
FIGS. 3A-3C show schematic representations of a number of semiconductor structures, employing an n-InGaN cap, which were tested using electroluminescent …
FIGS. 4A-4C show schematic representations of a number of semiconductor structures, without an n-InGaN cap, which were tested using electroluminescent methods …
FIGS. 5A-5 D and Table 1, to display higher Vf and lower LOP indicating poor hole injection efficiency and high series resistance which are associated with a …
FIGS. 6A-6D, and in Tables 1 and 2, indicate that the TJ structure grown under RPCVD conditions according to the present invention (Structure 3 in each …
FIG. 7. SVG 16724855.12-23-2019.K₄IRK₁GIRXEAPX0.SPEC.36.2.580.300.1969.1131.svg 2.77 4.63 Chemistry Black and white 1 N 2 flow excludes N 2 plasma flow. [256] …
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
FIG. 9 show device structures used to evaluate the performance of n/p-(A l,In)GaN tunnel junctions and buried activated p--(A l,In)GaN layers fabricated using …
FIG. 10 shows an IV curve for the n/p-GaN tunnel junction shown in
FIG. 11 shows a schematic of an example of a buried activated n/p-GaN tunnel junction provided by the present disclosure. [29]
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 15 demonstrate that tunnel junctions fabricated using process conditions B and fabricated according to methods provided by the present disclosure …
FIGS. 16A and 16B show photographs of electroluminescence images of an LED with an overlying n/p-GaN tunnel junction fabricated according to methods provided …
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer, comprising: (a) exposing a magnesium-doped p-(A l,I n)GaN layer to a gaseous mixture comprising H2, N H3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr, to provide an exposed magnesium-doped p-(A l,I n)GaN layer; and (b) growing an n-(A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD, to provide a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer. Previously presented
The method of claim 2, wherein (b) growing the n- (Al, I n)GaN layer comprises growing the n- (A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of H₂ is greater than the partial pressure of N2. Previously presented
The method of claim 2, wherein (b) growing the n- (Al, I n)GaN layer comprises growing the n- (A l,I n)GaN layer on the exposed magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2. Previously presented
The method of claim 2, wherein step (b) comprises: (b1) growing a first n-(A l,I n)GaN layer on the exposed magnesium-doped p- (Al, I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing a second n-(A l,I n)GaN layer on the first n-(Al, I n)GaN layer by RPCVD. Previously presented
The method of claim 2, wherein step (b) comprises: (b1) growing an (Al, I n)GaN layer on the exposed magnesium-doped p-(Al, I n)GaN layer in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing the n-(A l,I n)GaN layer on the (A l,I n)GaN layer by RPCVD. Previously presented
The method of claim 2, wherein in step (a) exposing the magnesium-doped p-(Al, I n)GaN layer comprises exposing the magnesium-doped p-(Al, I n)GaN layer to a N₂ plasma. Currently amended
The method of claim 2, wherein step (b) is performed after step (a) without any intervening steps. Previously presented
The method of claim 2, wherein exposing comprises exposing the magnesium-doped p-(Al, I n)GaN layer to a partial pressure of H₂ less than 300 Torr and to a temperature greater than 700 0 C. Currently amended
The method of claim 2, wherein, in step (a) the partial pressure of H₂ is from 1 Torr to 300 Torr; or in step (b) the partial pressure of H₂ is from 0.1 Torr to 300 Torr. Currently amended
The method of claim 2, wherein step (a) further comprises growing the a magnesium-doped p-(Al, I n)GaN layer using a gaseous mixture comprising H2, NH 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr, to provide the a magnesium-doped p-(A l,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor structure fabricated by the method of claim 2. Previously presented
A semiconductor structure fabricated by the method of claim 2. Previously presented
Canceled
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN la y er, comprising: a) growing a magnesium-doped p-(A l,I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD,, wherein growing the n-(Al, I n)GaN layer consists of growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor structure fabricated by the method of claim 13 4-2. Currently amended
A semiconductor structure fabricated by the method of claim 13 4-2. Currently amended structure fabricated by the method of method of claim 14. New structure fabricated by the method of method of claim 15. New
A method of fabricating a semiconductor structure comprising a buried activated p-(A l,I n)GaN layer, comprising: a) growing a magnesium-doped p-(A l,I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD,, wherein growing the n-(Al, I n)GaN layer consists of growing an n-(Al, I n)GaN layer on the magnesium-doped p-(A l,I n)GaN layer by RPCVD in an environment wherein the partial pressure of H₂ is greater than the partial pressure of N2, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al,I n)GaN layer. Currently amended
A semiconductor device comprising a semiconductor claim 14. New
A method of fabricating a semiconductor structure comprising a buried activated p-(Al, I n)GaN la y er, comprising: a) growing a magnesium-doped p-(Al, I n)GaN layer using a gaseous mixture comprising H2, N H 3, or a combination thereof, wherein the gaseous mixture has a partial pressure of H₂ less than 760 Torr; and (b) growing an n-(A l,I n)GaN layer on the magnesium-doped p-(Al, I n)GaN layer by RPCVD,, wherein step (b) comprises: (b1) growing an (A l,I n)GaN layer on the magnesium-doped p-(Al, I n)GaN layer in an environment wherein the partial pressure of N₂ is greater than the partial pressure of H2; and (b2) growing the n-(A l,I n)GaN layer on the (A l,I n)GaN layer by RPCVD, to provide a semiconductor structure comprising a buried activated magnesium doped p- (Al, I n)GaN la y er. Currently amended
A semiconductor device comprising a semiconductor claim 15. New
A semiconductor structure fabricated by the
A semiconductor structure fabricated by the
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials2 process steps
Semiconductor structures comprising a p-GaN layer with an n-InGaN cap were tested using electroluminescent methods. Three variants were compared: (A) MOCVD-grown blue LED baseline, (B) MOCVD-completed structure, and (C) RPCVD-completed structure. IV curves and electroluminescent imaging were used to assess device performance.
2 materials2 process steps
Semiconductor structures comprising a p-GaN layer without an n-InGaN cap were tested using electroluminescent methods. Two variants were compared: (A) MOCVD-grown blue LED baseline and (C) RPCVD-completed structure. IV curves were measured.
2 materials1 process step
A commercial LED was overgrown with a buried activated n/p-GaN tunnel junction. IV curves for the resulting structure were measured and are shown in FIG. 10.
3 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a NH3:N₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured.
3 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a NH3:H₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured. LOP as a function of input current was also characterized (FIG. 15).
2 materials1 process step
p-GaN layer on commercial LEDs (full and partial) with ITO was exposed to a N₂ environment followed by overgrowth of an n+/n-GaN layer using RPCVD. IV curves were measured.
Layer stacks claimed or described, ordered top of device to substrate.
buried activated n/p-(Al,In)GaN tunnel junction semiconductor structure
commercial LED with buried n/p-GaN tunnel junction
Materials described outside the worked examples.
H₂
NH₃
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 400–1000 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
FIG. 9 show device structures used to evaluate the performance of n/p-(A l,In)GaN tunnel junctions and buried activated p--(A l,In)GaN layers fabricated using …
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
| 500–1000 °C |
| — |
Temperature | 600–1000 °C | — |
Temperature | 700–1000 °C | — |
Temperature | 400–950 °C | — |
Temperature | 500–950 °C | — |
Temperature | 600–950 °C | — |
Temperature | 700–950 °C | — |
Temperature | 400–900 °C | — |
Temperature | 500–900 °C | — |
Temperature | 600–900 °C | — |
Temperature | 700–900 °C | — |
Temperature | 750–850 °C | — |
Pressure | 0.1–300 Torr | — |
Pressure | 0.1–100 Torr | — |
Pressure | 0.1–50 Torr | — |
Pressure | 0.1–25 Torr | — |
Pressure | 0.1–15 Torr | — |
Pressure | 0.5–300 Torr | — |
Pressure | 0.5–100 Torr | — |
Pressure | 0.5–50 Torr | — |
Pressure | 0.5–25 Torr | — |
Pressure | 0.5–15 Torr | — |
Pressure | 1–10 Torr | — |
Temperature | 400–1050 °C | — |
Pressure | 1–300 Torr | — |
Pressure | 0.1–10 Torr | — |
Temperature | 500–1050 °C | — |
Pressure | 1–760 Torr | — |
Pressure | 1–500 Torr | — |
Pressure | 5–275 Torr | — |
Pressure | 10–250 Torr | — |
Pressure | 50–200 Torr | — |
Temperature | 500–1200 °C | — |
Temperature | 500–1100 °C | — |
Temperature | 600–1050 °C | — |
Temperature | 700–1050 °C | — |
Temperature | 800–1050 °C | — |
Duration | 5–5 minutes | — |
Duration | 1–4 minutes | — |
Duration | 1–3 minutes | — |
Temperature | 700–1200 °C | — |
Temperature | 800–1100 °C | — |
Pressure | 100–250 Torr | — |
Temperature | 875–1050 °C | — |
Pressure | 1–200 Torr | — |
Pressure | 1–100 Torr | — |
Pressure | 1–50 Torr | — |
Temperature | 450–900 °C | — |
Temperature | 500–850 °C | — |
Temperature | 550–800 °C | — |
Temperature | 600–750 °C | — |
Pressure | 25–400 Torr | — |
Pressure | 0.2–50 Torr | — |
Pressure | 0.1–200 Torr | — |
Thickness | 1–10 nm | — |
Thickness | 1–8 nm | — |
Thickness | 1–6 nm | — |
Thickness | 1–4 nm | — |
Thickness | 1–2 nm | — |
Pressure | 0.1–760 Torr | — |
Pressure | 0.1–500 Torr | — |
Temperature | 400–850 °C | — |
Temperature | 450–800 °C | — |
Temperature | 500–750 °C | — |
Temperature | 400–700 °C | — |
Temperature | 500–650 °C | — |
Thickness | 1–100 nm | — |
Thickness | 0.5–50 nm | — |
Thickness | 25–35 nm | — |
Voltage | 0.01–0.3 V | — |
Voltage | 0.05–0.3 V | — |
Voltage | 0.1–0.2 V | — |
Pressure | ≤ 760 Torr | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 25 nm | — |
Thickness | ≤ 20 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 5 nm | — |
Duration | ≤ 5 minutes | — |
Duration | ≤ 4 minutes | — |
Duration | ≤ 2 minutes | — |
Duration | ≤ 1 minute | — |
Pressure | ≤ 300 Torr | — |
Temperature | ≤ 900 °C | — |
Pressure | ≤ 250 Torr | — |
Pressure | ≤ 200 Torr | — |
Pressure | ≤ 1 Torr | — |
Pressure | ≤ 50 Torr | — |
Pressure | ≤ 10 Torr | — |
Duration | ≤ 6 minutes | — |
Duration | ≤ 3 minutes | — |
Temperature | ≤ 1e+50 °C | — |
Temperature | ≤ 850 °C | — |
Temperature | ≤ 800 °C | — |
Temperature | ≤ 700 °C | — |
Temperature | ≤ 600 °C | — |
Pressure | ≤ 500 Torr | — |
Thickness | ≤ 30 mm | — |
Thickness | ≤ 20 mm | — |
Thickness | ≤ 8 nm | — |
Thickness | ≤ 6 nm | — |
Thickness | ≤ 4 nm | — |
Thickness | ≤ 2 nm | — |
Temperature | ≤ 950 °C | — |
Voltage | ≤ 0.3 V | — |
Voltage | ≤ 0.1 V | — |
Voltage | ≤ 0.2 V | — |
Voltage | ≤ 0.05 V | — |
Thickness | ≥ 10 nm | — |
Thickness | ≥ 20 nm | — |
Thickness | ≥ 30 nm | — |
Temperature | ≥ 500 °C | — |
Temperature | ≥ 600 °C | — |
Temperature | ≥ 700 °C | — |
Temperature | ≥ 800 °C | — |
Temperature | ≥ 850 °C | — |
Temperature | ≥ 900 °C | — |
Temperature | ≥ 950 °C | — |
Temperature | ≥ 1 °C | — |
Temperature | ≥ 1100 °C | — |
Temperature | ≥ 1200 °C | — |
Duration | ≥ 30 sec | — |
Duration | ≥ 60 sec | — |
Duration | ≥ 120 sec | — |
Duration | ≥ 240 sec | — |
Duration | ≥ 90 sec | — |
Pressure | ≥ 0.1 Torr | — |
Pressure | ≥ 10 Torr | — |
Pressure | ≥ 1 Torr | — |
Pressure | ≥ 250 Torr | — |
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
FIG. 9 show device structures used to evaluate the performance of n/p-(A l,In)GaN tunnel junctions and buried activated p--(A l,In)GaN layers fabricated using …
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
| 500–1000 °C |
| — |
Temperature | 600–1000 °C | — |
Temperature | 700–1000 °C | — |
Temperature | 400–950 °C | — |
Temperature | 500–950 °C | — |
Temperature | 600–950 °C | — |
Temperature | 700–950 °C | — |
Temperature | 400–900 °C | — |
Temperature | 500–900 °C | — |
Temperature | 600–900 °C | — |
Temperature | 700–900 °C | — |
Temperature | 750–850 °C | — |
Pressure | 0.1–300 Torr | — |
Pressure | 0.1–100 Torr | — |
Pressure | 0.1–50 Torr | — |
Pressure | 0.1–25 Torr | — |
Pressure | 0.1–15 Torr | — |
Pressure | 0.5–300 Torr | — |
Pressure | 0.5–100 Torr | — |
Pressure | 0.5–50 Torr | — |
Pressure | 0.5–25 Torr | — |
Pressure | 0.5–15 Torr | — |
Pressure | 1–10 Torr | — |
Temperature | 400–1050 °C | — |
Pressure | 1–300 Torr | — |
Pressure | 0.1–10 Torr | — |
Temperature | 500–1050 °C | — |
Pressure | 1–760 Torr | — |
Pressure | 1–500 Torr | — |
Pressure | 5–275 Torr | — |
Pressure | 10–250 Torr | — |
Pressure | 50–200 Torr | — |
Temperature | 500–1200 °C | — |
Temperature | 500–1100 °C | — |
Temperature | 600–1050 °C | — |
Temperature | 700–1050 °C | — |
Temperature | 800–1050 °C | — |
Duration | 5–5 minutes | — |
Duration | 1–4 minutes | — |
Duration | 1–3 minutes | — |
Temperature | 700–1200 °C | — |
Temperature | 800–1100 °C | — |
Pressure | 100–250 Torr | — |
Temperature | 875–1050 °C | — |
Pressure | 1–200 Torr | — |
Pressure | 1–100 Torr | — |
Pressure | 1–50 Torr | — |
Temperature | 450–900 °C | — |
Temperature | 500–850 °C | — |
Temperature | 550–800 °C | — |
Temperature | 600–750 °C | — |
Pressure | 25–400 Torr | — |
Pressure | 0.2–50 Torr | — |
Pressure | 0.1–200 Torr | — |
Thickness | 1–10 nm | — |
Thickness | 1–8 nm | — |
Thickness | 1–6 nm | — |
Thickness | 1–4 nm | — |
Thickness | 1–2 nm | — |
Pressure | 0.1–760 Torr | — |
Pressure | 0.1–500 Torr | — |
Temperature | 400–850 °C | — |
Temperature | 450–800 °C | — |
Temperature | 500–750 °C | — |
Temperature | 400–700 °C | — |
Temperature | 500–650 °C | — |
Thickness | 1–100 nm | — |
Thickness | 0.5–50 nm | — |
Thickness | 25–35 nm | — |
Voltage | 0.01–0.3 V | — |
Voltage | 0.05–0.3 V | — |
Voltage | 0.1–0.2 V | — |
Pressure | ≤ 760 Torr | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 25 nm | — |
Thickness | ≤ 20 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 5 nm | — |
Duration | ≤ 5 minutes | — |
Duration | ≤ 4 minutes | — |
Duration | ≤ 2 minutes | — |
Duration | ≤ 1 minute | — |
Pressure | ≤ 300 Torr | — |
Temperature | ≤ 900 °C | — |
Pressure | ≤ 250 Torr | — |
Pressure | ≤ 200 Torr | — |
Pressure | ≤ 1 Torr | — |
Pressure | ≤ 50 Torr | — |
Pressure | ≤ 10 Torr | — |
Duration | ≤ 6 minutes | — |
Duration | ≤ 3 minutes | — |
Temperature | ≤ 1e+50 °C | — |
Temperature | ≤ 850 °C | — |
Temperature | ≤ 800 °C | — |
Temperature | ≤ 700 °C | — |
Temperature | ≤ 600 °C | — |
Pressure | ≤ 500 Torr | — |
Thickness | ≤ 30 mm | — |
Thickness | ≤ 20 mm | — |
Thickness | ≤ 8 nm | — |
Thickness | ≤ 6 nm | — |
Thickness | ≤ 4 nm | — |
Thickness | ≤ 2 nm | — |
Temperature | ≤ 950 °C | — |
Voltage | ≤ 0.3 V | — |
Voltage | ≤ 0.1 V | — |
Voltage | ≤ 0.2 V | — |
Voltage | ≤ 0.05 V | — |
Thickness | ≥ 10 nm | — |
Thickness | ≥ 20 nm | — |
Thickness | ≥ 30 nm | — |
Temperature | ≥ 500 °C | — |
Temperature | ≥ 600 °C | — |
Temperature | ≥ 700 °C | — |
Temperature | ≥ 800 °C | — |
Temperature | ≥ 850 °C | — |
Temperature | ≥ 900 °C | — |
Temperature | ≥ 950 °C | — |
Temperature | ≥ 1 °C | — |
Temperature | ≥ 1100 °C | — |
Temperature | ≥ 1200 °C | — |
Duration | ≥ 30 sec | — |
Duration | ≥ 60 sec | — |
Duration | ≥ 120 sec | — |
Duration | ≥ 240 sec | — |
Duration | ≥ 90 sec | — |
Pressure | ≥ 0.1 Torr | — |
Pressure | ≥ 10 Torr | — |
Pressure | ≥ 1 Torr | — |
Pressure | ≥ 250 Torr | — |
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
FIG. 9 show device structures used to evaluate the performance of n/p-(A l,In)GaN tunnel junctions and buried activated p--(A l,In)GaN layers fabricated using …
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
| 500–1000 °C |
| — |
Temperature | 600–1000 °C | — |
Temperature | 700–1000 °C | — |
Temperature | 400–950 °C | — |
Temperature | 500–950 °C | — |
Temperature | 600–950 °C | — |
Temperature | 700–950 °C | — |
Temperature | 400–900 °C | — |
Temperature | 500–900 °C | — |
Temperature | 600–900 °C | — |
Temperature | 700–900 °C | — |
Temperature | 750–850 °C | — |
Pressure | 0.1–300 Torr | — |
Pressure | 0.1–100 Torr | — |
Pressure | 0.1–50 Torr | — |
Pressure | 0.1–25 Torr | — |
Pressure | 0.1–15 Torr | — |
Pressure | 0.5–300 Torr | — |
Pressure | 0.5–100 Torr | — |
Pressure | 0.5–50 Torr | — |
Pressure | 0.5–25 Torr | — |
Pressure | 0.5–15 Torr | — |
Pressure | 1–10 Torr | — |
Temperature | 400–1050 °C | — |
Pressure | 1–300 Torr | — |
Pressure | 0.1–10 Torr | — |
Temperature | 500–1050 °C | — |
Pressure | 1–760 Torr | — |
Pressure | 1–500 Torr | — |
Pressure | 5–275 Torr | — |
Pressure | 10–250 Torr | — |
Pressure | 50–200 Torr | — |
Temperature | 500–1200 °C | — |
Temperature | 500–1100 °C | — |
Temperature | 600–1050 °C | — |
Temperature | 700–1050 °C | — |
Temperature | 800–1050 °C | — |
Duration | 5–5 minutes | — |
Duration | 1–4 minutes | — |
Duration | 1–3 minutes | — |
Temperature | 700–1200 °C | — |
Temperature | 800–1100 °C | — |
Pressure | 100–250 Torr | — |
Temperature | 875–1050 °C | — |
Pressure | 1–200 Torr | — |
Pressure | 1–100 Torr | — |
Pressure | 1–50 Torr | — |
Temperature | 450–900 °C | — |
Temperature | 500–850 °C | — |
Temperature | 550–800 °C | — |
Temperature | 600–750 °C | — |
Pressure | 25–400 Torr | — |
Pressure | 0.2–50 Torr | — |
Pressure | 0.1–200 Torr | — |
Thickness | 1–10 nm | — |
Thickness | 1–8 nm | — |
Thickness | 1–6 nm | — |
Thickness | 1–4 nm | — |
Thickness | 1–2 nm | — |
Pressure | 0.1–760 Torr | — |
Pressure | 0.1–500 Torr | — |
Temperature | 400–850 °C | — |
Temperature | 450–800 °C | — |
Temperature | 500–750 °C | — |
Temperature | 400–700 °C | — |
Temperature | 500–650 °C | — |
Thickness | 1–100 nm | — |
Thickness | 0.5–50 nm | — |
Thickness | 25–35 nm | — |
Voltage | 0.01–0.3 V | — |
Voltage | 0.05–0.3 V | — |
Voltage | 0.1–0.2 V | — |
Pressure | ≤ 760 Torr | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 25 nm | — |
Thickness | ≤ 20 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 5 nm | — |
Duration | ≤ 5 minutes | — |
Duration | ≤ 4 minutes | — |
Duration | ≤ 2 minutes | — |
Duration | ≤ 1 minute | — |
Pressure | ≤ 300 Torr | — |
Temperature | ≤ 900 °C | — |
Pressure | ≤ 250 Torr | — |
Pressure | ≤ 200 Torr | — |
Pressure | ≤ 1 Torr | — |
Pressure | ≤ 50 Torr | — |
Pressure | ≤ 10 Torr | — |
Duration | ≤ 6 minutes | — |
Duration | ≤ 3 minutes | — |
Temperature | ≤ 1e+50 °C | — |
Temperature | ≤ 850 °C | — |
Temperature | ≤ 800 °C | — |
Temperature | ≤ 700 °C | — |
Temperature | ≤ 600 °C | — |
Pressure | ≤ 500 Torr | — |
Thickness | ≤ 30 mm | — |
Thickness | ≤ 20 mm | — |
Thickness | ≤ 8 nm | — |
Thickness | ≤ 6 nm | — |
Thickness | ≤ 4 nm | — |
Thickness | ≤ 2 nm | — |
Temperature | ≤ 950 °C | — |
Voltage | ≤ 0.3 V | — |
Voltage | ≤ 0.1 V | — |
Voltage | ≤ 0.2 V | — |
Voltage | ≤ 0.05 V | — |
Thickness | ≥ 10 nm | — |
Thickness | ≥ 20 nm | — |
Thickness | ≥ 30 nm | — |
Temperature | ≥ 500 °C | — |
Temperature | ≥ 600 °C | — |
Temperature | ≥ 700 °C | — |
Temperature | ≥ 800 °C | — |
Temperature | ≥ 850 °C | — |
Temperature | ≥ 900 °C | — |
Temperature | ≥ 950 °C | — |
Temperature | ≥ 1 °C | — |
Temperature | ≥ 1100 °C | — |
Temperature | ≥ 1200 °C | — |
Duration | ≥ 30 sec | — |
Duration | ≥ 60 sec | — |
Duration | ≥ 120 sec | — |
Duration | ≥ 240 sec | — |
Duration | ≥ 90 sec | — |
Pressure | ≥ 0.1 Torr | — |
Pressure | ≥ 10 Torr | — |
Pressure | ≥ 1 Torr | — |
Pressure | ≥ 250 Torr | — |
FIG. 8 shows a cross-sectional view of a commercial blue MQW LED including sapphire substrate 801, u-GaN layer 802, n-GaN layer 803, multi-quantum well layer …
FIG. 9 show device structures used to evaluate the performance of n/p-(A l,In)GaN tunnel junctions and buried activated p--(A l,In)GaN layers fabricated using …
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIG. 12B shows IV curves for a partial MQW LED with p +/p-GaN layers grown by MOCVD grown over the uppermost LED layer before (dashed line) and after (solid …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIGS. 13A and 13B, respectively. The quality of the electroluminescence was comparable demonstrating that the n/p-tunnel junction did not degrade the …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 14B shows IV curves for 1 TS p-GaN on a commercial partial LED including exposure of the p-GaN layer to a N 2 environment and overgrowth of an n */n-GaN …
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
FIG. 17, Table 4), and corresponding to the devices having the IV curves shown in
| 500–1000 °C |
| — |
Temperature | 600–1000 °C | — |
Temperature | 700–1000 °C | — |
Temperature | 400–950 °C | — |
Temperature | 500–950 °C | — |
Temperature | 600–950 °C | — |
Temperature | 700–950 °C | — |
Temperature | 400–900 °C | — |
Temperature | 500–900 °C | — |
Temperature | 600–900 °C | — |
Temperature | 700–900 °C | — |
Temperature | 750–850 °C | — |
Pressure | 0.1–300 Torr | — |
Pressure | 0.1–100 Torr | — |
Pressure | 0.1–50 Torr | — |
Pressure | 0.1–25 Torr | — |
Pressure | 0.1–15 Torr | — |
Pressure | 0.5–300 Torr | — |
Pressure | 0.5–100 Torr | — |
Pressure | 0.5–50 Torr | — |
Pressure | 0.5–25 Torr | — |
Pressure | 0.5–15 Torr | — |
Pressure | 1–10 Torr | — |
Temperature | 400–1050 °C | — |
Pressure | 1–300 Torr | — |
Pressure | 0.1–10 Torr | — |
Temperature | 500–1050 °C | — |
Pressure | 1–760 Torr | — |
Pressure | 1–500 Torr | — |
Pressure | 5–275 Torr | — |
Pressure | 10–250 Torr | — |
Pressure | 50–200 Torr | — |
Temperature | 500–1200 °C | — |
Temperature | 500–1100 °C | — |
Temperature | 600–1050 °C | — |
Temperature | 700–1050 °C | — |
Temperature | 800–1050 °C | — |
Duration | 5–5 minutes | — |
Duration | 1–4 minutes | — |
Duration | 1–3 minutes | — |
Temperature | 700–1200 °C | — |
Temperature | 800–1100 °C | — |
Pressure | 100–250 Torr | — |
Temperature | 875–1050 °C | — |
Pressure | 1–200 Torr | — |
Pressure | 1–100 Torr | — |
Pressure | 1–50 Torr | — |
Temperature | 450–900 °C | — |
Temperature | 500–850 °C | — |
Temperature | 550–800 °C | — |
Temperature | 600–750 °C | — |
Pressure | 25–400 Torr | — |
Pressure | 0.2–50 Torr | — |
Pressure | 0.1–200 Torr | — |
Thickness | 1–10 nm | — |
Thickness | 1–8 nm | — |
Thickness | 1–6 nm | — |
Thickness | 1–4 nm | — |
Thickness | 1–2 nm | — |
Pressure | 0.1–760 Torr | — |
Pressure | 0.1–500 Torr | — |
Temperature | 400–850 °C | — |
Temperature | 450–800 °C | — |
Temperature | 500–750 °C | — |
Temperature | 400–700 °C | — |
Temperature | 500–650 °C | — |
Thickness | 1–100 nm | — |
Thickness | 0.5–50 nm | — |
Thickness | 25–35 nm | — |
Voltage | 0.01–0.3 V | — |
Voltage | 0.05–0.3 V | — |
Voltage | 0.1–0.2 V | — |
Pressure | ≤ 760 Torr | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 25 nm | — |
Thickness | ≤ 20 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 5 nm | — |
Duration | ≤ 5 minutes | — |
Duration | ≤ 4 minutes | — |
Duration | ≤ 2 minutes | — |
Duration | ≤ 1 minute | — |
Pressure | ≤ 300 Torr | — |
Temperature | ≤ 900 °C | — |
Pressure | ≤ 250 Torr | — |
Pressure | ≤ 200 Torr | — |
Pressure | ≤ 1 Torr | — |
Pressure | ≤ 50 Torr | — |
Pressure | ≤ 10 Torr | — |
Duration | ≤ 6 minutes | — |
Duration | ≤ 3 minutes | — |
Temperature | ≤ 1e+50 °C | — |
Temperature | ≤ 850 °C | — |
Temperature | ≤ 800 °C | — |
Temperature | ≤ 700 °C | — |
Temperature | ≤ 600 °C | — |
Pressure | ≤ 500 Torr | — |
Thickness | ≤ 30 mm | — |
Thickness | ≤ 20 mm | — |
Thickness | ≤ 8 nm | — |
Thickness | ≤ 6 nm | — |
Thickness | ≤ 4 nm | — |
Thickness | ≤ 2 nm | — |
Temperature | ≤ 950 °C | — |
Voltage | ≤ 0.3 V | — |
Voltage | ≤ 0.1 V | — |
Voltage | ≤ 0.2 V | — |
Voltage | ≤ 0.05 V | — |
Thickness | ≥ 10 nm | — |
Thickness | ≥ 20 nm | — |
Thickness | ≥ 30 nm | — |
Temperature | ≥ 500 °C | — |
Temperature | ≥ 600 °C | — |
Temperature | ≥ 700 °C | — |
Temperature | ≥ 800 °C | — |
Temperature | ≥ 850 °C | — |
Temperature | ≥ 900 °C | — |
Temperature | ≥ 950 °C | — |
Temperature | ≥ 1 °C | — |
Temperature | ≥ 1100 °C | — |
Temperature | ≥ 1200 °C | — |
Duration | ≥ 30 sec | — |
Duration | ≥ 60 sec | — |
Duration | ≥ 120 sec | — |
Duration | ≥ 240 sec | — |
Duration | ≥ 90 sec | — |
Pressure | ≥ 0.1 Torr | — |
Pressure | ≥ 10 Torr | — |
Pressure | ≥ 1 Torr | — |
Pressure | ≥ 250 Torr | — |