Patent
US 11,626,483LOW-LEAKAGE REGROWN GAN P-N JUNCTIONS FOR GAN POWER DEVICES
Yuji Zhao
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,626,483Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B depicts etched surface 104 of UID GaN layer 102. Etched surface 104 can be treated to reduce surface contaminants (e.g., with UV-ozone, strong acid …
FIG. 2D depicts bipolar junction transistor 206 including regrownp-GAN. EXAMPLES [0015] Samples were grown homoepitaxially by metalorganic chemical vapor …
FIGS. 3A and 3B, the reverse leakage currents for both samples were large and the breakdown voltages were about 100 V. These results indicate that surfaces …
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 5 shows that the regrown sample with the four-step-etching recipe exhibited a high breakdown voltage of 1270 V. [0022] Ideality factor is another factor …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a regrown GaN p-n junction, the method comprising: depositing a n-GaN layer on a substrate comprising n + -GaN; etching a surface of the n-GaN layer to yield an etched surface; depositing ap-GaN layer on the etched surface; etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate; and passivating a portion of the p-GaN layer around an edge of the mesa, wherein the regrown GaNp-n junction is defined at an interface between the n-GaN layer and the p-GaN layer.
The method of claim 1, wherein the n-GaN layer is unintentionally doped.
The method of claim 1, wherein depositing the n-GaN layer comprises metalorganic chemical vapor deposition.
The method of claim 1, wherein etching the surface of the n-GaN layer comprises wet etching.
The method of claim 1, wherein etching the surface of the n-GaN layer occurs in multiple steps.
The method of claim 1, further comprising cleaning the etched surface before depositing the p-GaN layer.
The method of claim 1, further comprising depositing an insertion layer between the etched surface and the p-GaN l ayer.
The method of claim 1, further comprising activating the p-GaN layer before etching the portion of the n-GaN layer and the portion of the p-GaN layer.
The method of claim 1, wherein etching the portion of the n -GaN layer and the portion of the p-GaN layer comprises dry etching.
The method of claim 1, wherein passivating the portion of the p-GaN layer comprises hydrogen-plasma passivation.
The method of claim 1, further comprising depositing a first metal stack on an outer surface of the p-GaN layer and a second metal stack on an outer surface of the substrate.
The regrown GaNp-n junction of claim 1 5, wherein the substrate comprises n + -GaN.
A regrown GaN p-n junction comprisin g: a substrate; a n-GaN layer on the substrate, wherein a surface of the n -GaN layer is etched; a p-GaN layer on the etched surface; a mesa defined by an etched portion of the n -GaN layer and an etched portion of the p- GaN layer; and a passivated portion of the p -GaN layer around an edge of the mesa, wherein an interface between the n -GaN layer and the p-GaN layer defines the regrown GaN p-n junction.
The regrown GaNp-n junction of claim 15, further comprising an insertion layer between the n-GaN layer and the p-GaN layer.
The regrown GaN p-n junction of claim 15, wherein a differential on-resistance of the GaNp-n junction is about 8 mQ cm 2.
A device comprising the regrown GaNp-n junction of claim 15.
Embodiments described in the patent, grouped by the materials and process steps they use.
6 materials5 process steps
A free-standing c-plane n+-GaN substrate is used. A UID GaN drift layer (~9 µm, electron concentration ~10¹⁶ cm⁻³) is grown homoepitaxially by MOCVD. The UID GaN surface is etched by ICP (chlorine-based) using a multiple-RF-power recipe with four steps of decreasing RF power (70 W → 35 W → 5 W → 2 W). The etched surface is treated with UV-ozone and/or strong acid baths. An optional insertion layer of thin UID GaN (~25–75 nm) is deposited. Regrown p-GaN layer (~400–600 nm) is deposited by MOCVD using bis(cyclopentadienyl)magnesium as p-type dopant at ~900–1040°C. p-GaN activation is carried out by rapid thermal annealing at ~600–700°C for ~10–30 min in inert atmosphere. Pd/Ni/Au (20/30/50 nm) p-contact is deposited by electron beam evaporation. Mesa isolation and hydrogen-plasma passivation edge terminations are formed by ICP dry etching. Ti/Al/Ni/Au (20/130/50/150 nm) backside n-contact is deposited. Metal stacks subjected to RTA.
Layer stacks claimed or described, ordered top of device to substrate.
regrown GaN p-n junction diode
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2D depicts bipolar junction transistor 206 including regrownp-GAN. EXAMPLES [0015] Samples were grown homoepitaxially by metalorganic chemical vapor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage (four-step etching recipe) | 1200–1300 V | — |
breakdown voltage (with insertion layer) | 1250–1350 V | — |
breakdown voltage (best example) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,626,483Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B depicts etched surface 104 of UID GaN layer 102. Etched surface 104 can be treated to reduce surface contaminants (e.g., with UV-ozone, strong acid …
FIG. 2D depicts bipolar junction transistor 206 including regrownp-GAN. EXAMPLES [0015] Samples were grown homoepitaxially by metalorganic chemical vapor …
FIGS. 3A and 3B, the reverse leakage currents for both samples were large and the breakdown voltages were about 100 V. These results indicate that surfaces …
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 5 shows that the regrown sample with the four-step-etching recipe exhibited a high breakdown voltage of 1270 V. [0022] Ideality factor is another factor …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a regrown GaN p-n junction, the method comprising: depositing a n-GaN layer on a substrate comprising n + -GaN; etching a surface of the n-GaN layer to yield an etched surface; depositing ap-GaN layer on the etched surface; etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate; and passivating a portion of the p-GaN layer around an edge of the mesa, wherein the regrown GaNp-n junction is defined at an interface between the n-GaN layer and the p-GaN layer.
The method of claim 1, wherein the n-GaN layer is unintentionally doped.
The method of claim 1, wherein depositing the n-GaN layer comprises metalorganic chemical vapor deposition.
The method of claim 1, wherein etching the surface of the n-GaN layer comprises wet etching.
The method of claim 1, wherein etching the surface of the n-GaN layer occurs in multiple steps.
The method of claim 1, further comprising cleaning the etched surface before depositing the p-GaN layer.
The method of claim 1, further comprising depositing an insertion layer between the etched surface and the p-GaN l ayer.
The method of claim 1, further comprising activating the p-GaN layer before etching the portion of the n-GaN layer and the portion of the p-GaN layer.
The method of claim 1, wherein etching the portion of the n -GaN layer and the portion of the p-GaN layer comprises dry etching.
The method of claim 1, wherein passivating the portion of the p-GaN layer comprises hydrogen-plasma passivation.
The method of claim 1, further comprising depositing a first metal stack on an outer surface of the p-GaN layer and a second metal stack on an outer surface of the substrate.
The regrown GaNp-n junction of claim 1 5, wherein the substrate comprises n + -GaN.
A regrown GaN p-n junction comprisin g: a substrate; a n-GaN layer on the substrate, wherein a surface of the n -GaN layer is etched; a p-GaN layer on the etched surface; a mesa defined by an etched portion of the n -GaN layer and an etched portion of the p- GaN layer; and a passivated portion of the p -GaN layer around an edge of the mesa, wherein an interface between the n -GaN layer and the p-GaN layer defines the regrown GaN p-n junction.
The regrown GaNp-n junction of claim 15, further comprising an insertion layer between the n-GaN layer and the p-GaN layer.
The regrown GaN p-n junction of claim 15, wherein a differential on-resistance of the GaNp-n junction is about 8 mQ cm 2.
A device comprising the regrown GaNp-n junction of claim 15.
Embodiments described in the patent, grouped by the materials and process steps they use.
6 materials5 process steps
A free-standing c-plane n+-GaN substrate is used. A UID GaN drift layer (~9 µm, electron concentration ~10¹⁶ cm⁻³) is grown homoepitaxially by MOCVD. The UID GaN surface is etched by ICP (chlorine-based) using a multiple-RF-power recipe with four steps of decreasing RF power (70 W → 35 W → 5 W → 2 W). The etched surface is treated with UV-ozone and/or strong acid baths. An optional insertion layer of thin UID GaN (~25–75 nm) is deposited. Regrown p-GaN layer (~400–600 nm) is deposited by MOCVD using bis(cyclopentadienyl)magnesium as p-type dopant at ~900–1040°C. p-GaN activation is carried out by rapid thermal annealing at ~600–700°C for ~10–30 min in inert atmosphere. Pd/Ni/Au (20/30/50 nm) p-contact is deposited by electron beam evaporation. Mesa isolation and hydrogen-plasma passivation edge terminations are formed by ICP dry etching. Ti/Al/Ni/Au (20/130/50/150 nm) backside n-contact is deposited. Metal stacks subjected to RTA.
Layer stacks claimed or described, ordered top of device to substrate.
regrown GaN p-n junction diode
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2D depicts bipolar junction transistor 206 including regrownp-GAN. EXAMPLES [0015] Samples were grown homoepitaxially by metalorganic chemical vapor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage (four-step etching recipe) | 1200–1300 V | — |
breakdown voltage (with insertion layer) | 1250–1350 V | — |
breakdown voltage (best example) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,626,483Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B depicts etched surface 104 of UID GaN layer 102. Etched surface 104 can be treated to reduce surface contaminants (e.g., with UV-ozone, strong acid …
FIG. 2D depicts bipolar junction transistor 206 including regrownp-GAN. EXAMPLES [0015] Samples were grown homoepitaxially by metalorganic chemical vapor …
FIGS. 3A and 3B, the reverse leakage currents for both samples were large and the breakdown voltages were about 100 V. These results indicate that surfaces …
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 5 shows that the regrown sample with the four-step-etching recipe exhibited a high breakdown voltage of 1270 V. [0022] Ideality factor is another factor …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a regrown GaN p-n junction, the method comprising: depositing a n-GaN layer on a substrate comprising n + -GaN; etching a surface of the n-GaN layer to yield an etched surface; depositing ap-GaN layer on the etched surface; etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate; and passivating a portion of the p-GaN layer around an edge of the mesa, wherein the regrown GaNp-n junction is defined at an interface between the n-GaN layer and the p-GaN layer.
The method of claim 1, wherein the n-GaN layer is unintentionally doped.
The method of claim 1, wherein depositing the n-GaN layer comprises metalorganic chemical vapor deposition.
The method of claim 1, wherein etching the surface of the n-GaN layer comprises wet etching.
The method of claim 1, wherein etching the surface of the n-GaN layer occurs in multiple steps.
The method of claim 1, further comprising cleaning the etched surface before depositing the p-GaN layer.
The method of claim 1, further comprising depositing an insertion layer between the etched surface and the p-GaN l ayer.
The method of claim 1, further comprising activating the p-GaN layer before etching the portion of the n-GaN layer and the portion of the p-GaN layer.
The method of claim 1, wherein etching the portion of the n -GaN layer and the portion of the p-GaN layer comprises dry etching.
The method of claim 1, wherein passivating the portion of the p-GaN layer comprises hydrogen-plasma passivation.
The method of claim 1, further comprising depositing a first metal stack on an outer surface of the p-GaN layer and a second metal stack on an outer surface of the substrate.
The regrown GaNp-n junction of claim 1 5, wherein the substrate comprises n + -GaN.
A regrown GaN p-n junction comprisin g: a substrate; a n-GaN layer on the substrate, wherein a surface of the n -GaN layer is etched; a p-GaN layer on the etched surface; a mesa defined by an etched portion of the n -GaN layer and an etched portion of the p- GaN layer; and a passivated portion of the p -GaN layer around an edge of the mesa, wherein an interface between the n -GaN layer and the p-GaN layer defines the regrown GaN p-n junction.
The regrown GaNp-n junction of claim 15, further comprising an insertion layer between the n-GaN layer and the p-GaN layer.
The regrown GaN p-n junction of claim 15, wherein a differential on-resistance of the GaNp-n junction is about 8 mQ cm 2.
A device comprising the regrown GaNp-n junction of claim 15.
Embodiments described in the patent, grouped by the materials and process steps they use.
6 materials5 process steps
A free-standing c-plane n+-GaN substrate is used. A UID GaN drift layer (~9 µm, electron concentration ~10¹⁶ cm⁻³) is grown homoepitaxially by MOCVD. The UID GaN surface is etched by ICP (chlorine-based) using a multiple-RF-power recipe with four steps of decreasing RF power (70 W → 35 W → 5 W → 2 W). The etched surface is treated with UV-ozone and/or strong acid baths. An optional insertion layer of thin UID GaN (~25–75 nm) is deposited. Regrown p-GaN layer (~400–600 nm) is deposited by MOCVD using bis(cyclopentadienyl)magnesium as p-type dopant at ~900–1040°C. p-GaN activation is carried out by rapid thermal annealing at ~600–700°C for ~10–30 min in inert atmosphere. Pd/Ni/Au (20/30/50 nm) p-contact is deposited by electron beam evaporation. Mesa isolation and hydrogen-plasma passivation edge terminations are formed by ICP dry etching. Ti/Al/Ni/Au (20/130/50/150 nm) backside n-contact is deposited. Metal stacks subjected to RTA.
Layer stacks claimed or described, ordered top of device to substrate.
regrown GaN p-n junction diode
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2D depicts bipolar junction transistor 206 including regrownp-GAN. EXAMPLES [0015] Samples were grown homoepitaxially by metalorganic chemical vapor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage (four-step etching recipe) | 1200–1300 V | — |
breakdown voltage (with insertion layer) | 1250–1350 V | — |
breakdown voltage (best example) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,626,483Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B depicts etched surface 104 of UID GaN layer 102. Etched surface 104 can be treated to reduce surface contaminants (e.g., with UV-ozone, strong acid …
FIG. 2D depicts bipolar junction transistor 206 including regrownp-GAN. EXAMPLES [0015] Samples were grown homoepitaxially by metalorganic chemical vapor …
FIGS. 3A and 3B, the reverse leakage currents for both samples were large and the breakdown voltages were about 100 V. These results indicate that surfaces …
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 5 shows that the regrown sample with the four-step-etching recipe exhibited a high breakdown voltage of 1270 V. [0022] Ideality factor is another factor …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a regrown GaN p-n junction, the method comprising: depositing a n-GaN layer on a substrate comprising n + -GaN; etching a surface of the n-GaN layer to yield an etched surface; depositing ap-GaN layer on the etched surface; etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate; and passivating a portion of the p-GaN layer around an edge of the mesa, wherein the regrown GaNp-n junction is defined at an interface between the n-GaN layer and the p-GaN layer.
The method of claim 1, wherein the n-GaN layer is unintentionally doped.
The method of claim 1, wherein depositing the n-GaN layer comprises metalorganic chemical vapor deposition.
The method of claim 1, wherein etching the surface of the n-GaN layer comprises wet etching.
The method of claim 1, wherein etching the surface of the n-GaN layer occurs in multiple steps.
The method of claim 1, further comprising cleaning the etched surface before depositing the p-GaN layer.
The method of claim 1, further comprising depositing an insertion layer between the etched surface and the p-GaN l ayer.
The method of claim 1, further comprising activating the p-GaN layer before etching the portion of the n-GaN layer and the portion of the p-GaN layer.
The method of claim 1, wherein etching the portion of the n -GaN layer and the portion of the p-GaN layer comprises dry etching.
The method of claim 1, wherein passivating the portion of the p-GaN layer comprises hydrogen-plasma passivation.
The method of claim 1, further comprising depositing a first metal stack on an outer surface of the p-GaN layer and a second metal stack on an outer surface of the substrate.
The regrown GaNp-n junction of claim 1 5, wherein the substrate comprises n + -GaN.
A regrown GaN p-n junction comprisin g: a substrate; a n-GaN layer on the substrate, wherein a surface of the n -GaN layer is etched; a p-GaN layer on the etched surface; a mesa defined by an etched portion of the n -GaN layer and an etched portion of the p- GaN layer; and a passivated portion of the p -GaN layer around an edge of the mesa, wherein an interface between the n -GaN layer and the p-GaN layer defines the regrown GaN p-n junction.
The regrown GaNp-n junction of claim 15, further comprising an insertion layer between the n-GaN layer and the p-GaN layer.
The regrown GaN p-n junction of claim 15, wherein a differential on-resistance of the GaNp-n junction is about 8 mQ cm 2.
A device comprising the regrown GaNp-n junction of claim 15.
Embodiments described in the patent, grouped by the materials and process steps they use.
6 materials5 process steps
A free-standing c-plane n+-GaN substrate is used. A UID GaN drift layer (~9 µm, electron concentration ~10¹⁶ cm⁻³) is grown homoepitaxially by MOCVD. The UID GaN surface is etched by ICP (chlorine-based) using a multiple-RF-power recipe with four steps of decreasing RF power (70 W → 35 W → 5 W → 2 W). The etched surface is treated with UV-ozone and/or strong acid baths. An optional insertion layer of thin UID GaN (~25–75 nm) is deposited. Regrown p-GaN layer (~400–600 nm) is deposited by MOCVD using bis(cyclopentadienyl)magnesium as p-type dopant at ~900–1040°C. p-GaN activation is carried out by rapid thermal annealing at ~600–700°C for ~10–30 min in inert atmosphere. Pd/Ni/Au (20/30/50 nm) p-contact is deposited by electron beam evaporation. Mesa isolation and hydrogen-plasma passivation edge terminations are formed by ICP dry etching. Ti/Al/Ni/Au (20/130/50/150 nm) backside n-contact is deposited. Metal stacks subjected to RTA.
Layer stacks claimed or described, ordered top of device to substrate.
regrown GaN p-n junction diode
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2D depicts bipolar junction transistor 206 including regrownp-GAN. EXAMPLES [0015] Samples were grown homoepitaxially by metalorganic chemical vapor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage (four-step etching recipe) | 1200–1300 V | — |
breakdown voltage (with insertion layer) | 1250–1350 V | — |
breakdown voltage (best example) |
Related documents with shared materials, methods, properties, or citations.
junction barrier Schottky (JBS) diode
No layer stack recorded.
device with floating field rings
No layer stack recorded.
field effect transistor (FET)
No layer stack recorded.
bipolar junction transistor (BJT)
No layer stack recorded.
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 5 shows that the regrown sample with the four-step-etching recipe exhibited a high breakdown voltage of 1270 V. [0022] Ideality factor is another factor …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
| 1270 V |
| — |
differential on-resistance (claimed value) | 8 mΩ·cm² | — |
differential on-resistance (description example) | 0.8 mΩ·cm² | — |
reverse leakage current at -600 V | 10 nA | — |
— | 5–35 W | — |
Temperature | 970–1040 °C | — |
Temperature | 600–700 °C | — |
— | 200–600 W | — |
— | 2–70 W | — |
— | 35–70 W | — |
— | 2–5 W | — |
Thickness | 25–75 nm | — |
Thickness | 400–600 nm | — |
Temperature | 900–1040 °C | — |
Voltage | ≥ 1200 V | — |
junction barrier Schottky (JBS) diode
No layer stack recorded.
device with floating field rings
No layer stack recorded.
field effect transistor (FET)
No layer stack recorded.
bipolar junction transistor (BJT)
No layer stack recorded.
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 5 shows that the regrown sample with the four-step-etching recipe exhibited a high breakdown voltage of 1270 V. [0022] Ideality factor is another factor …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
| 1270 V |
| — |
differential on-resistance (claimed value) | 8 mΩ·cm² | — |
differential on-resistance (description example) | 0.8 mΩ·cm² | — |
reverse leakage current at -600 V | 10 nA | — |
— | 5–35 W | — |
Temperature | 970–1040 °C | — |
Temperature | 600–700 °C | — |
— | 200–600 W | — |
— | 2–70 W | — |
— | 35–70 W | — |
— | 2–5 W | — |
Thickness | 25–75 nm | — |
Thickness | 400–600 nm | — |
Temperature | 900–1040 °C | — |
Voltage | ≥ 1200 V | — |
junction barrier Schottky (JBS) diode
No layer stack recorded.
device with floating field rings
No layer stack recorded.
field effect transistor (FET)
No layer stack recorded.
bipolar junction transistor (BJT)
No layer stack recorded.
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 5 shows that the regrown sample with the four-step-etching recipe exhibited a high breakdown voltage of 1270 V. [0022] Ideality factor is another factor …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
| 1270 V |
| — |
differential on-resistance (claimed value) | 8 mΩ·cm² | — |
differential on-resistance (description example) | 0.8 mΩ·cm² | — |
reverse leakage current at -600 V | 10 nA | — |
— | 5–35 W | — |
Temperature | 970–1040 °C | — |
Temperature | 600–700 °C | — |
— | 200–600 W | — |
— | 2–70 W | — |
— | 35–70 W | — |
— | 2–5 W | — |
Thickness | 25–75 nm | — |
Thickness | 400–600 nm | — |
Temperature | 900–1040 °C | — |
Voltage | ≥ 1200 V | — |
junction barrier Schottky (JBS) diode
No layer stack recorded.
device with floating field rings
No layer stack recorded.
field effect transistor (FET)
No layer stack recorded.
bipolar junction transistor (BJT)
No layer stack recorded.
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 4A. The as-grown sample showed a low and constant charge concentration on the order of 1 0 16 cm⁻³. However, the regrown samples had high charge …
FIG. 5 shows that the regrown sample with the four-step-etching recipe exhibited a high breakdown voltage of 1270 V. [0022] Ideality factor is another factor …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
FIG. 6B shows a forward I-V curve and ideality factor in logarithmic scale. DETAILED DESCRIPTION [0007] This disclosure describes high performance GaNp-n …
| 1270 V |
| — |
differential on-resistance (claimed value) | 8 mΩ·cm² | — |
differential on-resistance (description example) | 0.8 mΩ·cm² | — |
reverse leakage current at -600 V | 10 nA | — |
— | 5–35 W | — |
Temperature | 970–1040 °C | — |
Temperature | 600–700 °C | — |
— | 200–600 W | — |
— | 2–70 W | — |
— | 35–70 W | — |
— | 2–5 W | — |
Thickness | 25–75 nm | — |
Thickness | 400–600 nm | — |
Temperature | 900–1040 °C | — |
Voltage | ≥ 1200 V | — |