Patent
US 9,287,389METHOD AND SYSTEM FOR DOPING CONTROL IN GALLIUM NITRIDE BASED DEVICES
Isik C. Kizilyalli
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,287,389Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the dopant concentration for an n-type dopant is illustrated as a function of the breakdown voltage. For the dopant 20 concentration curve, the …
FIG. 2 is a simplified schematic diagram of an epitaxial structure suitable to high 10 voltage vertical operation according to an embodiment of the present …
FIG. 3 is a simplified flowchart illustrating a method of fabricating an epitaxial layer with controlled doping according to an embodiment of the present …
FIG. 4 is a simplified schematic cross-section of vertical junction field effect transistor 10 (JFET) according to an embodiment of the present invention. The …
FIG. 5, a substrate 500 is provided (e.g., 30 an n-type GaN substrate) with an epitaxial layer 501 coupled to the substrate. In the illustrated 13 embodiment, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical JFET formed by a method comprising: providing a GaN-based substrate having a surface and a first electrical contact opposing the surface; forming a GaN-based drift layer coupled to the GaN-based substrate and operable to conduct current in a direction substantially orthogonal to the surface, wherein forming the GaN-based drift layer comprises doping the drift layer with indium to cause the indium concentration of the drift layer to be less than about 1 x 10 16 cm- 3 and to cause the carbon concentration of the drift layer to be less than about 1 x 10 16 cm 3;forming an n-type channel layer coupled to the GaN-based drift layer; forming an n-contact layer coupled to the GaN-based drift layer and substantially parallel to the surface; forming a second electrical contact electrically coupled to the n-contact layer; forming a p-type gate region electrically coupled to the n-type channel layer; and forming a third electrical contact electrically coupled to the p-type gate region.
The vertical JFET of claim 1, wherein a concentration of indium in the n-type drift layer is between 1 x 10 15 cm- 3 and 1 x 10 16 cm- 3.
The vertical JFET of claim 1, wherein a thickness of the n-type drift layer is greater than 1 m.
The vertical JFET of claim 1, wherein the n-type channel layer comprises a GaN layer.
The vertical JFET of claim 1, wherein the n-type drift layer comprises an n-type GaN layer.
The vertical JFET of claim 1, wherein the GaN- based drift layer is formed by a metal organic chemical vapor deposition (MOC V D) process.
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed in an environment containing at least one of t ri -methyl indium (T MI), t ri -ethyl indium (TEI), and ethyldimethylindium (EDMI).
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed in an environment containing hydrogen.
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed at a temperature greater than 1000 °C.
A method of manufacturing a vertical JFET, the method comprising: providing a GaN-based substrate having a surface and a first electrical contact opposing the surface; forming a GaN-based drift layer coupled to the GaN-based substrate and operable to conduct current in a direction substantially orthogonal to the surface, wherein forming the GaN-based drift layer comprises doping the drift layer with indium to cause the indium concentration of the drift layer to be less than about 1 x 10 16 cm- 3 and to cause the carbon concentration of the drift layer to be less than about 1 x 10 16 cm 3;forming an n-type channel layer coupled to the GaN-based drift layer; forming an n-contact layer coupled to the GaN-based drift layer and substantially parallel to the surface; forming a second electrical contact electrically coupled to the n-contact layer; forming a p-type gate region electrically coupled to the n-type channel layer; and forming a third electrical contact electrically coupled to the p-type gate region.
The method of claim 11, wherein a concentration of indium in the n-type drift layer is between 1 x 10 15 cm⁻³ and 1 x 10 16 cm- 3.
The method of claim 11, wherein a thickness of the n-type drift layer is greater than 1 m.
The method of claim 11, wherein the n-type channel layer comprises a GaN layer.
The method of claim 11, wherein the n-type drift layer comprises an n-type GaN layer.
The method of claim 11, wherein the GaN-based drift layer is formed by metal a metal organic chemical vapor deposition (MOC V D) process.
The method of claim 11, wherein the GaN-based containing at least one of t ri -methyl indium (TMI), ethyldimethylindium (EDMI).
The method of claim 11, wherein the GaN-based containing hydrogen.
The method of claim 11, wherein the GaN-based than 1000 °C. Page 4 of 6 during the MOCVD process, a metalorganic drift layer is formed in an environment t ri -ethyl indium (TE I), and drift layer is formed in an environment drift layer is formed at a temperature greater
Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field-effect transistor (vertical JFET)
Materials described outside the worked examples.
GaN-based substrate
GaN
p-type gate region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the dopant concentration for an n-type dopant is illustrated as a function of the breakdown voltage. For the dopant 20 concentration curve, the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
indium concentration in drift layer (upper bound) | 10000000000000000 | GaN |
carbon concentration in drift layer (upper bound) | 10000000000000000 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,287,389Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the dopant concentration for an n-type dopant is illustrated as a function of the breakdown voltage. For the dopant 20 concentration curve, the …
FIG. 2 is a simplified schematic diagram of an epitaxial structure suitable to high 10 voltage vertical operation according to an embodiment of the present …
FIG. 3 is a simplified flowchart illustrating a method of fabricating an epitaxial layer with controlled doping according to an embodiment of the present …
FIG. 4 is a simplified schematic cross-section of vertical junction field effect transistor 10 (JFET) according to an embodiment of the present invention. The …
FIG. 5, a substrate 500 is provided (e.g., 30 an n-type GaN substrate) with an epitaxial layer 501 coupled to the substrate. In the illustrated 13 embodiment, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical JFET formed by a method comprising: providing a GaN-based substrate having a surface and a first electrical contact opposing the surface; forming a GaN-based drift layer coupled to the GaN-based substrate and operable to conduct current in a direction substantially orthogonal to the surface, wherein forming the GaN-based drift layer comprises doping the drift layer with indium to cause the indium concentration of the drift layer to be less than about 1 x 10 16 cm- 3 and to cause the carbon concentration of the drift layer to be less than about 1 x 10 16 cm 3;forming an n-type channel layer coupled to the GaN-based drift layer; forming an n-contact layer coupled to the GaN-based drift layer and substantially parallel to the surface; forming a second electrical contact electrically coupled to the n-contact layer; forming a p-type gate region electrically coupled to the n-type channel layer; and forming a third electrical contact electrically coupled to the p-type gate region.
The vertical JFET of claim 1, wherein a concentration of indium in the n-type drift layer is between 1 x 10 15 cm- 3 and 1 x 10 16 cm- 3.
The vertical JFET of claim 1, wherein a thickness of the n-type drift layer is greater than 1 m.
The vertical JFET of claim 1, wherein the n-type channel layer comprises a GaN layer.
The vertical JFET of claim 1, wherein the n-type drift layer comprises an n-type GaN layer.
The vertical JFET of claim 1, wherein the GaN- based drift layer is formed by a metal organic chemical vapor deposition (MOC V D) process.
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed in an environment containing at least one of t ri -methyl indium (T MI), t ri -ethyl indium (TEI), and ethyldimethylindium (EDMI).
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed in an environment containing hydrogen.
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed at a temperature greater than 1000 °C.
A method of manufacturing a vertical JFET, the method comprising: providing a GaN-based substrate having a surface and a first electrical contact opposing the surface; forming a GaN-based drift layer coupled to the GaN-based substrate and operable to conduct current in a direction substantially orthogonal to the surface, wherein forming the GaN-based drift layer comprises doping the drift layer with indium to cause the indium concentration of the drift layer to be less than about 1 x 10 16 cm- 3 and to cause the carbon concentration of the drift layer to be less than about 1 x 10 16 cm 3;forming an n-type channel layer coupled to the GaN-based drift layer; forming an n-contact layer coupled to the GaN-based drift layer and substantially parallel to the surface; forming a second electrical contact electrically coupled to the n-contact layer; forming a p-type gate region electrically coupled to the n-type channel layer; and forming a third electrical contact electrically coupled to the p-type gate region.
The method of claim 11, wherein a concentration of indium in the n-type drift layer is between 1 x 10 15 cm⁻³ and 1 x 10 16 cm- 3.
The method of claim 11, wherein a thickness of the n-type drift layer is greater than 1 m.
The method of claim 11, wherein the n-type channel layer comprises a GaN layer.
The method of claim 11, wherein the n-type drift layer comprises an n-type GaN layer.
The method of claim 11, wherein the GaN-based drift layer is formed by metal a metal organic chemical vapor deposition (MOC V D) process.
The method of claim 11, wherein the GaN-based containing at least one of t ri -methyl indium (TMI), ethyldimethylindium (EDMI).
The method of claim 11, wherein the GaN-based containing hydrogen.
The method of claim 11, wherein the GaN-based than 1000 °C. Page 4 of 6 during the MOCVD process, a metalorganic drift layer is formed in an environment t ri -ethyl indium (TE I), and drift layer is formed in an environment drift layer is formed at a temperature greater
Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field-effect transistor (vertical JFET)
Materials described outside the worked examples.
GaN-based substrate
GaN
p-type gate region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the dopant concentration for an n-type dopant is illustrated as a function of the breakdown voltage. For the dopant 20 concentration curve, the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
indium concentration in drift layer (upper bound) | 10000000000000000 | GaN |
carbon concentration in drift layer (upper bound) | 10000000000000000 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,287,389Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the dopant concentration for an n-type dopant is illustrated as a function of the breakdown voltage. For the dopant 20 concentration curve, the …
FIG. 2 is a simplified schematic diagram of an epitaxial structure suitable to high 10 voltage vertical operation according to an embodiment of the present …
FIG. 3 is a simplified flowchart illustrating a method of fabricating an epitaxial layer with controlled doping according to an embodiment of the present …
FIG. 4 is a simplified schematic cross-section of vertical junction field effect transistor 10 (JFET) according to an embodiment of the present invention. The …
FIG. 5, a substrate 500 is provided (e.g., 30 an n-type GaN substrate) with an epitaxial layer 501 coupled to the substrate. In the illustrated 13 embodiment, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical JFET formed by a method comprising: providing a GaN-based substrate having a surface and a first electrical contact opposing the surface; forming a GaN-based drift layer coupled to the GaN-based substrate and operable to conduct current in a direction substantially orthogonal to the surface, wherein forming the GaN-based drift layer comprises doping the drift layer with indium to cause the indium concentration of the drift layer to be less than about 1 x 10 16 cm- 3 and to cause the carbon concentration of the drift layer to be less than about 1 x 10 16 cm 3;forming an n-type channel layer coupled to the GaN-based drift layer; forming an n-contact layer coupled to the GaN-based drift layer and substantially parallel to the surface; forming a second electrical contact electrically coupled to the n-contact layer; forming a p-type gate region electrically coupled to the n-type channel layer; and forming a third electrical contact electrically coupled to the p-type gate region.
The vertical JFET of claim 1, wherein a concentration of indium in the n-type drift layer is between 1 x 10 15 cm- 3 and 1 x 10 16 cm- 3.
The vertical JFET of claim 1, wherein a thickness of the n-type drift layer is greater than 1 m.
The vertical JFET of claim 1, wherein the n-type channel layer comprises a GaN layer.
The vertical JFET of claim 1, wherein the n-type drift layer comprises an n-type GaN layer.
The vertical JFET of claim 1, wherein the GaN- based drift layer is formed by a metal organic chemical vapor deposition (MOC V D) process.
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed in an environment containing at least one of t ri -methyl indium (T MI), t ri -ethyl indium (TEI), and ethyldimethylindium (EDMI).
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed in an environment containing hydrogen.
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed at a temperature greater than 1000 °C.
A method of manufacturing a vertical JFET, the method comprising: providing a GaN-based substrate having a surface and a first electrical contact opposing the surface; forming a GaN-based drift layer coupled to the GaN-based substrate and operable to conduct current in a direction substantially orthogonal to the surface, wherein forming the GaN-based drift layer comprises doping the drift layer with indium to cause the indium concentration of the drift layer to be less than about 1 x 10 16 cm- 3 and to cause the carbon concentration of the drift layer to be less than about 1 x 10 16 cm 3;forming an n-type channel layer coupled to the GaN-based drift layer; forming an n-contact layer coupled to the GaN-based drift layer and substantially parallel to the surface; forming a second electrical contact electrically coupled to the n-contact layer; forming a p-type gate region electrically coupled to the n-type channel layer; and forming a third electrical contact electrically coupled to the p-type gate region.
The method of claim 11, wherein a concentration of indium in the n-type drift layer is between 1 x 10 15 cm⁻³ and 1 x 10 16 cm- 3.
The method of claim 11, wherein a thickness of the n-type drift layer is greater than 1 m.
The method of claim 11, wherein the n-type channel layer comprises a GaN layer.
The method of claim 11, wherein the n-type drift layer comprises an n-type GaN layer.
The method of claim 11, wherein the GaN-based drift layer is formed by metal a metal organic chemical vapor deposition (MOC V D) process.
The method of claim 11, wherein the GaN-based containing at least one of t ri -methyl indium (TMI), ethyldimethylindium (EDMI).
The method of claim 11, wherein the GaN-based containing hydrogen.
The method of claim 11, wherein the GaN-based than 1000 °C. Page 4 of 6 during the MOCVD process, a metalorganic drift layer is formed in an environment t ri -ethyl indium (TE I), and drift layer is formed in an environment drift layer is formed at a temperature greater
Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field-effect transistor (vertical JFET)
Materials described outside the worked examples.
GaN-based substrate
GaN
p-type gate region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the dopant concentration for an n-type dopant is illustrated as a function of the breakdown voltage. For the dopant 20 concentration curve, the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
indium concentration in drift layer (upper bound) | 10000000000000000 | GaN |
carbon concentration in drift layer (upper bound) | 10000000000000000 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,287,389Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the dopant concentration for an n-type dopant is illustrated as a function of the breakdown voltage. For the dopant 20 concentration curve, the …
FIG. 2 is a simplified schematic diagram of an epitaxial structure suitable to high 10 voltage vertical operation according to an embodiment of the present …
FIG. 3 is a simplified flowchart illustrating a method of fabricating an epitaxial layer with controlled doping according to an embodiment of the present …
FIG. 4 is a simplified schematic cross-section of vertical junction field effect transistor 10 (JFET) according to an embodiment of the present invention. The …
FIG. 5, a substrate 500 is provided (e.g., 30 an n-type GaN substrate) with an epitaxial layer 501 coupled to the substrate. In the illustrated 13 embodiment, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical JFET formed by a method comprising: providing a GaN-based substrate having a surface and a first electrical contact opposing the surface; forming a GaN-based drift layer coupled to the GaN-based substrate and operable to conduct current in a direction substantially orthogonal to the surface, wherein forming the GaN-based drift layer comprises doping the drift layer with indium to cause the indium concentration of the drift layer to be less than about 1 x 10 16 cm- 3 and to cause the carbon concentration of the drift layer to be less than about 1 x 10 16 cm 3;forming an n-type channel layer coupled to the GaN-based drift layer; forming an n-contact layer coupled to the GaN-based drift layer and substantially parallel to the surface; forming a second electrical contact electrically coupled to the n-contact layer; forming a p-type gate region electrically coupled to the n-type channel layer; and forming a third electrical contact electrically coupled to the p-type gate region.
The vertical JFET of claim 1, wherein a concentration of indium in the n-type drift layer is between 1 x 10 15 cm- 3 and 1 x 10 16 cm- 3.
The vertical JFET of claim 1, wherein a thickness of the n-type drift layer is greater than 1 m.
The vertical JFET of claim 1, wherein the n-type channel layer comprises a GaN layer.
The vertical JFET of claim 1, wherein the n-type drift layer comprises an n-type GaN layer.
The vertical JFET of claim 1, wherein the GaN- based drift layer is formed by a metal organic chemical vapor deposition (MOC V D) process.
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed in an environment containing at least one of t ri -methyl indium (T MI), t ri -ethyl indium (TEI), and ethyldimethylindium (EDMI).
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed in an environment containing hydrogen.
The vertical JFET of claim 1, wherein the GaN-based drift layer is formed at a temperature greater than 1000 °C.
A method of manufacturing a vertical JFET, the method comprising: providing a GaN-based substrate having a surface and a first electrical contact opposing the surface; forming a GaN-based drift layer coupled to the GaN-based substrate and operable to conduct current in a direction substantially orthogonal to the surface, wherein forming the GaN-based drift layer comprises doping the drift layer with indium to cause the indium concentration of the drift layer to be less than about 1 x 10 16 cm- 3 and to cause the carbon concentration of the drift layer to be less than about 1 x 10 16 cm 3;forming an n-type channel layer coupled to the GaN-based drift layer; forming an n-contact layer coupled to the GaN-based drift layer and substantially parallel to the surface; forming a second electrical contact electrically coupled to the n-contact layer; forming a p-type gate region electrically coupled to the n-type channel layer; and forming a third electrical contact electrically coupled to the p-type gate region.
The method of claim 11, wherein a concentration of indium in the n-type drift layer is between 1 x 10 15 cm⁻³ and 1 x 10 16 cm- 3.
The method of claim 11, wherein a thickness of the n-type drift layer is greater than 1 m.
The method of claim 11, wherein the n-type channel layer comprises a GaN layer.
The method of claim 11, wherein the n-type drift layer comprises an n-type GaN layer.
The method of claim 11, wherein the GaN-based drift layer is formed by metal a metal organic chemical vapor deposition (MOC V D) process.
The method of claim 11, wherein the GaN-based containing at least one of t ri -methyl indium (TMI), ethyldimethylindium (EDMI).
The method of claim 11, wherein the GaN-based containing hydrogen.
The method of claim 11, wherein the GaN-based than 1000 °C. Page 4 of 6 during the MOCVD process, a metalorganic drift layer is formed in an environment t ri -ethyl indium (TE I), and drift layer is formed in an environment drift layer is formed at a temperature greater
Layer stacks claimed or described, ordered top of device to substrate.
vertical junction field-effect transistor (vertical JFET)
Materials described outside the worked examples.
GaN-based substrate
GaN
p-type gate region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the dopant concentration for an n-type dopant is illustrated as a function of the breakdown voltage. For the dopant 20 concentration curve, the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
indium concentration in drift layer (upper bound) | 10000000000000000 | GaN |
carbon concentration in drift layer (upper bound) | 10000000000000000 |
Related documents with shared materials, methods, properties, or citations.
indium precursors (TMI, TEI, EDMI)
n-contact layer
FIG. 4 is a simplified schematic cross-section of vertical junction field effect transistor 10 (JFET) according to an embodiment of the present invention. The …
indium concentration range in drift layer | 1000000000000000–10000000000000000 | GaN |
Thickness | ≤ 10000000000000000 cm | — |
Thickness | ≤ 1 cm | — |
Thickness | ≥ 10000000000000000 cm | — |
Temperature | ≥ 1 °C | — |
indium precursors (TMI, TEI, EDMI)
n-contact layer
FIG. 4 is a simplified schematic cross-section of vertical junction field effect transistor 10 (JFET) according to an embodiment of the present invention. The …
indium concentration range in drift layer | 1000000000000000–10000000000000000 | GaN |
Thickness | ≤ 10000000000000000 cm | — |
Thickness | ≤ 1 cm | — |
Thickness | ≥ 10000000000000000 cm | — |
Temperature | ≥ 1 °C | — |
indium precursors (TMI, TEI, EDMI)
n-contact layer
FIG. 4 is a simplified schematic cross-section of vertical junction field effect transistor 10 (JFET) according to an embodiment of the present invention. The …
indium concentration range in drift layer | 1000000000000000–10000000000000000 | GaN |
Thickness | ≤ 10000000000000000 cm | — |
Thickness | ≤ 1 cm | — |
Thickness | ≥ 10000000000000000 cm | — |
Temperature | ≥ 1 °C | — |
indium precursors (TMI, TEI, EDMI)
n-contact layer
FIG. 4 is a simplified schematic cross-section of vertical junction field effect transistor 10 (JFET) according to an embodiment of the present invention. The …
indium concentration range in drift layer | 1000000000000000–10000000000000000 | GaN |
Thickness | ≤ 10000000000000000 cm | — |
Thickness | ≤ 1 cm | — |
Thickness | ≥ 10000000000000000 cm | — |
Temperature | ≥ 1 °C | — |