Patent
Atlas literature
Patent
US 12,396,295 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B schematically illustrate examples of InxGa₁-xN/GaN semibulk (SB) microstructures with conven- tional and increasing GaN interlayer thicknesses, …
FIG. 2 illustrates examples of photoluminescence (PL) emissions for three samples (A, B and C) of InxGa₁-xN/GaN SB microstructures, in accordance with various …
FIGS. 3A-3D illustrates examples of surface morphology of samples A and B showing the effect of increasing the GaN interlayer thickness, in accordance with …
FIG. 4 illustrates examples of high-resolution x-ray dif- 60 fraction (HRXRD) rocking curves of sample B, in accor- dance with various embodiments of the …
FIG. 5 is a table illustrating examples of InGaN reflection and dislocation density, in accordance with various embodi- ments of the present disclosure. 65
FIGS. 6A-6E illustrate examples of atomic force micros- copy (AFM) image height retrace of sample C before and B₂ after silane treatments, in accordance with …
FIG. 7 is a table illustrating an example of silane treat- ment results, in accordance with various embodiments of the present disclosure.
FIGS. 8A-8C illustrate examples of SIMS data for three fabricated SB templates, with several growth temperature approaches, in accordance with various …
FIG. 9 illustrates an example of a p-type device quality InGaN relaxed template, in accordance with various embodiments of the present disclosure.
FIG. 10 illustrates an example of a QW lattice matched to n and p-type InGaN templates to eliminate Droop, in accor- dance with various embodiments of the …
FIG. 11 illustrates an example of an LED for red emission, in accordance with various embodiments of the present disclosure.
FIG. 12 illustrates an example of strain layer superlattice (SLS) structures between SB microstructures, in accordance with various embodiments of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device structure, comprising: a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, wherein the layer of InGaN comprises p-InGaN or n-InGaN.
The device structure of claim 1, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each of the first group of stacked periods has a GaN interlayer thickness substan-tially equal to the thickness of the GaN interlayer of the bottom layer.
The device structure of claim 1, wherein the GaN layer is a GaN blocking layer.
A device structure, comprising: a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, where the layer of InGaN comprises InxGa₁-xN, wherein InN of the layer of InGaN is about 15% or greater.
The device structure of claim 9, wherein the InN is in a range from about 15% to about 25%.
A device structure, comprising; a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, wherein the GaN layer is a GaN blocking layer comprising p-GaN and the layer of InGaN comprises p-InGaN or the GaN blocking layer comprises n-GaN and the layer of InGaN comprises n-InGaN.
The device structure of claim 11, wherein the GaN layer is a GaN prelayer disposed on a sapphire substrate.
A device structure, comprising: a GaN layer: a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer; and a strain layer superlattice (SLS) structure disposed between a first plurality of stacked periods of the SB template on the GaN layer and a second plurality of stacked periods of the SB template disposed on the SLS structure.
The device structure of claim 13, wherein the layer of InGaN comprises InxGa₁-xN.
The device structure of claim 13, wherein a light emitting diode (LED) comprises the device structure.
The device structure of claim 13, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each of the first group of stacked periods has a GaN interlayer thickness substan-tially equal to the thickness of the GaN interlayer of the bottom layer.
A method, comprising: forming a GaN layer; and forming a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period comprising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a bottom period of the plurality of stacked periods is formed at a first temperature and a second period of the plurality of B₂ stacked periods is formed at a second temperature less than the first temperature, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer.
The method of claim 18, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each period of the first group of stacked periods is formed at the first temperature.
The method of claim 18, wherein individual periods of the plurality of stacked periods are formed at temperatures that are reduced in a gradual or step-wise fashion. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials1 process step
Conventional semibulk (SB) sample grown on 300 µm n-type GaN on sapphire substrates via MOCVD. Structure consists of 18 nm InxGa₁-xN layers with fixed ~2 nm GaN interlayers throughout all periods. Growth temperature targets indium content x~0.085. PL emission observed at ~411 nm.
3 materials1 process step
Modified SB sample grown on 300 µm n-type GaN on sapphire via MOCVD. For the first 15 periods, GaN interlayer target thickness ~2 nm; then GaN interlayer thickness gradually increases every 3 periods until 30 periods reached; final GaN interlayer thickness in last 3 periods ~3.5 nm. Growth temperature same as Sample A, targeting indium content x~0.085. HRXRD rocking curves of symmetric (00.2) and asymmetric (10.5) reflections collected using Rigaku SmartLab diffractometer.
4 materials2 process steps
Modified SB sample with same interlayer graduation as Sample B, grown at higher temperature targeting x~0.07. Used for etch pit density (EPD) measurement. Capped with 10 nm GaN layer grown at 1025°C, then silane etching performed at 860°C with H₂ and 20 ppm SiH₄ at 5 sccm for 15 min. AFM used to measure EPD.
Layer stacks claimed or described, ordered top of device to substrate.
InGaN/GaN semibulk (SB) relaxed template device structure
InGaN/GaN SB template with intermediate SLS structure
Materials described outside the worked examples.
p-InGaN or n-InGaN
sapphire substrate
Al₂O₃
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates examples of photoluminescence (PL) emissions for three samples (A, B and C) of InxGa₁-xN/GaN SB microstructures, in accordance with various …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
PL Peak | 411 nm | InxGa₁-xN |
PL Peak |
Patents and literature cited by this patent (applicant and examiner references).
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US 12,396,295 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B schematically illustrate examples of InxGa₁-xN/GaN semibulk (SB) microstructures with conven- tional and increasing GaN interlayer thicknesses, …
FIG. 2 illustrates examples of photoluminescence (PL) emissions for three samples (A, B and C) of InxGa₁-xN/GaN SB microstructures, in accordance with various …
FIGS. 3A-3D illustrates examples of surface morphology of samples A and B showing the effect of increasing the GaN interlayer thickness, in accordance with …
FIG. 4 illustrates examples of high-resolution x-ray dif- 60 fraction (HRXRD) rocking curves of sample B, in accor- dance with various embodiments of the …
FIG. 5 is a table illustrating examples of InGaN reflection and dislocation density, in accordance with various embodi- ments of the present disclosure. 65
FIGS. 6A-6E illustrate examples of atomic force micros- copy (AFM) image height retrace of sample C before and B₂ after silane treatments, in accordance with …
FIG. 7 is a table illustrating an example of silane treat- ment results, in accordance with various embodiments of the present disclosure.
FIGS. 8A-8C illustrate examples of SIMS data for three fabricated SB templates, with several growth temperature approaches, in accordance with various …
FIG. 9 illustrates an example of a p-type device quality InGaN relaxed template, in accordance with various embodiments of the present disclosure.
FIG. 10 illustrates an example of a QW lattice matched to n and p-type InGaN templates to eliminate Droop, in accor- dance with various embodiments of the …
FIG. 11 illustrates an example of an LED for red emission, in accordance with various embodiments of the present disclosure.
FIG. 12 illustrates an example of strain layer superlattice (SLS) structures between SB microstructures, in accordance with various embodiments of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device structure, comprising: a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, wherein the layer of InGaN comprises p-InGaN or n-InGaN.
The device structure of claim 1, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each of the first group of stacked periods has a GaN interlayer thickness substan-tially equal to the thickness of the GaN interlayer of the bottom layer.
The device structure of claim 1, wherein the GaN layer is a GaN blocking layer.
A device structure, comprising: a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, where the layer of InGaN comprises InxGa₁-xN, wherein InN of the layer of InGaN is about 15% or greater.
The device structure of claim 9, wherein the InN is in a range from about 15% to about 25%.
A device structure, comprising; a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, wherein the GaN layer is a GaN blocking layer comprising p-GaN and the layer of InGaN comprises p-InGaN or the GaN blocking layer comprises n-GaN and the layer of InGaN comprises n-InGaN.
The device structure of claim 11, wherein the GaN layer is a GaN prelayer disposed on a sapphire substrate.
A device structure, comprising: a GaN layer: a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer; and a strain layer superlattice (SLS) structure disposed between a first plurality of stacked periods of the SB template on the GaN layer and a second plurality of stacked periods of the SB template disposed on the SLS structure.
The device structure of claim 13, wherein the layer of InGaN comprises InxGa₁-xN.
The device structure of claim 13, wherein a light emitting diode (LED) comprises the device structure.
The device structure of claim 13, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each of the first group of stacked periods has a GaN interlayer thickness substan-tially equal to the thickness of the GaN interlayer of the bottom layer.
A method, comprising: forming a GaN layer; and forming a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period comprising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a bottom period of the plurality of stacked periods is formed at a first temperature and a second period of the plurality of B₂ stacked periods is formed at a second temperature less than the first temperature, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer.
The method of claim 18, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each period of the first group of stacked periods is formed at the first temperature.
The method of claim 18, wherein individual periods of the plurality of stacked periods are formed at temperatures that are reduced in a gradual or step-wise fashion. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials1 process step
Conventional semibulk (SB) sample grown on 300 µm n-type GaN on sapphire substrates via MOCVD. Structure consists of 18 nm InxGa₁-xN layers with fixed ~2 nm GaN interlayers throughout all periods. Growth temperature targets indium content x~0.085. PL emission observed at ~411 nm.
3 materials1 process step
Modified SB sample grown on 300 µm n-type GaN on sapphire via MOCVD. For the first 15 periods, GaN interlayer target thickness ~2 nm; then GaN interlayer thickness gradually increases every 3 periods until 30 periods reached; final GaN interlayer thickness in last 3 periods ~3.5 nm. Growth temperature same as Sample A, targeting indium content x~0.085. HRXRD rocking curves of symmetric (00.2) and asymmetric (10.5) reflections collected using Rigaku SmartLab diffractometer.
4 materials2 process steps
Modified SB sample with same interlayer graduation as Sample B, grown at higher temperature targeting x~0.07. Used for etch pit density (EPD) measurement. Capped with 10 nm GaN layer grown at 1025°C, then silane etching performed at 860°C with H₂ and 20 ppm SiH₄ at 5 sccm for 15 min. AFM used to measure EPD.
Layer stacks claimed or described, ordered top of device to substrate.
InGaN/GaN semibulk (SB) relaxed template device structure
InGaN/GaN SB template with intermediate SLS structure
Materials described outside the worked examples.
p-InGaN or n-InGaN
sapphire substrate
Al₂O₃
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates examples of photoluminescence (PL) emissions for three samples (A, B and C) of InxGa₁-xN/GaN SB microstructures, in accordance with various …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
PL Peak | 411 nm | InxGa₁-xN |
PL Peak |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,396,295 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B schematically illustrate examples of InxGa₁-xN/GaN semibulk (SB) microstructures with conven- tional and increasing GaN interlayer thicknesses, …
FIG. 2 illustrates examples of photoluminescence (PL) emissions for three samples (A, B and C) of InxGa₁-xN/GaN SB microstructures, in accordance with various …
FIGS. 3A-3D illustrates examples of surface morphology of samples A and B showing the effect of increasing the GaN interlayer thickness, in accordance with …
FIG. 4 illustrates examples of high-resolution x-ray dif- 60 fraction (HRXRD) rocking curves of sample B, in accor- dance with various embodiments of the …
FIG. 5 is a table illustrating examples of InGaN reflection and dislocation density, in accordance with various embodi- ments of the present disclosure. 65
FIGS. 6A-6E illustrate examples of atomic force micros- copy (AFM) image height retrace of sample C before and B₂ after silane treatments, in accordance with …
FIG. 7 is a table illustrating an example of silane treat- ment results, in accordance with various embodiments of the present disclosure.
FIGS. 8A-8C illustrate examples of SIMS data for three fabricated SB templates, with several growth temperature approaches, in accordance with various …
FIG. 9 illustrates an example of a p-type device quality InGaN relaxed template, in accordance with various embodiments of the present disclosure.
FIG. 10 illustrates an example of a QW lattice matched to n and p-type InGaN templates to eliminate Droop, in accor- dance with various embodiments of the …
FIG. 11 illustrates an example of an LED for red emission, in accordance with various embodiments of the present disclosure.
FIG. 12 illustrates an example of strain layer superlattice (SLS) structures between SB microstructures, in accordance with various embodiments of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device structure, comprising: a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, wherein the layer of InGaN comprises p-InGaN or n-InGaN.
The device structure of claim 1, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each of the first group of stacked periods has a GaN interlayer thickness substan-tially equal to the thickness of the GaN interlayer of the bottom layer.
The device structure of claim 1, wherein the GaN layer is a GaN blocking layer.
A device structure, comprising: a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, where the layer of InGaN comprises InxGa₁-xN, wherein InN of the layer of InGaN is about 15% or greater.
The device structure of claim 9, wherein the InN is in a range from about 15% to about 25%.
A device structure, comprising; a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, wherein the GaN layer is a GaN blocking layer comprising p-GaN and the layer of InGaN comprises p-InGaN or the GaN blocking layer comprises n-GaN and the layer of InGaN comprises n-InGaN.
The device structure of claim 11, wherein the GaN layer is a GaN prelayer disposed on a sapphire substrate.
A device structure, comprising: a GaN layer: a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer; and a strain layer superlattice (SLS) structure disposed between a first plurality of stacked periods of the SB template on the GaN layer and a second plurality of stacked periods of the SB template disposed on the SLS structure.
The device structure of claim 13, wherein the layer of InGaN comprises InxGa₁-xN.
The device structure of claim 13, wherein a light emitting diode (LED) comprises the device structure.
The device structure of claim 13, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each of the first group of stacked periods has a GaN interlayer thickness substan-tially equal to the thickness of the GaN interlayer of the bottom layer.
A method, comprising: forming a GaN layer; and forming a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period comprising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a bottom period of the plurality of stacked periods is formed at a first temperature and a second period of the plurality of B₂ stacked periods is formed at a second temperature less than the first temperature, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer.
The method of claim 18, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each period of the first group of stacked periods is formed at the first temperature.
The method of claim 18, wherein individual periods of the plurality of stacked periods are formed at temperatures that are reduced in a gradual or step-wise fashion. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials1 process step
Conventional semibulk (SB) sample grown on 300 µm n-type GaN on sapphire substrates via MOCVD. Structure consists of 18 nm InxGa₁-xN layers with fixed ~2 nm GaN interlayers throughout all periods. Growth temperature targets indium content x~0.085. PL emission observed at ~411 nm.
3 materials1 process step
Modified SB sample grown on 300 µm n-type GaN on sapphire via MOCVD. For the first 15 periods, GaN interlayer target thickness ~2 nm; then GaN interlayer thickness gradually increases every 3 periods until 30 periods reached; final GaN interlayer thickness in last 3 periods ~3.5 nm. Growth temperature same as Sample A, targeting indium content x~0.085. HRXRD rocking curves of symmetric (00.2) and asymmetric (10.5) reflections collected using Rigaku SmartLab diffractometer.
4 materials2 process steps
Modified SB sample with same interlayer graduation as Sample B, grown at higher temperature targeting x~0.07. Used for etch pit density (EPD) measurement. Capped with 10 nm GaN layer grown at 1025°C, then silane etching performed at 860°C with H₂ and 20 ppm SiH₄ at 5 sccm for 15 min. AFM used to measure EPD.
Layer stacks claimed or described, ordered top of device to substrate.
InGaN/GaN semibulk (SB) relaxed template device structure
InGaN/GaN SB template with intermediate SLS structure
Materials described outside the worked examples.
p-InGaN or n-InGaN
sapphire substrate
Al₂O₃
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates examples of photoluminescence (PL) emissions for three samples (A, B and C) of InxGa₁-xN/GaN SB microstructures, in accordance with various …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
PL Peak | 411 nm | InxGa₁-xN |
PL Peak |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,396,295 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B schematically illustrate examples of InxGa₁-xN/GaN semibulk (SB) microstructures with conven- tional and increasing GaN interlayer thicknesses, …
FIG. 2 illustrates examples of photoluminescence (PL) emissions for three samples (A, B and C) of InxGa₁-xN/GaN SB microstructures, in accordance with various …
FIGS. 3A-3D illustrates examples of surface morphology of samples A and B showing the effect of increasing the GaN interlayer thickness, in accordance with …
FIG. 4 illustrates examples of high-resolution x-ray dif- 60 fraction (HRXRD) rocking curves of sample B, in accor- dance with various embodiments of the …
FIG. 5 is a table illustrating examples of InGaN reflection and dislocation density, in accordance with various embodi- ments of the present disclosure. 65
FIGS. 6A-6E illustrate examples of atomic force micros- copy (AFM) image height retrace of sample C before and B₂ after silane treatments, in accordance with …
FIG. 7 is a table illustrating an example of silane treat- ment results, in accordance with various embodiments of the present disclosure.
FIGS. 8A-8C illustrate examples of SIMS data for three fabricated SB templates, with several growth temperature approaches, in accordance with various …
FIG. 9 illustrates an example of a p-type device quality InGaN relaxed template, in accordance with various embodiments of the present disclosure.
FIG. 10 illustrates an example of a QW lattice matched to n and p-type InGaN templates to eliminate Droop, in accor- dance with various embodiments of the …
FIG. 11 illustrates an example of an LED for red emission, in accordance with various embodiments of the present disclosure.
FIG. 12 illustrates an example of strain layer superlattice (SLS) structures between SB microstructures, in accordance with various embodiments of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device structure, comprising: a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, wherein the layer of InGaN comprises p-InGaN or n-InGaN.
The device structure of claim 1, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each of the first group of stacked periods has a GaN interlayer thickness substan-tially equal to the thickness of the GaN interlayer of the bottom layer.
The device structure of claim 1, wherein the GaN layer is a GaN blocking layer.
A device structure, comprising: a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, where the layer of InGaN comprises InxGa₁-xN, wherein InN of the layer of InGaN is about 15% or greater.
The device structure of claim 9, wherein the InN is in a range from about 15% to about 25%.
A device structure, comprising; a GaN layer; and a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer, wherein the GaN layer is a GaN blocking layer comprising p-GaN and the layer of InGaN comprises p-InGaN or the GaN blocking layer comprises n-GaN and the layer of InGaN comprises n-InGaN.
The device structure of claim 11, wherein the GaN layer is a GaN prelayer disposed on a sapphire substrate.
A device structure, comprising: a GaN layer: a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period com-prising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer; and a strain layer superlattice (SLS) structure disposed between a first plurality of stacked periods of the SB template on the GaN layer and a second plurality of stacked periods of the SB template disposed on the SLS structure.
The device structure of claim 13, wherein the layer of InGaN comprises InxGa₁-xN.
The device structure of claim 13, wherein a light emitting diode (LED) comprises the device structure.
The device structure of claim 13, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each of the first group of stacked periods has a GaN interlayer thickness substan-tially equal to the thickness of the GaN interlayer of the bottom layer.
A method, comprising: forming a GaN layer; and forming a semibulk (SB) template comprising a plurality of stacked periods on the GaN layer, each period comprising a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a bottom period of the plurality of stacked periods is formed at a first temperature and a second period of the plurality of B₂ stacked periods is formed at a second temperature less than the first temperature, where a thickness of the GaN interlayer of a top period of the plurality of stacked periods is greater than a thickness of the GaN interlayer of a bottom period of the plurality of stacked periods, the bottom period disposed on the GaN layer.
The method of claim 18, wherein the plurality of stacked periods comprises a first group of stacked periods including the bottom period, wherein each period of the first group of stacked periods is formed at the first temperature.
The method of claim 18, wherein individual periods of the plurality of stacked periods are formed at temperatures that are reduced in a gradual or step-wise fashion. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials1 process step
Conventional semibulk (SB) sample grown on 300 µm n-type GaN on sapphire substrates via MOCVD. Structure consists of 18 nm InxGa₁-xN layers with fixed ~2 nm GaN interlayers throughout all periods. Growth temperature targets indium content x~0.085. PL emission observed at ~411 nm.
3 materials1 process step
Modified SB sample grown on 300 µm n-type GaN on sapphire via MOCVD. For the first 15 periods, GaN interlayer target thickness ~2 nm; then GaN interlayer thickness gradually increases every 3 periods until 30 periods reached; final GaN interlayer thickness in last 3 periods ~3.5 nm. Growth temperature same as Sample A, targeting indium content x~0.085. HRXRD rocking curves of symmetric (00.2) and asymmetric (10.5) reflections collected using Rigaku SmartLab diffractometer.
4 materials2 process steps
Modified SB sample with same interlayer graduation as Sample B, grown at higher temperature targeting x~0.07. Used for etch pit density (EPD) measurement. Capped with 10 nm GaN layer grown at 1025°C, then silane etching performed at 860°C with H₂ and 20 ppm SiH₄ at 5 sccm for 15 min. AFM used to measure EPD.
Layer stacks claimed or described, ordered top of device to substrate.
InGaN/GaN semibulk (SB) relaxed template device structure
InGaN/GaN SB template with intermediate SLS structure
Materials described outside the worked examples.
p-InGaN or n-InGaN
sapphire substrate
Al₂O₃
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates examples of photoluminescence (PL) emissions for three samples (A, B and C) of InxGa₁-xN/GaN SB microstructures, in accordance with various …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
PL Peak | 411 nm | InxGa₁-xN |
PL Peak |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
Light emitting diode (LED) with SB template and SLS
strain layer superlattice (SLS)
FIGS. 3A-3D illustrates examples of surface morphology of samples A and B showing the effect of increasing the GaN interlayer thickness, in accordance with …
FIGS. 6A-6E illustrate examples of atomic force micros- copy (AFM) image height retrace of sample C before and B₂ after silane treatments, in accordance with …
| 429 nm |
InxGa₁-xN |
PL Peak | 414 nm | InxGa₁-xN |
Thickness | 109–1010 cm | — |
Thickness | 1–2 nm | — |
Thickness | 10–15 nm | — |
Thickness | 4–5 nm | — |
Thickness | 7–10 nm | — |
Thickness | 3–4 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 10000000000 cm | — |
Thickness | ≥ 98 nm | — |
Light emitting diode (LED) with SB template and SLS
strain layer superlattice (SLS)
FIGS. 3A-3D illustrates examples of surface morphology of samples A and B showing the effect of increasing the GaN interlayer thickness, in accordance with …
FIGS. 6A-6E illustrate examples of atomic force micros- copy (AFM) image height retrace of sample C before and B₂ after silane treatments, in accordance with …
| 429 nm |
InxGa₁-xN |
PL Peak | 414 nm | InxGa₁-xN |
Thickness | 109–1010 cm | — |
Thickness | 1–2 nm | — |
Thickness | 10–15 nm | — |
Thickness | 4–5 nm | — |
Thickness | 7–10 nm | — |
Thickness | 3–4 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 10000000000 cm | — |
Thickness | ≥ 98 nm | — |
Light emitting diode (LED) with SB template and SLS
strain layer superlattice (SLS)
FIGS. 3A-3D illustrates examples of surface morphology of samples A and B showing the effect of increasing the GaN interlayer thickness, in accordance with …
FIGS. 6A-6E illustrate examples of atomic force micros- copy (AFM) image height retrace of sample C before and B₂ after silane treatments, in accordance with …
| 429 nm |
InxGa₁-xN |
PL Peak | 414 nm | InxGa₁-xN |
Thickness | 109–1010 cm | — |
Thickness | 1–2 nm | — |
Thickness | 10–15 nm | — |
Thickness | 4–5 nm | — |
Thickness | 7–10 nm | — |
Thickness | 3–4 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 10000000000 cm | — |
Thickness | ≥ 98 nm | — |
Light emitting diode (LED) with SB template and SLS
strain layer superlattice (SLS)
FIGS. 3A-3D illustrates examples of surface morphology of samples A and B showing the effect of increasing the GaN interlayer thickness, in accordance with …
FIGS. 6A-6E illustrate examples of atomic force micros- copy (AFM) image height retrace of sample C before and B₂ after silane treatments, in accordance with …
| 429 nm |
InxGa₁-xN |
PL Peak | 414 nm | InxGa₁-xN |
Thickness | 109–1010 cm | — |
Thickness | 1–2 nm | — |
Thickness | 10–15 nm | — |
Thickness | 4–5 nm | — |
Thickness | 7–10 nm | — |
Thickness | 3–4 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 10000000000 cm | — |
Thickness | ≥ 98 nm | — |
