Patent
US 11,527,573GaN-BASED THRESHOLD SWITCHING DEVICE AND MEMORY DIODE
Kai Fu
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
Patent
US 11,527,573Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 B and 1 C. In 102, a GaN substrate 120 is provided. In 104, an unintentionally doped (UID) GaN layer 122 (also referred to interchangeably as an …
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 4C.
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a switching device, the method compr ising: depositing a fi rst unintentionally doped GaN layer on a first surface of a GaN substrate; depositing a n ' -GaN layer on the first unintentionally doped GaN layer; etching away a portion of the n--GaN layer and a portion of the fi rst unintentionally doped GaN layer to yield a first etched surface and a second etched surface on the first unintentionally doped GaN layer; regrowing a second unintentionally doped GaN layer on the first etched surface and the second etched surface of the first unintentionally doped GaN layer; regrowing a p-GaN layer on the second unintentionally doped GaN layer; etching away a portion of the p-GaN layer and the second unintentionally doped GaN layer to yield an etched surface on the n + -GaN layer; forming a fi rst electrode on the etched surface of the n + -GaN layer; forming a second electrode on the p-GaN layer; and forming a third electrode on a second surface of the GaN substrate. Original
The method of claim 1, wherein a lateral p-n junction is de fi ned between the first electrode and the second electrode. Original
The method of claim 1, wherein a vertical p-n junction is de fi ned between the second electrode and the third electrode. Original
The method of claim 1, wherein etching away the portion of the n-GaN layer and the portion of the fi rst unintentionally doped GaN layer comprises forming a mesa pattern. Original
The method of claim 1, wherein regrowing the second unintentionally doped GaN layer further comprises regrowing the second unintentionally doped GaN layer on a first etched surface and a second etched surface of the n + -GaN layer. Original
A method for fabricating a switching device, the method comprising: depositing a first unintentionally doped GaN layer on a first surface of a GaN substrate; etching away a portion of the first unintentionally doped GaN layer to yield an etched surface on the first unintentionally doped GaN layer; regrowing a second unintentionally doped GaN layer on the etched surface of the first unintentionally doped GaN layer; regrowing a p-GaN layer on the second unintentionally doped GaN layer; forming a first electrode on the p-GaN layer; and forming a second electrode on a second surface of the GaN substrate. Original
The method of claim 8, wherein a vertical p-n junction is defined between the first electrode and the second electrode. Original
The method of claim 8, wherein etching away the portion of the first unintentionally doped GaN layer comprises forming a mesa pattern. Original
11-20. Canceled
Canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
Homoepitaxial growth and fabrication of GaN-based threshold switching devices (Device A and Device B) using MOCVD on c-plane n-GaN free-standing substrates. An ~7 µm thick UID-GaN layer and ~1 µm thick n+-GaN layer were grown, followed by ICP mesa etching, regrowth of 300 nm UID-GaN and 1 µm p-GaN layers, ICP ohmic contact formation, and electron-beam evaporation of metal stack electrodes.
Layer stacks claimed or described, ordered top of device to substrate.
Device A – GaN-based threshold switching diode with lateral and vertical p-n junctions
Materials described outside the worked examples.
Ti/Al/Ni/Au metal stack electrode
Pd/Ni/Au metal stack electrode
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
switching endurance cycles | >1000 cycles | — |
memory reset voltage threshold | ~4.4 V | — |
set voltage temperature dependence – saturation temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,527,573Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 B and 1 C. In 102, a GaN substrate 120 is provided. In 104, an unintentionally doped (UID) GaN layer 122 (also referred to interchangeably as an …
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 4C.
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a switching device, the method compr ising: depositing a fi rst unintentionally doped GaN layer on a first surface of a GaN substrate; depositing a n ' -GaN layer on the first unintentionally doped GaN layer; etching away a portion of the n--GaN layer and a portion of the fi rst unintentionally doped GaN layer to yield a first etched surface and a second etched surface on the first unintentionally doped GaN layer; regrowing a second unintentionally doped GaN layer on the first etched surface and the second etched surface of the first unintentionally doped GaN layer; regrowing a p-GaN layer on the second unintentionally doped GaN layer; etching away a portion of the p-GaN layer and the second unintentionally doped GaN layer to yield an etched surface on the n + -GaN layer; forming a fi rst electrode on the etched surface of the n + -GaN layer; forming a second electrode on the p-GaN layer; and forming a third electrode on a second surface of the GaN substrate. Original
The method of claim 1, wherein a lateral p-n junction is de fi ned between the first electrode and the second electrode. Original
The method of claim 1, wherein a vertical p-n junction is de fi ned between the second electrode and the third electrode. Original
The method of claim 1, wherein etching away the portion of the n-GaN layer and the portion of the fi rst unintentionally doped GaN layer comprises forming a mesa pattern. Original
The method of claim 1, wherein regrowing the second unintentionally doped GaN layer further comprises regrowing the second unintentionally doped GaN layer on a first etched surface and a second etched surface of the n + -GaN layer. Original
A method for fabricating a switching device, the method comprising: depositing a first unintentionally doped GaN layer on a first surface of a GaN substrate; etching away a portion of the first unintentionally doped GaN layer to yield an etched surface on the first unintentionally doped GaN layer; regrowing a second unintentionally doped GaN layer on the etched surface of the first unintentionally doped GaN layer; regrowing a p-GaN layer on the second unintentionally doped GaN layer; forming a first electrode on the p-GaN layer; and forming a second electrode on a second surface of the GaN substrate. Original
The method of claim 8, wherein a vertical p-n junction is defined between the first electrode and the second electrode. Original
The method of claim 8, wherein etching away the portion of the first unintentionally doped GaN layer comprises forming a mesa pattern. Original
11-20. Canceled
Canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
Homoepitaxial growth and fabrication of GaN-based threshold switching devices (Device A and Device B) using MOCVD on c-plane n-GaN free-standing substrates. An ~7 µm thick UID-GaN layer and ~1 µm thick n+-GaN layer were grown, followed by ICP mesa etching, regrowth of 300 nm UID-GaN and 1 µm p-GaN layers, ICP ohmic contact formation, and electron-beam evaporation of metal stack electrodes.
Layer stacks claimed or described, ordered top of device to substrate.
Device A – GaN-based threshold switching diode with lateral and vertical p-n junctions
Materials described outside the worked examples.
Ti/Al/Ni/Au metal stack electrode
Pd/Ni/Au metal stack electrode
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
switching endurance cycles | >1000 cycles | — |
memory reset voltage threshold | ~4.4 V | — |
set voltage temperature dependence – saturation temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,527,573Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 B and 1 C. In 102, a GaN substrate 120 is provided. In 104, an unintentionally doped (UID) GaN layer 122 (also referred to interchangeably as an …
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 4C.
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a switching device, the method compr ising: depositing a fi rst unintentionally doped GaN layer on a first surface of a GaN substrate; depositing a n ' -GaN layer on the first unintentionally doped GaN layer; etching away a portion of the n--GaN layer and a portion of the fi rst unintentionally doped GaN layer to yield a first etched surface and a second etched surface on the first unintentionally doped GaN layer; regrowing a second unintentionally doped GaN layer on the first etched surface and the second etched surface of the first unintentionally doped GaN layer; regrowing a p-GaN layer on the second unintentionally doped GaN layer; etching away a portion of the p-GaN layer and the second unintentionally doped GaN layer to yield an etched surface on the n + -GaN layer; forming a fi rst electrode on the etched surface of the n + -GaN layer; forming a second electrode on the p-GaN layer; and forming a third electrode on a second surface of the GaN substrate. Original
The method of claim 1, wherein a lateral p-n junction is de fi ned between the first electrode and the second electrode. Original
The method of claim 1, wherein a vertical p-n junction is de fi ned between the second electrode and the third electrode. Original
The method of claim 1, wherein etching away the portion of the n-GaN layer and the portion of the fi rst unintentionally doped GaN layer comprises forming a mesa pattern. Original
The method of claim 1, wherein regrowing the second unintentionally doped GaN layer further comprises regrowing the second unintentionally doped GaN layer on a first etched surface and a second etched surface of the n + -GaN layer. Original
A method for fabricating a switching device, the method comprising: depositing a first unintentionally doped GaN layer on a first surface of a GaN substrate; etching away a portion of the first unintentionally doped GaN layer to yield an etched surface on the first unintentionally doped GaN layer; regrowing a second unintentionally doped GaN layer on the etched surface of the first unintentionally doped GaN layer; regrowing a p-GaN layer on the second unintentionally doped GaN layer; forming a first electrode on the p-GaN layer; and forming a second electrode on a second surface of the GaN substrate. Original
The method of claim 8, wherein a vertical p-n junction is defined between the first electrode and the second electrode. Original
The method of claim 8, wherein etching away the portion of the first unintentionally doped GaN layer comprises forming a mesa pattern. Original
11-20. Canceled
Canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
Homoepitaxial growth and fabrication of GaN-based threshold switching devices (Device A and Device B) using MOCVD on c-plane n-GaN free-standing substrates. An ~7 µm thick UID-GaN layer and ~1 µm thick n+-GaN layer were grown, followed by ICP mesa etching, regrowth of 300 nm UID-GaN and 1 µm p-GaN layers, ICP ohmic contact formation, and electron-beam evaporation of metal stack electrodes.
Layer stacks claimed or described, ordered top of device to substrate.
Device A – GaN-based threshold switching diode with lateral and vertical p-n junctions
Materials described outside the worked examples.
Ti/Al/Ni/Au metal stack electrode
Pd/Ni/Au metal stack electrode
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
switching endurance cycles | >1000 cycles | — |
memory reset voltage threshold | ~4.4 V | — |
set voltage temperature dependence – saturation temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,527,573Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 B and 1 C. In 102, a GaN substrate 120 is provided. In 104, an unintentionally doped (UID) GaN layer 122 (also referred to interchangeably as an …
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 4C.
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a switching device, the method compr ising: depositing a fi rst unintentionally doped GaN layer on a first surface of a GaN substrate; depositing a n ' -GaN layer on the first unintentionally doped GaN layer; etching away a portion of the n--GaN layer and a portion of the fi rst unintentionally doped GaN layer to yield a first etched surface and a second etched surface on the first unintentionally doped GaN layer; regrowing a second unintentionally doped GaN layer on the first etched surface and the second etched surface of the first unintentionally doped GaN layer; regrowing a p-GaN layer on the second unintentionally doped GaN layer; etching away a portion of the p-GaN layer and the second unintentionally doped GaN layer to yield an etched surface on the n + -GaN layer; forming a fi rst electrode on the etched surface of the n + -GaN layer; forming a second electrode on the p-GaN layer; and forming a third electrode on a second surface of the GaN substrate. Original
The method of claim 1, wherein a lateral p-n junction is de fi ned between the first electrode and the second electrode. Original
The method of claim 1, wherein a vertical p-n junction is de fi ned between the second electrode and the third electrode. Original
The method of claim 1, wherein etching away the portion of the n-GaN layer and the portion of the fi rst unintentionally doped GaN layer comprises forming a mesa pattern. Original
The method of claim 1, wherein regrowing the second unintentionally doped GaN layer further comprises regrowing the second unintentionally doped GaN layer on a first etched surface and a second etched surface of the n + -GaN layer. Original
A method for fabricating a switching device, the method comprising: depositing a first unintentionally doped GaN layer on a first surface of a GaN substrate; etching away a portion of the first unintentionally doped GaN layer to yield an etched surface on the first unintentionally doped GaN layer; regrowing a second unintentionally doped GaN layer on the etched surface of the first unintentionally doped GaN layer; regrowing a p-GaN layer on the second unintentionally doped GaN layer; forming a first electrode on the p-GaN layer; and forming a second electrode on a second surface of the GaN substrate. Original
The method of claim 8, wherein a vertical p-n junction is defined between the first electrode and the second electrode. Original
The method of claim 8, wherein etching away the portion of the first unintentionally doped GaN layer comprises forming a mesa pattern. Original
11-20. Canceled
Canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
Homoepitaxial growth and fabrication of GaN-based threshold switching devices (Device A and Device B) using MOCVD on c-plane n-GaN free-standing substrates. An ~7 µm thick UID-GaN layer and ~1 µm thick n+-GaN layer were grown, followed by ICP mesa etching, regrowth of 300 nm UID-GaN and 1 µm p-GaN layers, ICP ohmic contact formation, and electron-beam evaporation of metal stack electrodes.
Layer stacks claimed or described, ordered top of device to substrate.
Device A – GaN-based threshold switching diode with lateral and vertical p-n junctions
Materials described outside the worked examples.
Ti/Al/Ni/Au metal stack electrode
Pd/Ni/Au metal stack electrode
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
switching endurance cycles | >1000 cycles | — |
memory reset voltage threshold | ~4.4 V | — |
set voltage temperature dependence – saturation temperature |
Related documents with shared materials, methods, properties, or citations.
Device B – GaN-based vertical p-n diode (no n+-GaN layer)
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
| ~200 °C |
| — |
UID-GaN background doping concentration | ~1e15 cm⁻³ | GaN |
GaN substrate carrier concentration | ~1e18 cm⁻³ | GaN |
Device B – GaN-based vertical p-n diode (no n+-GaN layer)
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
| ~200 °C |
| — |
UID-GaN background doping concentration | ~1e15 cm⁻³ | GaN |
GaN substrate carrier concentration | ~1e18 cm⁻³ | GaN |
Device B – GaN-based vertical p-n diode (no n+-GaN layer)
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
| ~200 °C |
| — |
UID-GaN background doping concentration | ~1e15 cm⁻³ | GaN |
GaN substrate carrier concentration | ~1e18 cm⁻³ | GaN |
Device B – GaN-based vertical p-n diode (no n+-GaN layer)
FIG. 2B shows a change (from curve 210 to curve 212) in the forward I-V characteristic for the lateral p-n junction of the same device. Both the reverse and …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 3A). The set voltage remained at this value at room temperature in the following high temperature test, where the initial high temperature cycle acted as …
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIG. 5 A. Here, the LRS I-V curves 500 are shown to follow the p-n diode characteristics, whereas the HRS I-V curves follow the space charge limited current …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
FIGS. 6A and 6B show I-V curves of a vertical diode in Device A with different scan voltages starting at 4.4 V and 6 V, respectively. Numbers indicate the scan …
| ~200 °C |
| — |
UID-GaN background doping concentration | ~1e15 cm⁻³ | GaN |
GaN substrate carrier concentration | ~1e18 cm⁻³ | GaN |