Patent
US 10,109,746GRAPHENE TRANSISTOR AND TERNARY LOGIC DEVICE USING THE SAME
Byoung Hun LEE
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,109,746Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is cr o ss-sectional view illustrating a graphene transistor according to a first embodiment of the present discl o sure. 20 Referring to
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 4 and 5 are graphs f o r comparing characteristics of the graphene transistors of
FIGS. 6 and 7 are graphs illustrating effects of the hydrogen annealing according 5 to the first embodiment of the present disclosure. Referring to FIG 6, a …
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIG. 9 is a characteristic graph for describing an operation o f the inverter o f
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
FIG. 25 8 according to the second embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a gate electrode having conductivity; a dielectric layer formed on the gate electrode; a graphene channel having a single-layer graphene formed on the dielectric layer; a source electrode and a drain electrode respectively formed at both end portions of the graphene channel based thereon and on the dielectric layer; a doping metal layer formed at a selected region of the graphene channel and configured to dope the graphene channel, which is below the doping metal layer, with a predetermined conductive type; and a passivation layer formed on the graphene channel and configured to shield the graphene channel and the doping metal layer, wherein the graphene channel includes: a doped graphene region disposed below the doping metal layer and having the predetermined conductive type; a first graphene region formed at one side of the doped graphene region and having a Fermi level different from that of the doped graphene region; and a second graphene region opposite to the first graphene region based on the doped graphene region and having a Fermi level different from that of the doped graphene region. Original
The graphene transistor of claim 1, wherein a work function of the doping metal layer is lower than a work function of graphene. Previously presented
The graphene transistor of claim 1, wherein a work function of the doping metal layer is higher than a work function of graphene. Previously presented
The graphene transistor of claim 1, wherein the graphene channel and the doping metal layer are annealed in hydrogen atmosphere. Original
The graphene transistor of claim 1, wherein the first graphene region and the second graphene region have the same Fermi level. Original
An inverter comprising: a first graphene transistor connected to a positive source voltage; and a second graphene transistor connected to a ground or a negative source voltage, wherein the first graphene transistor includes a first graphene channel and a first doping metal layer formed on the first graphene channel, wherein the second graphene transistor includes a second graphene channel and a second doping metal layer formed on the second graphene channel, wherein the first graphene channel and the second graphene channel include a doped graphene region, a first graphene region and a second graphene region, wherein the first graphene region formed at one side of the doped graphene region and having a Fermi level different from that of the doped graphene region, wherein the second graphene region opposite to the first graphene region based on the doped graphene region and having a Fermi level different from that of the doped graphene region, wherein gate terminals of the first graphene transistor and the second graphene transistor are commonly connected to an input signal, and wherein drain terminals of the first graphene transistor and the second graphene transistor are commonly connected to an output signal. Currently amended
The inverter of claim 12, wherein the first doping metal layer dopes a first doped graphene region, which is below the first doping metal layer, with an n-type, and includes Al or Ti. Original
The inverter of claim 12, wherein the second doping metal layer dopes a second doped graphene region, which is below the second doping metal layer, with a p-type, and includes Ni, Au, Pd, or Pt. Original
The inverter of claim 12, wherein the first graphene channel, the second graphene channel, the first doping metal layer, and the second doping metal layer are annealed in hydrogen atmosphere. Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor
graphene inverter
Materials described outside the worked examples.
single-layer graphene
C
doping metal layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is cr o ss-sectional view illustrating a graphene transistor according to a first embodiment of the present discl o sure. 20 Referring to
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
resistance maximum at first Dirac point (negative Vgs) in n-type doped graphene channel | — | C |
resistance maximum at second Dirac point (positive Vgs) in undoped graphene regions | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,109,746Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is cr o ss-sectional view illustrating a graphene transistor according to a first embodiment of the present discl o sure. 20 Referring to
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 4 and 5 are graphs f o r comparing characteristics of the graphene transistors of
FIGS. 6 and 7 are graphs illustrating effects of the hydrogen annealing according 5 to the first embodiment of the present disclosure. Referring to FIG 6, a …
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIG. 9 is a characteristic graph for describing an operation o f the inverter o f
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
FIG. 25 8 according to the second embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a gate electrode having conductivity; a dielectric layer formed on the gate electrode; a graphene channel having a single-layer graphene formed on the dielectric layer; a source electrode and a drain electrode respectively formed at both end portions of the graphene channel based thereon and on the dielectric layer; a doping metal layer formed at a selected region of the graphene channel and configured to dope the graphene channel, which is below the doping metal layer, with a predetermined conductive type; and a passivation layer formed on the graphene channel and configured to shield the graphene channel and the doping metal layer, wherein the graphene channel includes: a doped graphene region disposed below the doping metal layer and having the predetermined conductive type; a first graphene region formed at one side of the doped graphene region and having a Fermi level different from that of the doped graphene region; and a second graphene region opposite to the first graphene region based on the doped graphene region and having a Fermi level different from that of the doped graphene region. Original
The graphene transistor of claim 1, wherein a work function of the doping metal layer is lower than a work function of graphene. Previously presented
The graphene transistor of claim 1, wherein a work function of the doping metal layer is higher than a work function of graphene. Previously presented
The graphene transistor of claim 1, wherein the graphene channel and the doping metal layer are annealed in hydrogen atmosphere. Original
The graphene transistor of claim 1, wherein the first graphene region and the second graphene region have the same Fermi level. Original
An inverter comprising: a first graphene transistor connected to a positive source voltage; and a second graphene transistor connected to a ground or a negative source voltage, wherein the first graphene transistor includes a first graphene channel and a first doping metal layer formed on the first graphene channel, wherein the second graphene transistor includes a second graphene channel and a second doping metal layer formed on the second graphene channel, wherein the first graphene channel and the second graphene channel include a doped graphene region, a first graphene region and a second graphene region, wherein the first graphene region formed at one side of the doped graphene region and having a Fermi level different from that of the doped graphene region, wherein the second graphene region opposite to the first graphene region based on the doped graphene region and having a Fermi level different from that of the doped graphene region, wherein gate terminals of the first graphene transistor and the second graphene transistor are commonly connected to an input signal, and wherein drain terminals of the first graphene transistor and the second graphene transistor are commonly connected to an output signal. Currently amended
The inverter of claim 12, wherein the first doping metal layer dopes a first doped graphene region, which is below the first doping metal layer, with an n-type, and includes Al or Ti. Original
The inverter of claim 12, wherein the second doping metal layer dopes a second doped graphene region, which is below the second doping metal layer, with a p-type, and includes Ni, Au, Pd, or Pt. Original
The inverter of claim 12, wherein the first graphene channel, the second graphene channel, the first doping metal layer, and the second doping metal layer are annealed in hydrogen atmosphere. Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor
graphene inverter
Materials described outside the worked examples.
single-layer graphene
C
doping metal layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is cr o ss-sectional view illustrating a graphene transistor according to a first embodiment of the present discl o sure. 20 Referring to
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
resistance maximum at first Dirac point (negative Vgs) in n-type doped graphene channel | — | C |
resistance maximum at second Dirac point (positive Vgs) in undoped graphene regions | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,109,746Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is cr o ss-sectional view illustrating a graphene transistor according to a first embodiment of the present discl o sure. 20 Referring to
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 4 and 5 are graphs f o r comparing characteristics of the graphene transistors of
FIGS. 6 and 7 are graphs illustrating effects of the hydrogen annealing according 5 to the first embodiment of the present disclosure. Referring to FIG 6, a …
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIG. 9 is a characteristic graph for describing an operation o f the inverter o f
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
FIG. 25 8 according to the second embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a gate electrode having conductivity; a dielectric layer formed on the gate electrode; a graphene channel having a single-layer graphene formed on the dielectric layer; a source electrode and a drain electrode respectively formed at both end portions of the graphene channel based thereon and on the dielectric layer; a doping metal layer formed at a selected region of the graphene channel and configured to dope the graphene channel, which is below the doping metal layer, with a predetermined conductive type; and a passivation layer formed on the graphene channel and configured to shield the graphene channel and the doping metal layer, wherein the graphene channel includes: a doped graphene region disposed below the doping metal layer and having the predetermined conductive type; a first graphene region formed at one side of the doped graphene region and having a Fermi level different from that of the doped graphene region; and a second graphene region opposite to the first graphene region based on the doped graphene region and having a Fermi level different from that of the doped graphene region. Original
The graphene transistor of claim 1, wherein a work function of the doping metal layer is lower than a work function of graphene. Previously presented
The graphene transistor of claim 1, wherein a work function of the doping metal layer is higher than a work function of graphene. Previously presented
The graphene transistor of claim 1, wherein the graphene channel and the doping metal layer are annealed in hydrogen atmosphere. Original
The graphene transistor of claim 1, wherein the first graphene region and the second graphene region have the same Fermi level. Original
An inverter comprising: a first graphene transistor connected to a positive source voltage; and a second graphene transistor connected to a ground or a negative source voltage, wherein the first graphene transistor includes a first graphene channel and a first doping metal layer formed on the first graphene channel, wherein the second graphene transistor includes a second graphene channel and a second doping metal layer formed on the second graphene channel, wherein the first graphene channel and the second graphene channel include a doped graphene region, a first graphene region and a second graphene region, wherein the first graphene region formed at one side of the doped graphene region and having a Fermi level different from that of the doped graphene region, wherein the second graphene region opposite to the first graphene region based on the doped graphene region and having a Fermi level different from that of the doped graphene region, wherein gate terminals of the first graphene transistor and the second graphene transistor are commonly connected to an input signal, and wherein drain terminals of the first graphene transistor and the second graphene transistor are commonly connected to an output signal. Currently amended
The inverter of claim 12, wherein the first doping metal layer dopes a first doped graphene region, which is below the first doping metal layer, with an n-type, and includes Al or Ti. Original
The inverter of claim 12, wherein the second doping metal layer dopes a second doped graphene region, which is below the second doping metal layer, with a p-type, and includes Ni, Au, Pd, or Pt. Original
The inverter of claim 12, wherein the first graphene channel, the second graphene channel, the first doping metal layer, and the second doping metal layer are annealed in hydrogen atmosphere. Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor
graphene inverter
Materials described outside the worked examples.
single-layer graphene
C
doping metal layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is cr o ss-sectional view illustrating a graphene transistor according to a first embodiment of the present discl o sure. 20 Referring to
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
resistance maximum at first Dirac point (negative Vgs) in n-type doped graphene channel | — | C |
resistance maximum at second Dirac point (positive Vgs) in undoped graphene regions | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,109,746Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is cr o ss-sectional view illustrating a graphene transistor according to a first embodiment of the present discl o sure. 20 Referring to
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 4 and 5 are graphs f o r comparing characteristics of the graphene transistors of
FIGS. 6 and 7 are graphs illustrating effects of the hydrogen annealing according 5 to the first embodiment of the present disclosure. Referring to FIG 6, a …
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIG. 9 is a characteristic graph for describing an operation o f the inverter o f
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
FIG. 25 8 according to the second embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a gate electrode having conductivity; a dielectric layer formed on the gate electrode; a graphene channel having a single-layer graphene formed on the dielectric layer; a source electrode and a drain electrode respectively formed at both end portions of the graphene channel based thereon and on the dielectric layer; a doping metal layer formed at a selected region of the graphene channel and configured to dope the graphene channel, which is below the doping metal layer, with a predetermined conductive type; and a passivation layer formed on the graphene channel and configured to shield the graphene channel and the doping metal layer, wherein the graphene channel includes: a doped graphene region disposed below the doping metal layer and having the predetermined conductive type; a first graphene region formed at one side of the doped graphene region and having a Fermi level different from that of the doped graphene region; and a second graphene region opposite to the first graphene region based on the doped graphene region and having a Fermi level different from that of the doped graphene region. Original
The graphene transistor of claim 1, wherein a work function of the doping metal layer is lower than a work function of graphene. Previously presented
The graphene transistor of claim 1, wherein a work function of the doping metal layer is higher than a work function of graphene. Previously presented
The graphene transistor of claim 1, wherein the graphene channel and the doping metal layer are annealed in hydrogen atmosphere. Original
The graphene transistor of claim 1, wherein the first graphene region and the second graphene region have the same Fermi level. Original
An inverter comprising: a first graphene transistor connected to a positive source voltage; and a second graphene transistor connected to a ground or a negative source voltage, wherein the first graphene transistor includes a first graphene channel and a first doping metal layer formed on the first graphene channel, wherein the second graphene transistor includes a second graphene channel and a second doping metal layer formed on the second graphene channel, wherein the first graphene channel and the second graphene channel include a doped graphene region, a first graphene region and a second graphene region, wherein the first graphene region formed at one side of the doped graphene region and having a Fermi level different from that of the doped graphene region, wherein the second graphene region opposite to the first graphene region based on the doped graphene region and having a Fermi level different from that of the doped graphene region, wherein gate terminals of the first graphene transistor and the second graphene transistor are commonly connected to an input signal, and wherein drain terminals of the first graphene transistor and the second graphene transistor are commonly connected to an output signal. Currently amended
The inverter of claim 12, wherein the first doping metal layer dopes a first doped graphene region, which is below the first doping metal layer, with an n-type, and includes Al or Ti. Original
The inverter of claim 12, wherein the second doping metal layer dopes a second doped graphene region, which is below the second doping metal layer, with a p-type, and includes Ni, Au, Pd, or Pt. Original
The inverter of claim 12, wherein the first graphene channel, the second graphene channel, the first doping metal layer, and the second doping metal layer are annealed in hydrogen atmosphere. Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene transistor
graphene inverter
Materials described outside the worked examples.
single-layer graphene
C
doping metal layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is cr o ss-sectional view illustrating a graphene transistor according to a first embodiment of the present discl o sure. 20 Referring to
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
resistance maximum at first Dirac point (negative Vgs) in n-type doped graphene channel | — | C |
resistance maximum at second Dirac point (positive Vgs) in undoped graphene regions | — |
Related documents with shared materials, methods, properties, or citations.
passivation layer
aluminum
Al
titanium
Ti
nickel
Ni
gold
Au
palladium
Pd
platinum
Pt
silicon oxide
SiO₂
alumina
Al₂O₃
p++ heavily doped silicon substrate
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 4 and 5 are graphs f o r comparing characteristics of the graphene transistors of
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
C |
dielectric layer thickness | 90 nm | SiO₂ |
graphene channel length between source and drain | 9 um | C |
doping metal layer thickness | 10 nm | doping metal layer |
doping metal layer width | 2 um | doping metal layer |
first graphene region width | 3 um | C |
doped graphene region width | 2 um | C |
second graphene region length | 4 um | C |
Voltage | 30–30 V | — |
Voltage | 13–23 V | — |
Voltage | 35–40 V | — |
Voltage | 0.5–1.2 V | — |
Pressure | 20–30 atm | — |
Duration | 1–4 hours | — |
Pressure | ≤ 20 atm | — |
Voltage | ≤ 0.3 V | — |
Pressure | ≥ 30 atm | — |
passivation layer
aluminum
Al
titanium
Ti
nickel
Ni
gold
Au
palladium
Pd
platinum
Pt
silicon oxide
SiO₂
alumina
Al₂O₃
p++ heavily doped silicon substrate
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 4 and 5 are graphs f o r comparing characteristics of the graphene transistors of
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
C |
dielectric layer thickness | 90 nm | SiO₂ |
graphene channel length between source and drain | 9 um | C |
doping metal layer thickness | 10 nm | doping metal layer |
doping metal layer width | 2 um | doping metal layer |
first graphene region width | 3 um | C |
doped graphene region width | 2 um | C |
second graphene region length | 4 um | C |
Voltage | 30–30 V | — |
Voltage | 13–23 V | — |
Voltage | 35–40 V | — |
Voltage | 0.5–1.2 V | — |
Pressure | 20–30 atm | — |
Duration | 1–4 hours | — |
Pressure | ≤ 20 atm | — |
Voltage | ≤ 0.3 V | — |
Pressure | ≥ 30 atm | — |
passivation layer
aluminum
Al
titanium
Ti
nickel
Ni
gold
Au
palladium
Pd
platinum
Pt
silicon oxide
SiO₂
alumina
Al₂O₃
p++ heavily doped silicon substrate
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 4 and 5 are graphs f o r comparing characteristics of the graphene transistors of
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
C |
dielectric layer thickness | 90 nm | SiO₂ |
graphene channel length between source and drain | 9 um | C |
doping metal layer thickness | 10 nm | doping metal layer |
doping metal layer width | 2 um | doping metal layer |
first graphene region width | 3 um | C |
doped graphene region width | 2 um | C |
second graphene region length | 4 um | C |
Voltage | 30–30 V | — |
Voltage | 13–23 V | — |
Voltage | 35–40 V | — |
Voltage | 0.5–1.2 V | — |
Pressure | 20–30 atm | — |
Duration | 1–4 hours | — |
Pressure | ≤ 20 atm | — |
Voltage | ≤ 0.3 V | — |
Pressure | ≥ 30 atm | — |
passivation layer
aluminum
Al
titanium
Ti
nickel
Ni
gold
Au
palladium
Pd
platinum
Pt
silicon oxide
SiO₂
alumina
Al₂O₃
p++ heavily doped silicon substrate
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 2 and 3 according to the first embodiment of the present disclosure. 15 FI G 4 shows a graphene transistor which is formed under a condition the same as …
FIGS. 4 and 5 are graphs f o r comparing characteristics of the graphene transistors of
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIGS. 8 and 9, when the input signal V N is OV, Vgs of the first graphene transistor 201 becomes -2V, and Vgs of the second graphene transistor 202 becomes 2V. …
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
FIG. 10 is a graph illustrating input and output characteristics of the inverter of 15 FI G S. 8 and 9 according to the second embodiment o f the present …
C |
dielectric layer thickness | 90 nm | SiO₂ |
graphene channel length between source and drain | 9 um | C |
doping metal layer thickness | 10 nm | doping metal layer |
doping metal layer width | 2 um | doping metal layer |
first graphene region width | 3 um | C |
doped graphene region width | 2 um | C |
second graphene region length | 4 um | C |
Voltage | 30–30 V | — |
Voltage | 13–23 V | — |
Voltage | 35–40 V | — |
Voltage | 0.5–1.2 V | — |
Pressure | 20–30 atm | — |
Duration | 1–4 hours | — |
Pressure | ≤ 20 atm | — |
Voltage | ≤ 0.3 V | — |
Pressure | ≥ 30 atm | — |