Patent
US 10,079,313GRAPHENE ELECTRONIC DEVICE HAVING CHANNEL LAYER INCLUDING GRAPHENE ISLANDS AND METHOD OF FABRICATING THE SAME
Kiyoung LEE
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 10,079,313Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a graphene electronic device having a channel layer including graphene islands according to example embodiments; [0020]
FIG. 2 is a plan view of graphene islands according to example embodiments; [0021]
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
FIGS. 5A through 5D are cross-sectional views illustrating methods of fabricating a graphene electronic device according to example embodiments; [0024]
FIG. 6 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
FIG. 7 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
FIG. 8 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The graphene electronic device of c laim 20, wherein the gate electrode is a conductive substrate, the gate insulating layer is on the conductive substrate, the channel layer is on the gate insulating layer, and the source electrode is on the one end of the channel layer and the drain electrode is on the another end of the channel layer. Previously presented
The graphene electronic device of claim 1, wherein the semiconductor layer includes one of silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, and a Group III/V compound semiconductor. Original
The graphene electronic device of claim 1, wherein the plurality of graphene islands are spaced apart from each other by a gap of about 1 nm to about 100 nm. Original
The graphene electronic device of claim 1, wherein the plurality of graphene islands are between the gate insulating layer and the semiconductor layer. Original
(Withdrawn-Curren t ly Amended) The graphene electronic device of claim 20, comprising: a substrate, wherein the channel layer is on the substrate, the gate insulating layer is on the channel layer, the gate electrode is on the gate insulat in g layer, and the source electrode is on the one end of the channel layer and the drain electrode is on the another end of the channel layer. Currently amended
The graphene electronic device of claim 8, wherein the semiconductor layer includes one of silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, and a Group III/V compound semiconductor. Withdrawn
The graphene electronic device of claim 8, wherein the plurality of graphene islands are spaced apart from each other by a gap of about 1 nm to about 100 nm. Withdrawn
The graphene electronic device of claim 8, wherein the plurality of graphene islands are between the gate insulating layer and the semiconductor layer. Withdrawn
(Withdrawn-Previously Presented) A method of fabricating a graphene electronic device, the method comprising: forming a gate insulating layer on a conductive substrate; placing a graphene sheet on the gate insulating layer; coating a semiconductor precursor solution onto the graphene sheet to form a coated graphene sheet; heat-treating the substrate and the coated graphene ' sheet to form a graphene layer including a plurality of graphene islands; forming a semiconductor layer by oxidizing the semiconductor precursor solution; and forming a source electrode on one end of the semiconductor layer and the graphene layer and a drain electrode on another end of the semiconductor layer and the graphene layer. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the forming a semiconductor layer forms the semiconductor layer including InZnO. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the heat-treating is performed at about 400 * C to 500 *C. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the heat-treating forms the graphene layer including the plurality of graphene islands spaced apart from each other by a gap of about 1 nm to about 100 nm. Withdrawn
A graphene electronic device comprising: a channel layer including a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, the graphene layer including a plurality of graphene islands spaced apart from each other; a gate insulating layer connected to the channel layer such that the channel layer is on the gate insulating layer or the gate insulating layer is on the channel layer; a gate electrode connected to the gate insulating layer such that the gate insulating layer is between the channel layer and the gate electrode; and a source electrode connected to one end of the channel layer and a drain electrode connected another end of the channel layer. *** END CLAIM LISTING *** Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
bottom-gate graphene FET
top-gate graphene FET
Materials described outside the worked examples.
graphene islands
gate insulating layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
solution-type IZO FET mobility (background, prior art) | 1–15 cm2 V-1 s-1 | amorphous oxide semiconductor |
RF-sputtering IZO FET mobility (background, prior art) | 15–60 cm2 V-1 s-1 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,079,313Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a graphene electronic device having a channel layer including graphene islands according to example embodiments; [0020]
FIG. 2 is a plan view of graphene islands according to example embodiments; [0021]
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
FIGS. 5A through 5D are cross-sectional views illustrating methods of fabricating a graphene electronic device according to example embodiments; [0024]
FIG. 6 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
FIG. 7 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
FIG. 8 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The graphene electronic device of c laim 20, wherein the gate electrode is a conductive substrate, the gate insulating layer is on the conductive substrate, the channel layer is on the gate insulating layer, and the source electrode is on the one end of the channel layer and the drain electrode is on the another end of the channel layer. Previously presented
The graphene electronic device of claim 1, wherein the semiconductor layer includes one of silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, and a Group III/V compound semiconductor. Original
The graphene electronic device of claim 1, wherein the plurality of graphene islands are spaced apart from each other by a gap of about 1 nm to about 100 nm. Original
The graphene electronic device of claim 1, wherein the plurality of graphene islands are between the gate insulating layer and the semiconductor layer. Original
(Withdrawn-Curren t ly Amended) The graphene electronic device of claim 20, comprising: a substrate, wherein the channel layer is on the substrate, the gate insulating layer is on the channel layer, the gate electrode is on the gate insulat in g layer, and the source electrode is on the one end of the channel layer and the drain electrode is on the another end of the channel layer. Currently amended
The graphene electronic device of claim 8, wherein the semiconductor layer includes one of silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, and a Group III/V compound semiconductor. Withdrawn
The graphene electronic device of claim 8, wherein the plurality of graphene islands are spaced apart from each other by a gap of about 1 nm to about 100 nm. Withdrawn
The graphene electronic device of claim 8, wherein the plurality of graphene islands are between the gate insulating layer and the semiconductor layer. Withdrawn
(Withdrawn-Previously Presented) A method of fabricating a graphene electronic device, the method comprising: forming a gate insulating layer on a conductive substrate; placing a graphene sheet on the gate insulating layer; coating a semiconductor precursor solution onto the graphene sheet to form a coated graphene sheet; heat-treating the substrate and the coated graphene ' sheet to form a graphene layer including a plurality of graphene islands; forming a semiconductor layer by oxidizing the semiconductor precursor solution; and forming a source electrode on one end of the semiconductor layer and the graphene layer and a drain electrode on another end of the semiconductor layer and the graphene layer. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the forming a semiconductor layer forms the semiconductor layer including InZnO. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the heat-treating is performed at about 400 * C to 500 *C. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the heat-treating forms the graphene layer including the plurality of graphene islands spaced apart from each other by a gap of about 1 nm to about 100 nm. Withdrawn
A graphene electronic device comprising: a channel layer including a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, the graphene layer including a plurality of graphene islands spaced apart from each other; a gate insulating layer connected to the channel layer such that the channel layer is on the gate insulating layer or the gate insulating layer is on the channel layer; a gate electrode connected to the gate insulating layer such that the gate insulating layer is between the channel layer and the gate electrode; and a source electrode connected to one end of the channel layer and a drain electrode connected another end of the channel layer. *** END CLAIM LISTING *** Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
bottom-gate graphene FET
top-gate graphene FET
Materials described outside the worked examples.
graphene islands
gate insulating layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
solution-type IZO FET mobility (background, prior art) | 1–15 cm2 V-1 s-1 | amorphous oxide semiconductor |
RF-sputtering IZO FET mobility (background, prior art) | 15–60 cm2 V-1 s-1 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,079,313Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a graphene electronic device having a channel layer including graphene islands according to example embodiments; [0020]
FIG. 2 is a plan view of graphene islands according to example embodiments; [0021]
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
FIGS. 5A through 5D are cross-sectional views illustrating methods of fabricating a graphene electronic device according to example embodiments; [0024]
FIG. 6 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
FIG. 7 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
FIG. 8 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The graphene electronic device of c laim 20, wherein the gate electrode is a conductive substrate, the gate insulating layer is on the conductive substrate, the channel layer is on the gate insulating layer, and the source electrode is on the one end of the channel layer and the drain electrode is on the another end of the channel layer. Previously presented
The graphene electronic device of claim 1, wherein the semiconductor layer includes one of silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, and a Group III/V compound semiconductor. Original
The graphene electronic device of claim 1, wherein the plurality of graphene islands are spaced apart from each other by a gap of about 1 nm to about 100 nm. Original
The graphene electronic device of claim 1, wherein the plurality of graphene islands are between the gate insulating layer and the semiconductor layer. Original
(Withdrawn-Curren t ly Amended) The graphene electronic device of claim 20, comprising: a substrate, wherein the channel layer is on the substrate, the gate insulating layer is on the channel layer, the gate electrode is on the gate insulat in g layer, and the source electrode is on the one end of the channel layer and the drain electrode is on the another end of the channel layer. Currently amended
The graphene electronic device of claim 8, wherein the semiconductor layer includes one of silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, and a Group III/V compound semiconductor. Withdrawn
The graphene electronic device of claim 8, wherein the plurality of graphene islands are spaced apart from each other by a gap of about 1 nm to about 100 nm. Withdrawn
The graphene electronic device of claim 8, wherein the plurality of graphene islands are between the gate insulating layer and the semiconductor layer. Withdrawn
(Withdrawn-Previously Presented) A method of fabricating a graphene electronic device, the method comprising: forming a gate insulating layer on a conductive substrate; placing a graphene sheet on the gate insulating layer; coating a semiconductor precursor solution onto the graphene sheet to form a coated graphene sheet; heat-treating the substrate and the coated graphene ' sheet to form a graphene layer including a plurality of graphene islands; forming a semiconductor layer by oxidizing the semiconductor precursor solution; and forming a source electrode on one end of the semiconductor layer and the graphene layer and a drain electrode on another end of the semiconductor layer and the graphene layer. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the forming a semiconductor layer forms the semiconductor layer including InZnO. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the heat-treating is performed at about 400 * C to 500 *C. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the heat-treating forms the graphene layer including the plurality of graphene islands spaced apart from each other by a gap of about 1 nm to about 100 nm. Withdrawn
A graphene electronic device comprising: a channel layer including a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, the graphene layer including a plurality of graphene islands spaced apart from each other; a gate insulating layer connected to the channel layer such that the channel layer is on the gate insulating layer or the gate insulating layer is on the channel layer; a gate electrode connected to the gate insulating layer such that the gate insulating layer is between the channel layer and the gate electrode; and a source electrode connected to one end of the channel layer and a drain electrode connected another end of the channel layer. *** END CLAIM LISTING *** Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
bottom-gate graphene FET
top-gate graphene FET
Materials described outside the worked examples.
graphene islands
gate insulating layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
solution-type IZO FET mobility (background, prior art) | 1–15 cm2 V-1 s-1 | amorphous oxide semiconductor |
RF-sputtering IZO FET mobility (background, prior art) | 15–60 cm2 V-1 s-1 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,079,313Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a graphene electronic device having a channel layer including graphene islands according to example embodiments; [0020]
FIG. 2 is a plan view of graphene islands according to example embodiments; [0021]
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
FIGS. 5A through 5D are cross-sectional views illustrating methods of fabricating a graphene electronic device according to example embodiments; [0024]
FIG. 6 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
FIG. 7 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
FIG. 8 is a cross-sectional view illustrating a structure of a graphene electronic device having a channel layer including graphene islands according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The graphene electronic device of c laim 20, wherein the gate electrode is a conductive substrate, the gate insulating layer is on the conductive substrate, the channel layer is on the gate insulating layer, and the source electrode is on the one end of the channel layer and the drain electrode is on the another end of the channel layer. Previously presented
The graphene electronic device of claim 1, wherein the semiconductor layer includes one of silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, and a Group III/V compound semiconductor. Original
The graphene electronic device of claim 1, wherein the plurality of graphene islands are spaced apart from each other by a gap of about 1 nm to about 100 nm. Original
The graphene electronic device of claim 1, wherein the plurality of graphene islands are between the gate insulating layer and the semiconductor layer. Original
(Withdrawn-Curren t ly Amended) The graphene electronic device of claim 20, comprising: a substrate, wherein the channel layer is on the substrate, the gate insulating layer is on the channel layer, the gate electrode is on the gate insulat in g layer, and the source electrode is on the one end of the channel layer and the drain electrode is on the another end of the channel layer. Currently amended
The graphene electronic device of claim 8, wherein the semiconductor layer includes one of silicon, an organic semiconductor, an amorphous oxide semiconductor, a two-dimensional transition metal chalcogenide, and a Group III/V compound semiconductor. Withdrawn
The graphene electronic device of claim 8, wherein the plurality of graphene islands are spaced apart from each other by a gap of about 1 nm to about 100 nm. Withdrawn
The graphene electronic device of claim 8, wherein the plurality of graphene islands are between the gate insulating layer and the semiconductor layer. Withdrawn
(Withdrawn-Previously Presented) A method of fabricating a graphene electronic device, the method comprising: forming a gate insulating layer on a conductive substrate; placing a graphene sheet on the gate insulating layer; coating a semiconductor precursor solution onto the graphene sheet to form a coated graphene sheet; heat-treating the substrate and the coated graphene ' sheet to form a graphene layer including a plurality of graphene islands; forming a semiconductor layer by oxidizing the semiconductor precursor solution; and forming a source electrode on one end of the semiconductor layer and the graphene layer and a drain electrode on another end of the semiconductor layer and the graphene layer. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the forming a semiconductor layer forms the semiconductor layer including InZnO. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the heat-treating is performed at about 400 * C to 500 *C. Withdrawn
The method of fabricating a graphene electronic device of claim 15, wherein the heat-treating forms the graphene layer including the plurality of graphene islands spaced apart from each other by a gap of about 1 nm to about 100 nm. Withdrawn
A graphene electronic device comprising: a channel layer including a semiconductor layer and a graphene layer in direct contact with the semiconductor layer, the graphene layer including a plurality of graphene islands spaced apart from each other; a gate insulating layer connected to the channel layer such that the channel layer is on the gate insulating layer or the gate insulating layer is on the channel layer; a gate electrode connected to the gate insulating layer such that the gate insulating layer is between the channel layer and the gate electrode; and a source electrode connected to one end of the channel layer and a drain electrode connected another end of the channel layer. *** END CLAIM LISTING *** Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
bottom-gate graphene FET
top-gate graphene FET
Materials described outside the worked examples.
graphene islands
gate insulating layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
solution-type IZO FET mobility (background, prior art) | 1–15 cm2 V-1 s-1 | amorphous oxide semiconductor |
RF-sputtering IZO FET mobility (background, prior art) | 15–60 cm2 V-1 s-1 |
Related documents with shared materials, methods, properties, or citations.
silicon
Si
organic semiconductor
amorphous oxide semiconductor
two-dimensional transition metal chalcogenide
Group III/V compound semiconductor
InZnO
semiconductor precursor solution
silicon oxide
SiO₂
silicon nitride
Si₃N₄
polydimethylsiloxane
polyurethane
indium tin oxide
ITO
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
amorphous oxide semiconductor |
Thickness | 100–300 nm | — |
Thickness | 1–100 nm | — |
Thickness | 30–50 nm | — |
Thickness | 1–30 nm | — |
silicon
Si
organic semiconductor
amorphous oxide semiconductor
two-dimensional transition metal chalcogenide
Group III/V compound semiconductor
InZnO
semiconductor precursor solution
silicon oxide
SiO₂
silicon nitride
Si₃N₄
polydimethylsiloxane
polyurethane
indium tin oxide
ITO
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
amorphous oxide semiconductor |
Thickness | 100–300 nm | — |
Thickness | 1–100 nm | — |
Thickness | 30–50 nm | — |
Thickness | 1–30 nm | — |
silicon
Si
organic semiconductor
amorphous oxide semiconductor
two-dimensional transition metal chalcogenide
Group III/V compound semiconductor
InZnO
semiconductor precursor solution
silicon oxide
SiO₂
silicon nitride
Si₃N₄
polydimethylsiloxane
polyurethane
indium tin oxide
ITO
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
amorphous oxide semiconductor |
Thickness | 100–300 nm | — |
Thickness | 1–100 nm | — |
Thickness | 30–50 nm | — |
Thickness | 1–30 nm | — |
silicon
Si
organic semiconductor
amorphous oxide semiconductor
two-dimensional transition metal chalcogenide
Group III/V compound semiconductor
InZnO
semiconductor precursor solution
silicon oxide
SiO₂
silicon nitride
Si₃N₄
polydimethylsiloxane
polyurethane
indium tin oxide
ITO
FIG. 3 is a graph illustrating electrical characteristics of a graphene electronic device according to example embodiments; [0022]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
FIG. 4 is a graph illustrating electrical characteristics of a transistor having an IZO channel layer without a graphene layer; [0023]
amorphous oxide semiconductor |
Thickness | 100–300 nm | — |
Thickness | 1–100 nm | — |
Thickness | 30–50 nm | — |
Thickness | 1–30 nm | — |