Patent
US 9,252,704VOLTAGE TUNABLE OSCILLATOR USING BILAYER GRAPHENE AND A LEAD ZIRCONATE TITANATE CAPACITOR
Osama M. Nayfeh
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,252,704Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a circuit diagram illustrating a preferred embodiment of the present invention;
FIG. 2 is a top view of the GFET bilateral graphene transistor;
FIG. 3 is a diagrammatic cross-sectional view of the GFET transistor;
FIG. 4 is a graph illustrating the operation of the present invention;
FIG. 5 is a cross-sectional view of the PZT capacitor; 10
FIG. 6 is a top view of the PZT capacitor;
FIG. 7 is a cross-sectional view of a MEMS variable capacitor; and
FIG. 8 is a top view of the MEMS variable capacitor.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A voltage controlled oscillator comprising: a substrate, a voltage controlled variable capacitor comprising a layer of lead zirconate titanate (PZT) deposited on the substrate, the PZT layer forming a voltage controlled variable capacitor; a transistor comprising a layer of bilayer graphene formed directly on the same substrate as the PZT layer, the bilayer graphenc layer forming a transistor; and at least one component connected to said transistor and said voltage controlled variable capacitor to form a resonant circuit s wherein a first voltage applied to the voltage controlled variable capacitor adjusts the piezoelectric and ferroelectric properties of the PZT layer so that the capacitance thereof is varied, and varies the output frequency of the resonator circuit, and a second voltage applied to the transistor adjusts the energy band gap of the bilayer graphene layer.
The voltage controlled oscillator as defined in claim 16, further comprising: two signal terminals formed on the bilayer graphene layer.
The voltage controlled oscillator as defined in claim 16, wherein the bilayer graphene layer is deposited on the PZT layer of the capacitor.
The voltage controlled oscillator as defined in claim 16, wherein said at least one component comprises an inductor.
A method of forming the voltage controlled oscillator of claim 16, comprising: forming a voltage controlled variable capacitor including a step of depositing a layer of lead zirconate titanate (PZT) on a substrate to form a voltage controlled variable capacitor; forming a transistor including a step of depositing a layer of bilayer graphene directly on the same substrate as the PZT layer to form a transistor; and connecting at least one component to said transistor and said voltage controlled variable capacitor to form [[a]] the resonant circuit.
A method of operating the voltage controlled oscillator of claim 16, comprising: varying an applied voltage to the PZT layer of the voltage controlled variable capacitor so that the capacitance thereof is varied to vary the output frequency of the transistor.
The voltage controlled oscillator as defined in claim 16, wherein the layer of PZT of the voltage controlled variable capacitor is: (i) deposited on the substrate adjacent to the bilayer graphene layer; or (ii) deposited on the bilayer graphene layer with flip-chip bonding.
The voltage controlled oscillator as defined in claim 16, wherein the transistor comprises a layer of lead zirconate titanate (PZT).
The voltage controlled oscillator as defined in claim 16, wherein the capacitor is electrically connected to the transistor gate terminal. 4
canceled
Layer stacks claimed or described, ordered top of device to substrate.
voltage controlled oscillator with bilayer graphene FET and PZT variable capacitor
Materials described outside the worked examples.
bilayer graphene
lead zirconate titanate
PZT
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a top view of the GFET bilateral graphene transistor;
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,252,704Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a circuit diagram illustrating a preferred embodiment of the present invention;
FIG. 2 is a top view of the GFET bilateral graphene transistor;
FIG. 3 is a diagrammatic cross-sectional view of the GFET transistor;
FIG. 4 is a graph illustrating the operation of the present invention;
FIG. 5 is a cross-sectional view of the PZT capacitor; 10
FIG. 6 is a top view of the PZT capacitor;
FIG. 7 is a cross-sectional view of a MEMS variable capacitor; and
FIG. 8 is a top view of the MEMS variable capacitor.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A voltage controlled oscillator comprising: a substrate, a voltage controlled variable capacitor comprising a layer of lead zirconate titanate (PZT) deposited on the substrate, the PZT layer forming a voltage controlled variable capacitor; a transistor comprising a layer of bilayer graphene formed directly on the same substrate as the PZT layer, the bilayer graphenc layer forming a transistor; and at least one component connected to said transistor and said voltage controlled variable capacitor to form a resonant circuit s wherein a first voltage applied to the voltage controlled variable capacitor adjusts the piezoelectric and ferroelectric properties of the PZT layer so that the capacitance thereof is varied, and varies the output frequency of the resonator circuit, and a second voltage applied to the transistor adjusts the energy band gap of the bilayer graphene layer.
The voltage controlled oscillator as defined in claim 16, further comprising: two signal terminals formed on the bilayer graphene layer.
The voltage controlled oscillator as defined in claim 16, wherein the bilayer graphene layer is deposited on the PZT layer of the capacitor.
The voltage controlled oscillator as defined in claim 16, wherein said at least one component comprises an inductor.
A method of forming the voltage controlled oscillator of claim 16, comprising: forming a voltage controlled variable capacitor including a step of depositing a layer of lead zirconate titanate (PZT) on a substrate to form a voltage controlled variable capacitor; forming a transistor including a step of depositing a layer of bilayer graphene directly on the same substrate as the PZT layer to form a transistor; and connecting at least one component to said transistor and said voltage controlled variable capacitor to form [[a]] the resonant circuit.
A method of operating the voltage controlled oscillator of claim 16, comprising: varying an applied voltage to the PZT layer of the voltage controlled variable capacitor so that the capacitance thereof is varied to vary the output frequency of the transistor.
The voltage controlled oscillator as defined in claim 16, wherein the layer of PZT of the voltage controlled variable capacitor is: (i) deposited on the substrate adjacent to the bilayer graphene layer; or (ii) deposited on the bilayer graphene layer with flip-chip bonding.
The voltage controlled oscillator as defined in claim 16, wherein the transistor comprises a layer of lead zirconate titanate (PZT).
The voltage controlled oscillator as defined in claim 16, wherein the capacitor is electrically connected to the transistor gate terminal. 4
canceled
Layer stacks claimed or described, ordered top of device to substrate.
voltage controlled oscillator with bilayer graphene FET and PZT variable capacitor
Materials described outside the worked examples.
bilayer graphene
lead zirconate titanate
PZT
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a top view of the GFET bilateral graphene transistor;
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,252,704Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a circuit diagram illustrating a preferred embodiment of the present invention;
FIG. 2 is a top view of the GFET bilateral graphene transistor;
FIG. 3 is a diagrammatic cross-sectional view of the GFET transistor;
FIG. 4 is a graph illustrating the operation of the present invention;
FIG. 5 is a cross-sectional view of the PZT capacitor; 10
FIG. 6 is a top view of the PZT capacitor;
FIG. 7 is a cross-sectional view of a MEMS variable capacitor; and
FIG. 8 is a top view of the MEMS variable capacitor.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A voltage controlled oscillator comprising: a substrate, a voltage controlled variable capacitor comprising a layer of lead zirconate titanate (PZT) deposited on the substrate, the PZT layer forming a voltage controlled variable capacitor; a transistor comprising a layer of bilayer graphene formed directly on the same substrate as the PZT layer, the bilayer graphenc layer forming a transistor; and at least one component connected to said transistor and said voltage controlled variable capacitor to form a resonant circuit s wherein a first voltage applied to the voltage controlled variable capacitor adjusts the piezoelectric and ferroelectric properties of the PZT layer so that the capacitance thereof is varied, and varies the output frequency of the resonator circuit, and a second voltage applied to the transistor adjusts the energy band gap of the bilayer graphene layer.
The voltage controlled oscillator as defined in claim 16, further comprising: two signal terminals formed on the bilayer graphene layer.
The voltage controlled oscillator as defined in claim 16, wherein the bilayer graphene layer is deposited on the PZT layer of the capacitor.
The voltage controlled oscillator as defined in claim 16, wherein said at least one component comprises an inductor.
A method of forming the voltage controlled oscillator of claim 16, comprising: forming a voltage controlled variable capacitor including a step of depositing a layer of lead zirconate titanate (PZT) on a substrate to form a voltage controlled variable capacitor; forming a transistor including a step of depositing a layer of bilayer graphene directly on the same substrate as the PZT layer to form a transistor; and connecting at least one component to said transistor and said voltage controlled variable capacitor to form [[a]] the resonant circuit.
A method of operating the voltage controlled oscillator of claim 16, comprising: varying an applied voltage to the PZT layer of the voltage controlled variable capacitor so that the capacitance thereof is varied to vary the output frequency of the transistor.
The voltage controlled oscillator as defined in claim 16, wherein the layer of PZT of the voltage controlled variable capacitor is: (i) deposited on the substrate adjacent to the bilayer graphene layer; or (ii) deposited on the bilayer graphene layer with flip-chip bonding.
The voltage controlled oscillator as defined in claim 16, wherein the transistor comprises a layer of lead zirconate titanate (PZT).
The voltage controlled oscillator as defined in claim 16, wherein the capacitor is electrically connected to the transistor gate terminal. 4
canceled
Layer stacks claimed or described, ordered top of device to substrate.
voltage controlled oscillator with bilayer graphene FET and PZT variable capacitor
Materials described outside the worked examples.
bilayer graphene
lead zirconate titanate
PZT
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a top view of the GFET bilateral graphene transistor;
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,252,704Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a circuit diagram illustrating a preferred embodiment of the present invention;
FIG. 2 is a top view of the GFET bilateral graphene transistor;
FIG. 3 is a diagrammatic cross-sectional view of the GFET transistor;
FIG. 4 is a graph illustrating the operation of the present invention;
FIG. 5 is a cross-sectional view of the PZT capacitor; 10
FIG. 6 is a top view of the PZT capacitor;
FIG. 7 is a cross-sectional view of a MEMS variable capacitor; and
FIG. 8 is a top view of the MEMS variable capacitor.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A voltage controlled oscillator comprising: a substrate, a voltage controlled variable capacitor comprising a layer of lead zirconate titanate (PZT) deposited on the substrate, the PZT layer forming a voltage controlled variable capacitor; a transistor comprising a layer of bilayer graphene formed directly on the same substrate as the PZT layer, the bilayer graphenc layer forming a transistor; and at least one component connected to said transistor and said voltage controlled variable capacitor to form a resonant circuit s wherein a first voltage applied to the voltage controlled variable capacitor adjusts the piezoelectric and ferroelectric properties of the PZT layer so that the capacitance thereof is varied, and varies the output frequency of the resonator circuit, and a second voltage applied to the transistor adjusts the energy band gap of the bilayer graphene layer.
The voltage controlled oscillator as defined in claim 16, further comprising: two signal terminals formed on the bilayer graphene layer.
The voltage controlled oscillator as defined in claim 16, wherein the bilayer graphene layer is deposited on the PZT layer of the capacitor.
The voltage controlled oscillator as defined in claim 16, wherein said at least one component comprises an inductor.
A method of forming the voltage controlled oscillator of claim 16, comprising: forming a voltage controlled variable capacitor including a step of depositing a layer of lead zirconate titanate (PZT) on a substrate to form a voltage controlled variable capacitor; forming a transistor including a step of depositing a layer of bilayer graphene directly on the same substrate as the PZT layer to form a transistor; and connecting at least one component to said transistor and said voltage controlled variable capacitor to form [[a]] the resonant circuit.
A method of operating the voltage controlled oscillator of claim 16, comprising: varying an applied voltage to the PZT layer of the voltage controlled variable capacitor so that the capacitance thereof is varied to vary the output frequency of the transistor.
The voltage controlled oscillator as defined in claim 16, wherein the layer of PZT of the voltage controlled variable capacitor is: (i) deposited on the substrate adjacent to the bilayer graphene layer; or (ii) deposited on the bilayer graphene layer with flip-chip bonding.
The voltage controlled oscillator as defined in claim 16, wherein the transistor comprises a layer of lead zirconate titanate (PZT).
The voltage controlled oscillator as defined in claim 16, wherein the capacitor is electrically connected to the transistor gate terminal. 4
canceled
Layer stacks claimed or described, ordered top of device to substrate.
voltage controlled oscillator with bilayer graphene FET and PZT variable capacitor
Materials described outside the worked examples.
bilayer graphene
lead zirconate titanate
PZT
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a top view of the GFET bilateral graphene transistor;
Related documents with shared materials, methods, properties, or citations.
aluminum nitride
AlN
N+ doped silicon
silicon oxide
SiO₂
FIG. 3 is a diagrammatic cross-sectional view of the GFET transistor;
FIG. 4 is a graph illustrating the operation of the present invention;
aluminum nitride
AlN
N+ doped silicon
silicon oxide
SiO₂
FIG. 3 is a diagrammatic cross-sectional view of the GFET transistor;
FIG. 4 is a graph illustrating the operation of the present invention;
aluminum nitride
AlN
N+ doped silicon
silicon oxide
SiO₂
FIG. 3 is a diagrammatic cross-sectional view of the GFET transistor;
FIG. 4 is a graph illustrating the operation of the present invention;
aluminum nitride
AlN
N+ doped silicon
silicon oxide
SiO₂
FIG. 3 is a diagrammatic cross-sectional view of the GFET transistor;
FIG. 4 is a graph illustrating the operation of the present invention;