Patent
US 8,994,079GRAPHENE ELECTRONIC DEVICES HAVING MULTI-LAYERED GATE INSULATING LAYER
Hyun-jae Song
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,994,079Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to an example embodiment; [0016]
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
FIG. 5 is a schematic cross-sectional view of a structure of a graphene electronic device according to another example embodiment; and [0020]
FIG. 6 is a schematic cross-sectional view of a structure of a graphene electronic device according to still another example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a conductive substrate configured to function as a gate electrode; a gate insulating layer formed on the conductive substrate, the gate insulating layer including an inorganic insulating layer and an organic insulating layer; a graphene channel layer f o rmed on the gate insulating layer; and a source electrode formed on one end of the graphene channel layer and a drain electrode formed on another end of the graphene channel layer, wherein the or g anic insulating layer includes a fluorine group polymer.
(O riginal) The graphene electronic device of claim 1, wherein the organic insulating layer is disposed between the inorganic insulating layer and the graphene channel layer. original
The graphene electronic device of claim 1 [[3]], wherein the fluorine group polymer is one selected from a group consisting of polyviny l fluoride (PVF), polyvinylidene fluoride (PVDF), poly(perfluorobutenylvinylether), polytetrafluoroethylene (PTFE), and an amorphous fluoropoly m er. SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349591.1.1355.154.2247.307.svg 0.51 2.973 Graph Black and white
5. The graphene electronic device of claim 1, wherein the organic insulating layer has a thickness smaller than that of the inorganic insulating layer.
The graphene electronic device of claim 1, wherein the organic insulating layer has a thickness in a range from about 1 nm to about 20 nm.
The graphene electronic device of claim 1, wherein the inorganic insulating layer is formed of one material selected from a group consisting of a silicon oxide, an aluminum oxide, and a hafnium oxide.
The graphene electronic device of claim 1, wherein the graphene channel layer includes one of single-layer graphene and bi -layer graphene.
The graphene electronic device of claim 1, wherein the graphene channel layer is a nano-ribbon graphene channel layer, and the graphene electronic device is a field effect transistor.
The graphene electronic device of claim 1, further comprising: a passivation layer configured to cover the graphene channel layer.
The graphene electronic device of claim 1 1, wherein the graphene channel layer includes one of a single-layer graphene and a b i-layer graphene. withdrawn
. canceled
(Withdrawn-Currently Amended) A graphene electronic device comprising: a graphene channel layer formed on a substrate; a source electrode formed on one end of the graphene channel layer and a drain electrode formed on another end of the graphene channel layer; SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349592.1.1353.152.2247.303.svg 0.503 2.98 Graph Black and white a gate insulating layer formed to cover the graphene channel layer between the source electrode and the drain electrode, the gate insulating layer including an organic insulating layer and an inorganic insulating layer; and a gate electrode formed on the gate insulating layer between the source electrode and the drain electrode wherein the organic insulating layer includes a fluorine grou p polymer.
The graphe n e electronic device of claim 11, wherein the organic insulating layer is formed between the inorganic insulating layer and the graphe ne channel layer. withdrawn
(Withdrawn-Currently Amended) The graphe n e electronic device of claim 11 [[3]], wherein the fluorine group polymer is one selected from a group consisting of polyvinylfluoride (PVF), polyvinylidene fluoride (PVDF), poly(per f luorobutenylvinylether), polytetrafluoroethylene (PTFE), and an amorphous fluoropoly m er.
The graphe n e electronic device of claim 11, wherein the organic insulating layer has a thickness smaller than that of the inorganic insulating layer. withdrawn
The graphe n e electronic device of claim 11, wherein the organic insulating layer has a thickness in a range from about 1 nm to about 20 nm. SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349593.1.1354.154.2248.305.svg 0.503 2.98 Graph Black and white withdrawn
The graphene electronic device of claim 11, wherein the inorganic insulating layer is formed of one material selected from a group consisting of a silicon oxide, an aluminum oxide, and a hafnium oxide. withdrawn
The graphene electronic device of claim 11, wherein the graphene channel layer is a nanoribbon graphene channel layer, and the graphene electronic device is a field effect transistor. *** END CLAIM LISTING ** withdrawn
. canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A bottom-gate graphene FET is fabricated with a Si substrate (100 nm SiO₂ inorganic insulating layer) and a 7 nm poly(perfluorobutenylvinylether) organic insulating layer. The graphene channel is exfoliated graphene. Source/drain electrodes are 5 nm Cr/100 nm Au. Electrical characteristics (drain current vs. gate voltage) are measured at 45% relative humidity.
Layer stacks claimed or described, ordered top of device to substrate.
bottom-gate graphene field effect transistor
bottom-gate graphene nano-ribbon field effect transistor
Materials described outside the worked examples.
inorganic insulating layer
organic insulating layer (fluorine group polymer)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Dirac voltage (V_Dirac) of conventional graphene FET (SiO2 only, as fabricated) | 26.7 V | C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,994,079Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to an example embodiment; [0016]
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
FIG. 5 is a schematic cross-sectional view of a structure of a graphene electronic device according to another example embodiment; and [0020]
FIG. 6 is a schematic cross-sectional view of a structure of a graphene electronic device according to still another example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a conductive substrate configured to function as a gate electrode; a gate insulating layer formed on the conductive substrate, the gate insulating layer including an inorganic insulating layer and an organic insulating layer; a graphene channel layer f o rmed on the gate insulating layer; and a source electrode formed on one end of the graphene channel layer and a drain electrode formed on another end of the graphene channel layer, wherein the or g anic insulating layer includes a fluorine group polymer.
(O riginal) The graphene electronic device of claim 1, wherein the organic insulating layer is disposed between the inorganic insulating layer and the graphene channel layer. original
The graphene electronic device of claim 1 [[3]], wherein the fluorine group polymer is one selected from a group consisting of polyviny l fluoride (PVF), polyvinylidene fluoride (PVDF), poly(perfluorobutenylvinylether), polytetrafluoroethylene (PTFE), and an amorphous fluoropoly m er. SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349591.1.1355.154.2247.307.svg 0.51 2.973 Graph Black and white
5. The graphene electronic device of claim 1, wherein the organic insulating layer has a thickness smaller than that of the inorganic insulating layer.
The graphene electronic device of claim 1, wherein the organic insulating layer has a thickness in a range from about 1 nm to about 20 nm.
The graphene electronic device of claim 1, wherein the inorganic insulating layer is formed of one material selected from a group consisting of a silicon oxide, an aluminum oxide, and a hafnium oxide.
The graphene electronic device of claim 1, wherein the graphene channel layer includes one of single-layer graphene and bi -layer graphene.
The graphene electronic device of claim 1, wherein the graphene channel layer is a nano-ribbon graphene channel layer, and the graphene electronic device is a field effect transistor.
The graphene electronic device of claim 1, further comprising: a passivation layer configured to cover the graphene channel layer.
The graphene electronic device of claim 1 1, wherein the graphene channel layer includes one of a single-layer graphene and a b i-layer graphene. withdrawn
. canceled
(Withdrawn-Currently Amended) A graphene electronic device comprising: a graphene channel layer formed on a substrate; a source electrode formed on one end of the graphene channel layer and a drain electrode formed on another end of the graphene channel layer; SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349592.1.1353.152.2247.303.svg 0.503 2.98 Graph Black and white a gate insulating layer formed to cover the graphene channel layer between the source electrode and the drain electrode, the gate insulating layer including an organic insulating layer and an inorganic insulating layer; and a gate electrode formed on the gate insulating layer between the source electrode and the drain electrode wherein the organic insulating layer includes a fluorine grou p polymer.
The graphe n e electronic device of claim 11, wherein the organic insulating layer is formed between the inorganic insulating layer and the graphe ne channel layer. withdrawn
(Withdrawn-Currently Amended) The graphe n e electronic device of claim 11 [[3]], wherein the fluorine group polymer is one selected from a group consisting of polyvinylfluoride (PVF), polyvinylidene fluoride (PVDF), poly(per f luorobutenylvinylether), polytetrafluoroethylene (PTFE), and an amorphous fluoropoly m er.
The graphe n e electronic device of claim 11, wherein the organic insulating layer has a thickness smaller than that of the inorganic insulating layer. withdrawn
The graphe n e electronic device of claim 11, wherein the organic insulating layer has a thickness in a range from about 1 nm to about 20 nm. SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349593.1.1354.154.2248.305.svg 0.503 2.98 Graph Black and white withdrawn
The graphene electronic device of claim 11, wherein the inorganic insulating layer is formed of one material selected from a group consisting of a silicon oxide, an aluminum oxide, and a hafnium oxide. withdrawn
The graphene electronic device of claim 11, wherein the graphene channel layer is a nanoribbon graphene channel layer, and the graphene electronic device is a field effect transistor. *** END CLAIM LISTING ** withdrawn
. canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A bottom-gate graphene FET is fabricated with a Si substrate (100 nm SiO₂ inorganic insulating layer) and a 7 nm poly(perfluorobutenylvinylether) organic insulating layer. The graphene channel is exfoliated graphene. Source/drain electrodes are 5 nm Cr/100 nm Au. Electrical characteristics (drain current vs. gate voltage) are measured at 45% relative humidity.
Layer stacks claimed or described, ordered top of device to substrate.
bottom-gate graphene field effect transistor
bottom-gate graphene nano-ribbon field effect transistor
Materials described outside the worked examples.
inorganic insulating layer
organic insulating layer (fluorine group polymer)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Dirac voltage (V_Dirac) of conventional graphene FET (SiO2 only, as fabricated) | 26.7 V | C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,994,079Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to an example embodiment; [0016]
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
FIG. 5 is a schematic cross-sectional view of a structure of a graphene electronic device according to another example embodiment; and [0020]
FIG. 6 is a schematic cross-sectional view of a structure of a graphene electronic device according to still another example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a conductive substrate configured to function as a gate electrode; a gate insulating layer formed on the conductive substrate, the gate insulating layer including an inorganic insulating layer and an organic insulating layer; a graphene channel layer f o rmed on the gate insulating layer; and a source electrode formed on one end of the graphene channel layer and a drain electrode formed on another end of the graphene channel layer, wherein the or g anic insulating layer includes a fluorine group polymer.
(O riginal) The graphene electronic device of claim 1, wherein the organic insulating layer is disposed between the inorganic insulating layer and the graphene channel layer. original
The graphene electronic device of claim 1 [[3]], wherein the fluorine group polymer is one selected from a group consisting of polyviny l fluoride (PVF), polyvinylidene fluoride (PVDF), poly(perfluorobutenylvinylether), polytetrafluoroethylene (PTFE), and an amorphous fluoropoly m er. SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349591.1.1355.154.2247.307.svg 0.51 2.973 Graph Black and white
5. The graphene electronic device of claim 1, wherein the organic insulating layer has a thickness smaller than that of the inorganic insulating layer.
The graphene electronic device of claim 1, wherein the organic insulating layer has a thickness in a range from about 1 nm to about 20 nm.
The graphene electronic device of claim 1, wherein the inorganic insulating layer is formed of one material selected from a group consisting of a silicon oxide, an aluminum oxide, and a hafnium oxide.
The graphene electronic device of claim 1, wherein the graphene channel layer includes one of single-layer graphene and bi -layer graphene.
The graphene electronic device of claim 1, wherein the graphene channel layer is a nano-ribbon graphene channel layer, and the graphene electronic device is a field effect transistor.
The graphene electronic device of claim 1, further comprising: a passivation layer configured to cover the graphene channel layer.
The graphene electronic device of claim 1 1, wherein the graphene channel layer includes one of a single-layer graphene and a b i-layer graphene. withdrawn
. canceled
(Withdrawn-Currently Amended) A graphene electronic device comprising: a graphene channel layer formed on a substrate; a source electrode formed on one end of the graphene channel layer and a drain electrode formed on another end of the graphene channel layer; SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349592.1.1353.152.2247.303.svg 0.503 2.98 Graph Black and white a gate insulating layer formed to cover the graphene channel layer between the source electrode and the drain electrode, the gate insulating layer including an organic insulating layer and an inorganic insulating layer; and a gate electrode formed on the gate insulating layer between the source electrode and the drain electrode wherein the organic insulating layer includes a fluorine grou p polymer.
The graphe n e electronic device of claim 11, wherein the organic insulating layer is formed between the inorganic insulating layer and the graphe ne channel layer. withdrawn
(Withdrawn-Currently Amended) The graphe n e electronic device of claim 11 [[3]], wherein the fluorine group polymer is one selected from a group consisting of polyvinylfluoride (PVF), polyvinylidene fluoride (PVDF), poly(per f luorobutenylvinylether), polytetrafluoroethylene (PTFE), and an amorphous fluoropoly m er.
The graphe n e electronic device of claim 11, wherein the organic insulating layer has a thickness smaller than that of the inorganic insulating layer. withdrawn
The graphe n e electronic device of claim 11, wherein the organic insulating layer has a thickness in a range from about 1 nm to about 20 nm. SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349593.1.1354.154.2248.305.svg 0.503 2.98 Graph Black and white withdrawn
The graphene electronic device of claim 11, wherein the inorganic insulating layer is formed of one material selected from a group consisting of a silicon oxide, an aluminum oxide, and a hafnium oxide. withdrawn
The graphene electronic device of claim 11, wherein the graphene channel layer is a nanoribbon graphene channel layer, and the graphene electronic device is a field effect transistor. *** END CLAIM LISTING ** withdrawn
. canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A bottom-gate graphene FET is fabricated with a Si substrate (100 nm SiO₂ inorganic insulating layer) and a 7 nm poly(perfluorobutenylvinylether) organic insulating layer. The graphene channel is exfoliated graphene. Source/drain electrodes are 5 nm Cr/100 nm Au. Electrical characteristics (drain current vs. gate voltage) are measured at 45% relative humidity.
Layer stacks claimed or described, ordered top of device to substrate.
bottom-gate graphene field effect transistor
bottom-gate graphene nano-ribbon field effect transistor
Materials described outside the worked examples.
inorganic insulating layer
organic insulating layer (fluorine group polymer)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Dirac voltage (V_Dirac) of conventional graphene FET (SiO2 only, as fabricated) | 26.7 V | C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,994,079Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view showing a structure of a graphene electronic device according to an example embodiment; [0016]
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
FIG. 5 is a schematic cross-sectional view of a structure of a graphene electronic device according to another example embodiment; and [0020]
FIG. 6 is a schematic cross-sectional view of a structure of a graphene electronic device according to still another example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene electronic device comprising: a conductive substrate configured to function as a gate electrode; a gate insulating layer formed on the conductive substrate, the gate insulating layer including an inorganic insulating layer and an organic insulating layer; a graphene channel layer f o rmed on the gate insulating layer; and a source electrode formed on one end of the graphene channel layer and a drain electrode formed on another end of the graphene channel layer, wherein the or g anic insulating layer includes a fluorine group polymer.
(O riginal) The graphene electronic device of claim 1, wherein the organic insulating layer is disposed between the inorganic insulating layer and the graphene channel layer. original
The graphene electronic device of claim 1 [[3]], wherein the fluorine group polymer is one selected from a group consisting of polyviny l fluoride (PVF), polyvinylidene fluoride (PVDF), poly(perfluorobutenylvinylether), polytetrafluoroethylene (PTFE), and an amorphous fluoropoly m er. SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349591.1.1355.154.2247.307.svg 0.51 2.973 Graph Black and white
5. The graphene electronic device of claim 1, wherein the organic insulating layer has a thickness smaller than that of the inorganic insulating layer.
The graphene electronic device of claim 1, wherein the organic insulating layer has a thickness in a range from about 1 nm to about 20 nm.
The graphene electronic device of claim 1, wherein the inorganic insulating layer is formed of one material selected from a group consisting of a silicon oxide, an aluminum oxide, and a hafnium oxide.
The graphene electronic device of claim 1, wherein the graphene channel layer includes one of single-layer graphene and bi -layer graphene.
The graphene electronic device of claim 1, wherein the graphene channel layer is a nano-ribbon graphene channel layer, and the graphene electronic device is a field effect transistor.
The graphene electronic device of claim 1, further comprising: a passivation layer configured to cover the graphene channel layer.
The graphene electronic device of claim 1 1, wherein the graphene channel layer includes one of a single-layer graphene and a b i-layer graphene. withdrawn
. canceled
(Withdrawn-Currently Amended) A graphene electronic device comprising: a graphene channel layer formed on a substrate; a source electrode formed on one end of the graphene channel layer and a drain electrode formed on another end of the graphene channel layer; SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349592.1.1353.152.2247.303.svg 0.503 2.98 Graph Black and white a gate insulating layer formed to cover the graphene channel layer between the source electrode and the drain electrode, the gate insulating layer including an organic insulating layer and an inorganic insulating layer; and a gate electrode formed on the gate insulating layer between the source electrode and the drain electrode wherein the organic insulating layer includes a fluorine grou p polymer.
The graphe n e electronic device of claim 11, wherein the organic insulating layer is formed between the inorganic insulating layer and the graphe ne channel layer. withdrawn
(Withdrawn-Currently Amended) The graphe n e electronic device of claim 11 [[3]], wherein the fluorine group polymer is one selected from a group consisting of polyvinylfluoride (PVF), polyvinylidene fluoride (PVDF), poly(per f luorobutenylvinylether), polytetrafluoroethylene (PTFE), and an amorphous fluoropoly m er.
The graphe n e electronic device of claim 11, wherein the organic insulating layer has a thickness smaller than that of the inorganic insulating layer. withdrawn
The graphe n e electronic device of claim 11, wherein the organic insulating layer has a thickness in a range from about 1 nm to about 20 nm. SVG 13491999.09-18-2014.I₀DU₅₈MFPXXIFW2.CLM28349593.1.1354.154.2248.305.svg 0.503 2.98 Graph Black and white withdrawn
The graphene electronic device of claim 11, wherein the inorganic insulating layer is formed of one material selected from a group consisting of a silicon oxide, an aluminum oxide, and a hafnium oxide. withdrawn
The graphene electronic device of claim 11, wherein the graphene channel layer is a nanoribbon graphene channel layer, and the graphene electronic device is a field effect transistor. *** END CLAIM LISTING ** withdrawn
. canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A bottom-gate graphene FET is fabricated with a Si substrate (100 nm SiO₂ inorganic insulating layer) and a 7 nm poly(perfluorobutenylvinylether) organic insulating layer. The graphene channel is exfoliated graphene. Source/drain electrodes are 5 nm Cr/100 nm Au. Electrical characteristics (drain current vs. gate voltage) are measured at 45% relative humidity.
Layer stacks claimed or described, ordered top of device to substrate.
bottom-gate graphene field effect transistor
bottom-gate graphene nano-ribbon field effect transistor
Materials described outside the worked examples.
inorganic insulating layer
organic insulating layer (fluorine group polymer)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Dirac voltage (V_Dirac) of conventional graphene FET (SiO2 only, as fabricated) | 26.7 V | C |
Related documents with shared materials, methods, properties, or citations.
top-gate graphene field effect transistor
top-gate graphene nano-ribbon field effect transistor
polyvinyl fluoride
PVF
polyvinylidene fluoride
PVDF
polytetrafluoroethylene
PTFE
amorphous fluoropolymer
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
Thickness | 100–300 nm | — |
Thickness | 1–20 nm | — |
Thickness | 5–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |
Thickness | ≥ 1 nm | — |
top-gate graphene field effect transistor
top-gate graphene nano-ribbon field effect transistor
polyvinyl fluoride
PVF
polyvinylidene fluoride
PVDF
polytetrafluoroethylene
PTFE
amorphous fluoropolymer
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
Thickness | 100–300 nm | — |
Thickness | 1–20 nm | — |
Thickness | 5–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |
Thickness | ≥ 1 nm | — |
top-gate graphene field effect transistor
top-gate graphene nano-ribbon field effect transistor
polyvinyl fluoride
PVF
polyvinylidene fluoride
PVDF
polytetrafluoroethylene
PTFE
amorphous fluoropolymer
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
Thickness | 100–300 nm | — |
Thickness | 1–20 nm | — |
Thickness | 5–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |
Thickness | ≥ 1 nm | — |
top-gate graphene field effect transistor
top-gate graphene nano-ribbon field effect transistor
polyvinyl fluoride
PVF
polyvinylidene fluoride
PVDF
polytetrafluoroethylene
PTFE
amorphous fluoropolymer
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
FIG. 2 is a graph showing drain current characteristics according to a gate voltage of a field effect transistor (FET) in which a gate insulating layer is formed …
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 3 is a graph showing drain current characteristics according to a gate voltage of a FET having the structure of
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
FIG. 4 is a graph showing variations of hole mobility according to the increase in exposure time in air of a conventional graphene FET and a graphene FET …
Thickness | 100–300 nm | — |
Thickness | 1–20 nm | — |
Thickness | 5–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 20 nm | — |
Thickness | ≥ 1 nm | — |