Patent
US 8,803,131METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES
Yu-Ming Lin
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,803,131Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er application of mask material. [0011]
FIG. 3 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching regions of the graphene …
FIG. 4 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes after doping of a portion of the graphene. …
FIG. 5 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er formation of a dielectric layer. …
FIG. 6 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er application of mask material to …
FIG. 8 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er formation of a carbon nanotube …
FIG. 9A illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching of the carbon nanotube …
FIG. 10 illustrates a method of fabricating of an integrated circuit comprising graphene and carbon nanotubes.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENTS TO THE CLAIMS 1. An integrated circuit comprising: a graphene layer disposed on a substrate, the graphene layer comprising a region of undoped graphene and a region of doped graphene adjacent the region of undoped graphene, the undoped graphene comprising a channel of a transistor, and the region of doped graphene comprising a contact of the transistor; SVG 13604254.02-12-2014.HRQP₀D₃YPXXIFW1.CLM.1.svg 0.76 5.69 Black and white a dielectric layer located on top of the graphene layer and underneath the gate of the transistor, such that the first portion of the etched carbon nanotube film is isolated from the undoped graphene channel by the dielectric lay er; a via formed through the dielectric layer, and filled with a second portion of the carbon nanotube film; and a top level interconnect formed on top of the dielectric layer and in contact with the via, the top level interconnect comprising a third portion of the carbon nanotube film.
The integrated circuit of claim 1, wherein the dielectric layer comprises an oxide material.
The integrated circuit of claim 1, wherein the graphene layer is between about 0.35 nanometers (nm) and about 7nm thick.
The integrated circuit of claim 1, further comprising a substrate located underneath the graphene layer, the substrate comprising an oxide material.
The integrated circuit of claim 1, wherein the doped graphene comprises an organic molecule.
canceled
canceled
canceled
3 canceled
Layer stacks claimed or described, ordered top of device to substrate.
metal-free graphene/carbon nanotube transistor integrated circuit
Materials described outside the worked examples.
undoped graphene
doped graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9A illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching of the carbon nanotube …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness | 0.35–7 nm | graphene layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,803,131Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er application of mask material. [0011]
FIG. 3 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching regions of the graphene …
FIG. 4 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes after doping of a portion of the graphene. …
FIG. 5 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er formation of a dielectric layer. …
FIG. 6 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er application of mask material to …
FIG. 8 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er formation of a carbon nanotube …
FIG. 9A illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching of the carbon nanotube …
FIG. 10 illustrates a method of fabricating of an integrated circuit comprising graphene and carbon nanotubes.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENTS TO THE CLAIMS 1. An integrated circuit comprising: a graphene layer disposed on a substrate, the graphene layer comprising a region of undoped graphene and a region of doped graphene adjacent the region of undoped graphene, the undoped graphene comprising a channel of a transistor, and the region of doped graphene comprising a contact of the transistor; SVG 13604254.02-12-2014.HRQP₀D₃YPXXIFW1.CLM.1.svg 0.76 5.69 Black and white a dielectric layer located on top of the graphene layer and underneath the gate of the transistor, such that the first portion of the etched carbon nanotube film is isolated from the undoped graphene channel by the dielectric lay er; a via formed through the dielectric layer, and filled with a second portion of the carbon nanotube film; and a top level interconnect formed on top of the dielectric layer and in contact with the via, the top level interconnect comprising a third portion of the carbon nanotube film.
The integrated circuit of claim 1, wherein the dielectric layer comprises an oxide material.
The integrated circuit of claim 1, wherein the graphene layer is between about 0.35 nanometers (nm) and about 7nm thick.
The integrated circuit of claim 1, further comprising a substrate located underneath the graphene layer, the substrate comprising an oxide material.
The integrated circuit of claim 1, wherein the doped graphene comprises an organic molecule.
canceled
canceled
canceled
3 canceled
Layer stacks claimed or described, ordered top of device to substrate.
metal-free graphene/carbon nanotube transistor integrated circuit
Materials described outside the worked examples.
undoped graphene
doped graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9A illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching of the carbon nanotube …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness | 0.35–7 nm | graphene layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,803,131Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er application of mask material. [0011]
FIG. 3 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching regions of the graphene …
FIG. 4 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes after doping of a portion of the graphene. …
FIG. 5 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er formation of a dielectric layer. …
FIG. 6 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er application of mask material to …
FIG. 8 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er formation of a carbon nanotube …
FIG. 9A illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching of the carbon nanotube …
FIG. 10 illustrates a method of fabricating of an integrated circuit comprising graphene and carbon nanotubes.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENTS TO THE CLAIMS 1. An integrated circuit comprising: a graphene layer disposed on a substrate, the graphene layer comprising a region of undoped graphene and a region of doped graphene adjacent the region of undoped graphene, the undoped graphene comprising a channel of a transistor, and the region of doped graphene comprising a contact of the transistor; SVG 13604254.02-12-2014.HRQP₀D₃YPXXIFW1.CLM.1.svg 0.76 5.69 Black and white a dielectric layer located on top of the graphene layer and underneath the gate of the transistor, such that the first portion of the etched carbon nanotube film is isolated from the undoped graphene channel by the dielectric lay er; a via formed through the dielectric layer, and filled with a second portion of the carbon nanotube film; and a top level interconnect formed on top of the dielectric layer and in contact with the via, the top level interconnect comprising a third portion of the carbon nanotube film.
The integrated circuit of claim 1, wherein the dielectric layer comprises an oxide material.
The integrated circuit of claim 1, wherein the graphene layer is between about 0.35 nanometers (nm) and about 7nm thick.
The integrated circuit of claim 1, further comprising a substrate located underneath the graphene layer, the substrate comprising an oxide material.
The integrated circuit of claim 1, wherein the doped graphene comprises an organic molecule.
canceled
canceled
canceled
3 canceled
Layer stacks claimed or described, ordered top of device to substrate.
metal-free graphene/carbon nanotube transistor integrated circuit
Materials described outside the worked examples.
undoped graphene
doped graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9A illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching of the carbon nanotube …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness | 0.35–7 nm | graphene layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,803,131Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er application of mask material. [0011]
FIG. 3 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching regions of the graphene …
FIG. 4 illustrates a top view of an embodiment of an integrated circuit comprising graphene and carbon nanotubes after doping of a portion of the graphene. …
FIG. 5 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er formation of a dielectric layer. …
FIG. 6 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er application of mask material to …
FIG. 8 illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er formation of a carbon nanotube …
FIG. 9A illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching of the carbon nanotube …
FIG. 10 illustrates a method of fabricating of an integrated circuit comprising graphene and carbon nanotubes.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENTS TO THE CLAIMS 1. An integrated circuit comprising: a graphene layer disposed on a substrate, the graphene layer comprising a region of undoped graphene and a region of doped graphene adjacent the region of undoped graphene, the undoped graphene comprising a channel of a transistor, and the region of doped graphene comprising a contact of the transistor; SVG 13604254.02-12-2014.HRQP₀D₃YPXXIFW1.CLM.1.svg 0.76 5.69 Black and white a dielectric layer located on top of the graphene layer and underneath the gate of the transistor, such that the first portion of the etched carbon nanotube film is isolated from the undoped graphene channel by the dielectric lay er; a via formed through the dielectric layer, and filled with a second portion of the carbon nanotube film; and a top level interconnect formed on top of the dielectric layer and in contact with the via, the top level interconnect comprising a third portion of the carbon nanotube film.
The integrated circuit of claim 1, wherein the dielectric layer comprises an oxide material.
The integrated circuit of claim 1, wherein the graphene layer is between about 0.35 nanometers (nm) and about 7nm thick.
The integrated circuit of claim 1, further comprising a substrate located underneath the graphene layer, the substrate comprising an oxide material.
The integrated circuit of claim 1, wherein the doped graphene comprises an organic molecule.
canceled
canceled
canceled
3 canceled
Layer stacks claimed or described, ordered top of device to substrate.
metal-free graphene/carbon nanotube transistor integrated circuit
Materials described outside the worked examples.
undoped graphene
doped graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9A illustrates a cross section of an embodiment of an integrated circuit comprising graphene and carbon nanotubes af t er etching of the carbon nanotube …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness | 0.35–7 nm | graphene layer |
Related documents with shared materials, methods, properties, or citations.
graphene layer
oxide material (dielectric)
oxide substrate
organic molecule dopant
polyethyleneimine (PEI)
diazonium
hafnium oxide
HfO₂
silicon oxide
SiO₂
aluminum oxide
Al₂O₃
polymethyl methacrylate (PMMA)
graphene layer
oxide material (dielectric)
oxide substrate
organic molecule dopant
polyethyleneimine (PEI)
diazonium
hafnium oxide
HfO₂
silicon oxide
SiO₂
aluminum oxide
Al₂O₃
polymethyl methacrylate (PMMA)
graphene layer
oxide material (dielectric)
oxide substrate
organic molecule dopant
polyethyleneimine (PEI)
diazonium
hafnium oxide
HfO₂
silicon oxide
SiO₂
aluminum oxide
Al₂O₃
polymethyl methacrylate (PMMA)
graphene layer
oxide material (dielectric)
oxide substrate
organic molecule dopant
polyethyleneimine (PEI)
diazonium
hafnium oxide
HfO₂
silicon oxide
SiO₂
aluminum oxide
Al₂O₃
polymethyl methacrylate (PMMA)