Patent
US 8,753,965A GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE
Phaedon Avouris
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,753,965Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of a graphene layer. [0012]
FIG. 2 is a vertical cross-sectional view of the exemplary structure after patterning of the graphene layer. [0014]
FIG. 3 is a vertical cross-sectional view of the exemplary structure after deposition of a seed layer. [0016]
FIG. 4 is a vertical cross-sectional view of the exemplary structure after deposition of a blanket gate dielectric layer. [0017]
FIG. 5 is a vertical cross-sectional view of the exemplary structure after formation of a stack of a first metal portion and a second metal portion. [0018]
FIG. 6 is a vertical cross-sectional view of the exemplary structure after lateral recessing of the first metal portion and removal of exposed portions of the …
FIG. 7 is a vertical cross-sectional view of the exemplary structure after removal of the dielectric seed layer. [0020]
FIG. 8 is a vertical cross-sectional view of the exemplary structure after formation of contact metal portions, which constitute a gate electrode, a source …
FIG. 9 is a vertical cross-sectional view of the exemplary structure after formation of a contact level dielectric material layer and conductive contact via …
FIG. 10 is a vertical cross-sectional view of a variation of the exemplary structure. [0025]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a transistor structure comprising: forming a graphene layer directly on an upper surface of an insulating layer, wherein an entirety of a bottom surface of said graphene layer directly contacts said upper surface of said insulator layer; forming a stack of a first metal portion and a second metal portion over said graphene layer, wherein said second metal portion directly contacts said first metal portion and-whe rein peien; and laterally offsetting [[said]] sidewalls of said first metal portion relative to [[said]] sidewalls of said second metal portion by a lateral distance.
The method of Claim 1, further comprising: forming a blanket gate dielectric layer over said graphene layer, wherein said first metal portion is formed on said blanket gate dielectric layer; and patterning said blanket gate dielectric layer employing said second first metal portion as an etch mask, wherein a gate dielectric straddling over said portion of said graphene layer is formed.
The method of Claim 1, wherein said second metal portion overhangs said first metal portion by an overhang distance that is constant around the entirety of sidewalls of said first metal portion.
The method of Claim 1, wherein said second metal portion includes an elemental noble metal selected from ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, and gold, and said first metal portion does not include an elemental noble metal.
The method of Claim 1, further comprising: forming a first electrode contacting a portion of said graphene layer and laterally offset from a first sidewall of said first metal portion by said lateral distance; and 3 I: \IBM\105\26374A\AMEND\26374A.am2. doc forming a second electrode contacting another portion of said graphene layer and laterally offset from a second sidewall of said first metal portion by said lateral distance.
The method of Claim 1, wherein said second metal portion includes an elemental noble metal selected from ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, and gold, and said first metal portion does not include an elemental noble metal.
The method of Claim 1, wherein said forming the stack comprises depositing a first metal layer and a second metal layer as blanket metal layers sequentially, and lithographically patterning the second metal layer and the first metal layer in a subsequent processing step.
The method of Claim 1, wherein said laterally offsetting said sidewalls of the first metal portion relative to said sidewalls of said second metal portion comprises a lateral wet etching processing. 5 I:\IBM\1 05\26374A\A M END\26374A. am2.doc
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor with self-aligned gate
Materials described outside the worked examples.
graphene layer
C
first metal portion
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.6–10 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,753,965Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of a graphene layer. [0012]
FIG. 2 is a vertical cross-sectional view of the exemplary structure after patterning of the graphene layer. [0014]
FIG. 3 is a vertical cross-sectional view of the exemplary structure after deposition of a seed layer. [0016]
FIG. 4 is a vertical cross-sectional view of the exemplary structure after deposition of a blanket gate dielectric layer. [0017]
FIG. 5 is a vertical cross-sectional view of the exemplary structure after formation of a stack of a first metal portion and a second metal portion. [0018]
FIG. 6 is a vertical cross-sectional view of the exemplary structure after lateral recessing of the first metal portion and removal of exposed portions of the …
FIG. 7 is a vertical cross-sectional view of the exemplary structure after removal of the dielectric seed layer. [0020]
FIG. 8 is a vertical cross-sectional view of the exemplary structure after formation of contact metal portions, which constitute a gate electrode, a source …
FIG. 9 is a vertical cross-sectional view of the exemplary structure after formation of a contact level dielectric material layer and conductive contact via …
FIG. 10 is a vertical cross-sectional view of a variation of the exemplary structure. [0025]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a transistor structure comprising: forming a graphene layer directly on an upper surface of an insulating layer, wherein an entirety of a bottom surface of said graphene layer directly contacts said upper surface of said insulator layer; forming a stack of a first metal portion and a second metal portion over said graphene layer, wherein said second metal portion directly contacts said first metal portion and-whe rein peien; and laterally offsetting [[said]] sidewalls of said first metal portion relative to [[said]] sidewalls of said second metal portion by a lateral distance.
The method of Claim 1, further comprising: forming a blanket gate dielectric layer over said graphene layer, wherein said first metal portion is formed on said blanket gate dielectric layer; and patterning said blanket gate dielectric layer employing said second first metal portion as an etch mask, wherein a gate dielectric straddling over said portion of said graphene layer is formed.
The method of Claim 1, wherein said second metal portion overhangs said first metal portion by an overhang distance that is constant around the entirety of sidewalls of said first metal portion.
The method of Claim 1, wherein said second metal portion includes an elemental noble metal selected from ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, and gold, and said first metal portion does not include an elemental noble metal.
The method of Claim 1, further comprising: forming a first electrode contacting a portion of said graphene layer and laterally offset from a first sidewall of said first metal portion by said lateral distance; and 3 I: \IBM\105\26374A\AMEND\26374A.am2. doc forming a second electrode contacting another portion of said graphene layer and laterally offset from a second sidewall of said first metal portion by said lateral distance.
The method of Claim 1, wherein said second metal portion includes an elemental noble metal selected from ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, and gold, and said first metal portion does not include an elemental noble metal.
The method of Claim 1, wherein said forming the stack comprises depositing a first metal layer and a second metal layer as blanket metal layers sequentially, and lithographically patterning the second metal layer and the first metal layer in a subsequent processing step.
The method of Claim 1, wherein said laterally offsetting said sidewalls of the first metal portion relative to said sidewalls of said second metal portion comprises a lateral wet etching processing. 5 I:\IBM\1 05\26374A\A M END\26374A. am2.doc
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor with self-aligned gate
Materials described outside the worked examples.
graphene layer
C
first metal portion
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.6–10 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,753,965Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of a graphene layer. [0012]
FIG. 2 is a vertical cross-sectional view of the exemplary structure after patterning of the graphene layer. [0014]
FIG. 3 is a vertical cross-sectional view of the exemplary structure after deposition of a seed layer. [0016]
FIG. 4 is a vertical cross-sectional view of the exemplary structure after deposition of a blanket gate dielectric layer. [0017]
FIG. 5 is a vertical cross-sectional view of the exemplary structure after formation of a stack of a first metal portion and a second metal portion. [0018]
FIG. 6 is a vertical cross-sectional view of the exemplary structure after lateral recessing of the first metal portion and removal of exposed portions of the …
FIG. 7 is a vertical cross-sectional view of the exemplary structure after removal of the dielectric seed layer. [0020]
FIG. 8 is a vertical cross-sectional view of the exemplary structure after formation of contact metal portions, which constitute a gate electrode, a source …
FIG. 9 is a vertical cross-sectional view of the exemplary structure after formation of a contact level dielectric material layer and conductive contact via …
FIG. 10 is a vertical cross-sectional view of a variation of the exemplary structure. [0025]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a transistor structure comprising: forming a graphene layer directly on an upper surface of an insulating layer, wherein an entirety of a bottom surface of said graphene layer directly contacts said upper surface of said insulator layer; forming a stack of a first metal portion and a second metal portion over said graphene layer, wherein said second metal portion directly contacts said first metal portion and-whe rein peien; and laterally offsetting [[said]] sidewalls of said first metal portion relative to [[said]] sidewalls of said second metal portion by a lateral distance.
The method of Claim 1, further comprising: forming a blanket gate dielectric layer over said graphene layer, wherein said first metal portion is formed on said blanket gate dielectric layer; and patterning said blanket gate dielectric layer employing said second first metal portion as an etch mask, wherein a gate dielectric straddling over said portion of said graphene layer is formed.
The method of Claim 1, wherein said second metal portion overhangs said first metal portion by an overhang distance that is constant around the entirety of sidewalls of said first metal portion.
The method of Claim 1, wherein said second metal portion includes an elemental noble metal selected from ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, and gold, and said first metal portion does not include an elemental noble metal.
The method of Claim 1, further comprising: forming a first electrode contacting a portion of said graphene layer and laterally offset from a first sidewall of said first metal portion by said lateral distance; and 3 I: \IBM\105\26374A\AMEND\26374A.am2. doc forming a second electrode contacting another portion of said graphene layer and laterally offset from a second sidewall of said first metal portion by said lateral distance.
The method of Claim 1, wherein said second metal portion includes an elemental noble metal selected from ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, and gold, and said first metal portion does not include an elemental noble metal.
The method of Claim 1, wherein said forming the stack comprises depositing a first metal layer and a second metal layer as blanket metal layers sequentially, and lithographically patterning the second metal layer and the first metal layer in a subsequent processing step.
The method of Claim 1, wherein said laterally offsetting said sidewalls of the first metal portion relative to said sidewalls of said second metal portion comprises a lateral wet etching processing. 5 I:\IBM\1 05\26374A\A M END\26374A. am2.doc
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor with self-aligned gate
Materials described outside the worked examples.
graphene layer
C
first metal portion
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.6–10 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,753,965Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of a graphene layer. [0012]
FIG. 2 is a vertical cross-sectional view of the exemplary structure after patterning of the graphene layer. [0014]
FIG. 3 is a vertical cross-sectional view of the exemplary structure after deposition of a seed layer. [0016]
FIG. 4 is a vertical cross-sectional view of the exemplary structure after deposition of a blanket gate dielectric layer. [0017]
FIG. 5 is a vertical cross-sectional view of the exemplary structure after formation of a stack of a first metal portion and a second metal portion. [0018]
FIG. 6 is a vertical cross-sectional view of the exemplary structure after lateral recessing of the first metal portion and removal of exposed portions of the …
FIG. 7 is a vertical cross-sectional view of the exemplary structure after removal of the dielectric seed layer. [0020]
FIG. 8 is a vertical cross-sectional view of the exemplary structure after formation of contact metal portions, which constitute a gate electrode, a source …
FIG. 9 is a vertical cross-sectional view of the exemplary structure after formation of a contact level dielectric material layer and conductive contact via …
FIG. 10 is a vertical cross-sectional view of a variation of the exemplary structure. [0025]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a transistor structure comprising: forming a graphene layer directly on an upper surface of an insulating layer, wherein an entirety of a bottom surface of said graphene layer directly contacts said upper surface of said insulator layer; forming a stack of a first metal portion and a second metal portion over said graphene layer, wherein said second metal portion directly contacts said first metal portion and-whe rein peien; and laterally offsetting [[said]] sidewalls of said first metal portion relative to [[said]] sidewalls of said second metal portion by a lateral distance.
The method of Claim 1, further comprising: forming a blanket gate dielectric layer over said graphene layer, wherein said first metal portion is formed on said blanket gate dielectric layer; and patterning said blanket gate dielectric layer employing said second first metal portion as an etch mask, wherein a gate dielectric straddling over said portion of said graphene layer is formed.
The method of Claim 1, wherein said second metal portion overhangs said first metal portion by an overhang distance that is constant around the entirety of sidewalls of said first metal portion.
The method of Claim 1, wherein said second metal portion includes an elemental noble metal selected from ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, and gold, and said first metal portion does not include an elemental noble metal.
The method of Claim 1, further comprising: forming a first electrode contacting a portion of said graphene layer and laterally offset from a first sidewall of said first metal portion by said lateral distance; and 3 I: \IBM\105\26374A\AMEND\26374A.am2. doc forming a second electrode contacting another portion of said graphene layer and laterally offset from a second sidewall of said first metal portion by said lateral distance.
The method of Claim 1, wherein said second metal portion includes an elemental noble metal selected from ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, and gold, and said first metal portion does not include an elemental noble metal.
The method of Claim 1, wherein said forming the stack comprises depositing a first metal layer and a second metal layer as blanket metal layers sequentially, and lithographically patterning the second metal layer and the first metal layer in a subsequent processing step.
The method of Claim 1, wherein said laterally offsetting said sidewalls of the first metal portion relative to said sidewalls of said second metal portion comprises a lateral wet etching processing. 5 I:\IBM\1 05\26374A\A M END\26374A. am2.doc
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor with self-aligned gate
Materials described outside the worked examples.
graphene layer
C
first metal portion
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.6–10 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
second metal portion
blanket gate dielectric layer
dielectric seed layer
adsorbed monolayer of NO₂
NO₂
polymer layer
dielectric oxidized metal (nanoscale metal particles, oxidized)
elemental noble metal (second metal portion)
non-noble metal (first metal portion)
insulating layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
polymer-bound 9-anthracene methanol (polysen)
polyvinyl alcohol (PVA)
| 1–2 nm |
| — |
Thickness | 0.6–20 nm | — |
Thickness | 1–3 nm | — |
Thickness | 5–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | 5–1000 nm | — |
Thickness | 10–200 nm | — |
Thickness | 2–100 nm | — |
Thickness | 3–30 nm | — |
GRAPHENE-BASED NON-VOLATILE MEMORY
second metal portion
blanket gate dielectric layer
dielectric seed layer
adsorbed monolayer of NO₂
NO₂
polymer layer
dielectric oxidized metal (nanoscale metal particles, oxidized)
elemental noble metal (second metal portion)
non-noble metal (first metal portion)
insulating layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
polymer-bound 9-anthracene methanol (polysen)
polyvinyl alcohol (PVA)
| 1–2 nm |
| — |
Thickness | 0.6–20 nm | — |
Thickness | 1–3 nm | — |
Thickness | 5–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | 5–1000 nm | — |
Thickness | 10–200 nm | — |
Thickness | 2–100 nm | — |
Thickness | 3–30 nm | — |
GRAPHENE-BASED NON-VOLATILE MEMORY
second metal portion
blanket gate dielectric layer
dielectric seed layer
adsorbed monolayer of NO₂
NO₂
polymer layer
dielectric oxidized metal (nanoscale metal particles, oxidized)
elemental noble metal (second metal portion)
non-noble metal (first metal portion)
insulating layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
polymer-bound 9-anthracene methanol (polysen)
polyvinyl alcohol (PVA)
| 1–2 nm |
| — |
Thickness | 0.6–20 nm | — |
Thickness | 1–3 nm | — |
Thickness | 5–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | 5–1000 nm | — |
Thickness | 10–200 nm | — |
Thickness | 2–100 nm | — |
Thickness | 3–30 nm | — |
GRAPHENE-BASED NON-VOLATILE MEMORY
second metal portion
blanket gate dielectric layer
dielectric seed layer
adsorbed monolayer of NO₂
NO₂
polymer layer
dielectric oxidized metal (nanoscale metal particles, oxidized)
elemental noble metal (second metal portion)
non-noble metal (first metal portion)
insulating layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
polymer-bound 9-anthracene methanol (polysen)
polyvinyl alcohol (PVA)
| 1–2 nm |
| — |
Thickness | 0.6–20 nm | — |
Thickness | 1–3 nm | — |
Thickness | 5–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | 5–1000 nm | — |
Thickness | 10–200 nm | — |
Thickness | 2–100 nm | — |
Thickness | 3–30 nm | — |
GRAPHENE-BASED NON-VOLATILE MEMORY