Patent
US 9,741,859SEMICONDUCTOR DEVICE WITH GRAPHENE LAYER AS CHANNEL
Yasunori TATENO
US
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Patent
Atlas literature
Patent
US 9,741,859Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (F ET), comprising: a substrate; a graphene layer provided on the substrate; a gate insulating film provided on the graphene la y er: a source electrode and a drain electrode each provided [[on]] in contact with the graphene layer; and a first gate electrode and a second gate electrode provided on the g r-aphefe4ayer gate insulating film, the first gate electrode being disposed closer to the source electrode, the second gate electrode being disposed closer to the drain electrode, and an intermediate electrode provided between the first gate electrode and the second gate electrode and in contact with the graphene la y er, a substance of the intermediate electrode, the source electrode and the drain electrode being identical.
The FET of claim 1, wherein the second gate electrode receives a reference bias higher than a gate bias supplied to the first gate electrode.
The FET of claim 1, furt her-emprising a wherein the gate insulating film includes iieluding an aluminum oxide 1-ayer film.
The FET of claim 1, wherein the graphene layer has thickness of 0.35 to 0.7 nm.
The FET of claim 1, wherein the substrate is made of SiC.
canceled
A method to produce a field effect transistor (FET) having a graphene layer as a channel layer, comprising steps of. withdrawn
The method of claim 11, wherein the step of thermally treating the substrate includes a step of exposing the substrate in a temperature of 1600 0 C for one (1) minute. withdrawn
The method of claim 11, wherein the step of forming Al includes a step of depositing aluminum on the graphene layer by a thickness of 5 nm. withdrawn
The method of claim 11, 5 Application No. 14/844,996 Docket No.: 125786.390426 Reply to Office A ct ion of wherein the step of oxidizing Al includes a step of exposing the substrate covered with Al to an air for 24 hours. withdrawn
The method of claim 11, further including a step of forming a silicon oxide (Si O) layer by a chemical vapor deposition technique after the step of oxidizing Al but before the step of forming the first gate electrode and the second gate electrode. withdrawn
The method of claim 11, further including a step of exposing the substrate with the first gate electrode and the second gate electrode to an oxide plasma after the step of forming the first and second gate electrodes but before the step of forming the source, drain, and intermediate electrodes. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (FET) with dual gate and intermediate electrode
Materials described outside the worked examples.
graphene
C
aluminum oxide
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness (claimed range) | 0.35–0.7 nm | C |
aluminum oxide film thickness (claimed) | 5 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,741,859Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (F ET), comprising: a substrate; a graphene layer provided on the substrate; a gate insulating film provided on the graphene la y er: a source electrode and a drain electrode each provided [[on]] in contact with the graphene layer; and a first gate electrode and a second gate electrode provided on the g r-aphefe4ayer gate insulating film, the first gate electrode being disposed closer to the source electrode, the second gate electrode being disposed closer to the drain electrode, and an intermediate electrode provided between the first gate electrode and the second gate electrode and in contact with the graphene la y er, a substance of the intermediate electrode, the source electrode and the drain electrode being identical.
The FET of claim 1, wherein the second gate electrode receives a reference bias higher than a gate bias supplied to the first gate electrode.
The FET of claim 1, furt her-emprising a wherein the gate insulating film includes iieluding an aluminum oxide 1-ayer film.
The FET of claim 1, wherein the graphene layer has thickness of 0.35 to 0.7 nm.
The FET of claim 1, wherein the substrate is made of SiC.
canceled
A method to produce a field effect transistor (FET) having a graphene layer as a channel layer, comprising steps of. withdrawn
The method of claim 11, wherein the step of thermally treating the substrate includes a step of exposing the substrate in a temperature of 1600 0 C for one (1) minute. withdrawn
The method of claim 11, wherein the step of forming Al includes a step of depositing aluminum on the graphene layer by a thickness of 5 nm. withdrawn
The method of claim 11, 5 Application No. 14/844,996 Docket No.: 125786.390426 Reply to Office A ct ion of wherein the step of oxidizing Al includes a step of exposing the substrate covered with Al to an air for 24 hours. withdrawn
The method of claim 11, further including a step of forming a silicon oxide (Si O) layer by a chemical vapor deposition technique after the step of oxidizing Al but before the step of forming the first gate electrode and the second gate electrode. withdrawn
The method of claim 11, further including a step of exposing the substrate with the first gate electrode and the second gate electrode to an oxide plasma after the step of forming the first and second gate electrodes but before the step of forming the source, drain, and intermediate electrodes. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (FET) with dual gate and intermediate electrode
Materials described outside the worked examples.
graphene
C
aluminum oxide
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness (claimed range) | 0.35–0.7 nm | C |
aluminum oxide film thickness (claimed) | 5 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,741,859Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (F ET), comprising: a substrate; a graphene layer provided on the substrate; a gate insulating film provided on the graphene la y er: a source electrode and a drain electrode each provided [[on]] in contact with the graphene layer; and a first gate electrode and a second gate electrode provided on the g r-aphefe4ayer gate insulating film, the first gate electrode being disposed closer to the source electrode, the second gate electrode being disposed closer to the drain electrode, and an intermediate electrode provided between the first gate electrode and the second gate electrode and in contact with the graphene la y er, a substance of the intermediate electrode, the source electrode and the drain electrode being identical.
The FET of claim 1, wherein the second gate electrode receives a reference bias higher than a gate bias supplied to the first gate electrode.
The FET of claim 1, furt her-emprising a wherein the gate insulating film includes iieluding an aluminum oxide 1-ayer film.
The FET of claim 1, wherein the graphene layer has thickness of 0.35 to 0.7 nm.
The FET of claim 1, wherein the substrate is made of SiC.
canceled
A method to produce a field effect transistor (FET) having a graphene layer as a channel layer, comprising steps of. withdrawn
The method of claim 11, wherein the step of thermally treating the substrate includes a step of exposing the substrate in a temperature of 1600 0 C for one (1) minute. withdrawn
The method of claim 11, wherein the step of forming Al includes a step of depositing aluminum on the graphene layer by a thickness of 5 nm. withdrawn
The method of claim 11, 5 Application No. 14/844,996 Docket No.: 125786.390426 Reply to Office A ct ion of wherein the step of oxidizing Al includes a step of exposing the substrate covered with Al to an air for 24 hours. withdrawn
The method of claim 11, further including a step of forming a silicon oxide (Si O) layer by a chemical vapor deposition technique after the step of oxidizing Al but before the step of forming the first gate electrode and the second gate electrode. withdrawn
The method of claim 11, further including a step of exposing the substrate with the first gate electrode and the second gate electrode to an oxide plasma after the step of forming the first and second gate electrodes but before the step of forming the source, drain, and intermediate electrodes. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (FET) with dual gate and intermediate electrode
Materials described outside the worked examples.
graphene
C
aluminum oxide
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness (claimed range) | 0.35–0.7 nm | C |
aluminum oxide film thickness (claimed) | 5 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,741,859Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (F ET), comprising: a substrate; a graphene layer provided on the substrate; a gate insulating film provided on the graphene la y er: a source electrode and a drain electrode each provided [[on]] in contact with the graphene layer; and a first gate electrode and a second gate electrode provided on the g r-aphefe4ayer gate insulating film, the first gate electrode being disposed closer to the source electrode, the second gate electrode being disposed closer to the drain electrode, and an intermediate electrode provided between the first gate electrode and the second gate electrode and in contact with the graphene la y er, a substance of the intermediate electrode, the source electrode and the drain electrode being identical.
The FET of claim 1, wherein the second gate electrode receives a reference bias higher than a gate bias supplied to the first gate electrode.
The FET of claim 1, furt her-emprising a wherein the gate insulating film includes iieluding an aluminum oxide 1-ayer film.
The FET of claim 1, wherein the graphene layer has thickness of 0.35 to 0.7 nm.
The FET of claim 1, wherein the substrate is made of SiC.
canceled
A method to produce a field effect transistor (FET) having a graphene layer as a channel layer, comprising steps of. withdrawn
The method of claim 11, wherein the step of thermally treating the substrate includes a step of exposing the substrate in a temperature of 1600 0 C for one (1) minute. withdrawn
The method of claim 11, wherein the step of forming Al includes a step of depositing aluminum on the graphene layer by a thickness of 5 nm. withdrawn
The method of claim 11, 5 Application No. 14/844,996 Docket No.: 125786.390426 Reply to Office A ct ion of wherein the step of oxidizing Al includes a step of exposing the substrate covered with Al to an air for 24 hours. withdrawn
The method of claim 11, further including a step of forming a silicon oxide (Si O) layer by a chemical vapor deposition technique after the step of oxidizing Al but before the step of forming the first gate electrode and the second gate electrode. withdrawn
The method of claim 11, further including a step of exposing the substrate with the first gate electrode and the second gate electrode to an oxide plasma after the step of forming the first and second gate electrodes but before the step of forming the source, drain, and intermediate electrodes. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor (FET) with dual gate and intermediate electrode
Materials described outside the worked examples.
graphene
C
aluminum oxide
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness (claimed range) | 0.35–0.7 nm | C |
aluminum oxide film thickness (claimed) | 5 nm |
Related documents with shared materials, methods, properties, or citations.
silicon oxide
SiO₂
silicon carbide
SiC
aluminum
Al
Al₂O₃ |
silicon oxide film thickness (claimed) | 30 nm | SiO₂ |
graphene layer thickness in comparable example description | 0.35 nm | C |
Voltage | 0–5 V | — |
silicon oxide
SiO₂
silicon carbide
SiC
aluminum
Al
Al₂O₃ |
silicon oxide film thickness (claimed) | 30 nm | SiO₂ |
graphene layer thickness in comparable example description | 0.35 nm | C |
Voltage | 0–5 V | — |
silicon oxide
SiO₂
silicon carbide
SiC
aluminum
Al
Al₂O₃ |
silicon oxide film thickness (claimed) | 30 nm | SiO₂ |
graphene layer thickness in comparable example description | 0.35 nm | C |
Voltage | 0–5 V | — |
silicon oxide
SiO₂
silicon carbide
SiC
aluminum
Al
Al₂O₃ |
silicon oxide film thickness (claimed) | 30 nm | SiO₂ |
graphene layer thickness in comparable example description | 0.35 nm | C |
Voltage | 0–5 V | — |