Patent
US 8,168,964Semiconductor device using field effect with semiconductor graphene channel and metal graphene electrodes
Hidefumi Hiura
US
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Patent
Atlas literature
Patent
US 8,168,964Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device using a field effect, comprising: a channel layer formed of semiconductor graphene; electrode layers formed of metal graphene for a source, a drain, and a gate, the electrode layers serving as interconnections; and a gate insulating layer for insulating the channel layer and the gate electrode layer from each other, wherein the channel layer and the electrode layers are located on the s ame plane, wherein, the semiconductor graphene has an armchair edge with a width of 20 nm or less while the metal graphene has a zi g zag edge with a width of 20 nm or less.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type or n-type conduction by doping.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type conduction by substituting one element of boron, aluminum, gallium, and indium, or any combination thereof for part of 2 AMENDMENT UNDER 37 C.F.R. § 1.111 Attorney Docket No.: Q 1 14774 Appln. No.: 12/529,50 1 constituent carbon, or a graphene provided with n-type conduction by substituting one element of nitrogen, phosphorus, arsenic, and antimony, or any combination thereof for part of constituent carbon.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type conduction by arranging an acceptor on its surface, or a graphene provided with n-type conduction by arranging a donor on its surface.
The semiconductor device as recited in claim 1, wherein: the semiconductor device comprises an inverter into which p-type and n-type channels are combined in a complementary manner.
The semiconductor device as recited in claim 1, wherein: 3 AMENDMENT UNDER 37 C.F.R. § 1.111 Atto rney Docket No.: Q₁₁₄₇₇₄ Appln. No.: 12/529,501 the semiconductor device comprises a memory cell or a logic circuit including as a fundamental circuit an inverter into which p-type and n-type channels are combined in a complementary manner.
canceled
A method of manufacturing a semiconductor device, comprising: producing a graphene on a substrate; forming the graphene into a desired device structure through lithography and etching; forming an edge structure of the graphene into a zigzag edge or an armchair edge through oxidation reaction or reduction reaction; doping the semiconductor graphene; and depositing an insulating film. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the producing of the graphene on the substrate comprises a graphene formation method including pyrolysis on a silicon carbide (SiC) substrate. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the producing of the graphene on the substrate comprises a graphene formation method including processing a surface of a highly-oriented pyrolytic graphite (HOPG) and dispersing graphenes on the substrate. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the doping of the semiconductor graphene comprises p-type lattice-substitution doping of substituting one element of boron, aluminum, gallium, and indium, or any combination thereof for part of constituent carbon in the semiconductor graphene, or n-type lattice- substitution doping of substituting one element of nitrogen, phosphorus, arsenic, and antimony, or any combination thereof for part of constituent carbon. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the doping of the semiconductor graphene comprises charge-transfer doping of arranging an acceptor on a surface of the semiconductor graphene to provide p-type conduction, or charge-transfer doping of arranging a donor on a surface of the semiconductor graphene to provide n-type conduction. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor
complementary graphene inverter
Materials described outside the worked examples.
semiconductor graphene
C
gate insulating layer oxide
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–100 nm | — |
Duration | 10–600 s |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,168,964Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device using a field effect, comprising: a channel layer formed of semiconductor graphene; electrode layers formed of metal graphene for a source, a drain, and a gate, the electrode layers serving as interconnections; and a gate insulating layer for insulating the channel layer and the gate electrode layer from each other, wherein the channel layer and the electrode layers are located on the s ame plane, wherein, the semiconductor graphene has an armchair edge with a width of 20 nm or less while the metal graphene has a zi g zag edge with a width of 20 nm or less.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type or n-type conduction by doping.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type conduction by substituting one element of boron, aluminum, gallium, and indium, or any combination thereof for part of 2 AMENDMENT UNDER 37 C.F.R. § 1.111 Attorney Docket No.: Q 1 14774 Appln. No.: 12/529,50 1 constituent carbon, or a graphene provided with n-type conduction by substituting one element of nitrogen, phosphorus, arsenic, and antimony, or any combination thereof for part of constituent carbon.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type conduction by arranging an acceptor on its surface, or a graphene provided with n-type conduction by arranging a donor on its surface.
The semiconductor device as recited in claim 1, wherein: the semiconductor device comprises an inverter into which p-type and n-type channels are combined in a complementary manner.
The semiconductor device as recited in claim 1, wherein: 3 AMENDMENT UNDER 37 C.F.R. § 1.111 Atto rney Docket No.: Q₁₁₄₇₇₄ Appln. No.: 12/529,501 the semiconductor device comprises a memory cell or a logic circuit including as a fundamental circuit an inverter into which p-type and n-type channels are combined in a complementary manner.
canceled
A method of manufacturing a semiconductor device, comprising: producing a graphene on a substrate; forming the graphene into a desired device structure through lithography and etching; forming an edge structure of the graphene into a zigzag edge or an armchair edge through oxidation reaction or reduction reaction; doping the semiconductor graphene; and depositing an insulating film. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the producing of the graphene on the substrate comprises a graphene formation method including pyrolysis on a silicon carbide (SiC) substrate. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the producing of the graphene on the substrate comprises a graphene formation method including processing a surface of a highly-oriented pyrolytic graphite (HOPG) and dispersing graphenes on the substrate. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the doping of the semiconductor graphene comprises p-type lattice-substitution doping of substituting one element of boron, aluminum, gallium, and indium, or any combination thereof for part of constituent carbon in the semiconductor graphene, or n-type lattice- substitution doping of substituting one element of nitrogen, phosphorus, arsenic, and antimony, or any combination thereof for part of constituent carbon. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the doping of the semiconductor graphene comprises charge-transfer doping of arranging an acceptor on a surface of the semiconductor graphene to provide p-type conduction, or charge-transfer doping of arranging a donor on a surface of the semiconductor graphene to provide n-type conduction. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor
complementary graphene inverter
Materials described outside the worked examples.
semiconductor graphene
C
gate insulating layer oxide
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–100 nm | — |
Duration | 10–600 s |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,168,964Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device using a field effect, comprising: a channel layer formed of semiconductor graphene; electrode layers formed of metal graphene for a source, a drain, and a gate, the electrode layers serving as interconnections; and a gate insulating layer for insulating the channel layer and the gate electrode layer from each other, wherein the channel layer and the electrode layers are located on the s ame plane, wherein, the semiconductor graphene has an armchair edge with a width of 20 nm or less while the metal graphene has a zi g zag edge with a width of 20 nm or less.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type or n-type conduction by doping.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type conduction by substituting one element of boron, aluminum, gallium, and indium, or any combination thereof for part of 2 AMENDMENT UNDER 37 C.F.R. § 1.111 Attorney Docket No.: Q 1 14774 Appln. No.: 12/529,50 1 constituent carbon, or a graphene provided with n-type conduction by substituting one element of nitrogen, phosphorus, arsenic, and antimony, or any combination thereof for part of constituent carbon.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type conduction by arranging an acceptor on its surface, or a graphene provided with n-type conduction by arranging a donor on its surface.
The semiconductor device as recited in claim 1, wherein: the semiconductor device comprises an inverter into which p-type and n-type channels are combined in a complementary manner.
The semiconductor device as recited in claim 1, wherein: 3 AMENDMENT UNDER 37 C.F.R. § 1.111 Atto rney Docket No.: Q₁₁₄₇₇₄ Appln. No.: 12/529,501 the semiconductor device comprises a memory cell or a logic circuit including as a fundamental circuit an inverter into which p-type and n-type channels are combined in a complementary manner.
canceled
A method of manufacturing a semiconductor device, comprising: producing a graphene on a substrate; forming the graphene into a desired device structure through lithography and etching; forming an edge structure of the graphene into a zigzag edge or an armchair edge through oxidation reaction or reduction reaction; doping the semiconductor graphene; and depositing an insulating film. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the producing of the graphene on the substrate comprises a graphene formation method including pyrolysis on a silicon carbide (SiC) substrate. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the producing of the graphene on the substrate comprises a graphene formation method including processing a surface of a highly-oriented pyrolytic graphite (HOPG) and dispersing graphenes on the substrate. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the doping of the semiconductor graphene comprises p-type lattice-substitution doping of substituting one element of boron, aluminum, gallium, and indium, or any combination thereof for part of constituent carbon in the semiconductor graphene, or n-type lattice- substitution doping of substituting one element of nitrogen, phosphorus, arsenic, and antimony, or any combination thereof for part of constituent carbon. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the doping of the semiconductor graphene comprises charge-transfer doping of arranging an acceptor on a surface of the semiconductor graphene to provide p-type conduction, or charge-transfer doping of arranging a donor on a surface of the semiconductor graphene to provide n-type conduction. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor
complementary graphene inverter
Materials described outside the worked examples.
semiconductor graphene
C
gate insulating layer oxide
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–100 nm | — |
Duration | 10–600 s |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,168,964Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device using a field effect, comprising: a channel layer formed of semiconductor graphene; electrode layers formed of metal graphene for a source, a drain, and a gate, the electrode layers serving as interconnections; and a gate insulating layer for insulating the channel layer and the gate electrode layer from each other, wherein the channel layer and the electrode layers are located on the s ame plane, wherein, the semiconductor graphene has an armchair edge with a width of 20 nm or less while the metal graphene has a zi g zag edge with a width of 20 nm or less.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type or n-type conduction by doping.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type conduction by substituting one element of boron, aluminum, gallium, and indium, or any combination thereof for part of 2 AMENDMENT UNDER 37 C.F.R. § 1.111 Attorney Docket No.: Q 1 14774 Appln. No.: 12/529,50 1 constituent carbon, or a graphene provided with n-type conduction by substituting one element of nitrogen, phosphorus, arsenic, and antimony, or any combination thereof for part of constituent carbon.
The semiconductor device as recited in claim 1, wherein: the channel comprises a graphene provided with p-type conduction by arranging an acceptor on its surface, or a graphene provided with n-type conduction by arranging a donor on its surface.
The semiconductor device as recited in claim 1, wherein: the semiconductor device comprises an inverter into which p-type and n-type channels are combined in a complementary manner.
The semiconductor device as recited in claim 1, wherein: 3 AMENDMENT UNDER 37 C.F.R. § 1.111 Atto rney Docket No.: Q₁₁₄₇₇₄ Appln. No.: 12/529,501 the semiconductor device comprises a memory cell or a logic circuit including as a fundamental circuit an inverter into which p-type and n-type channels are combined in a complementary manner.
canceled
A method of manufacturing a semiconductor device, comprising: producing a graphene on a substrate; forming the graphene into a desired device structure through lithography and etching; forming an edge structure of the graphene into a zigzag edge or an armchair edge through oxidation reaction or reduction reaction; doping the semiconductor graphene; and depositing an insulating film. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the producing of the graphene on the substrate comprises a graphene formation method including pyrolysis on a silicon carbide (SiC) substrate. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the producing of the graphene on the substrate comprises a graphene formation method including processing a surface of a highly-oriented pyrolytic graphite (HOPG) and dispersing graphenes on the substrate. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the doping of the semiconductor graphene comprises p-type lattice-substitution doping of substituting one element of boron, aluminum, gallium, and indium, or any combination thereof for part of constituent carbon in the semiconductor graphene, or n-type lattice- substitution doping of substituting one element of nitrogen, phosphorus, arsenic, and antimony, or any combination thereof for part of constituent carbon. withdrawn
The method of manufacturing a semiconductor device as recited in claim 10, wherein: the doping of the semiconductor graphene comprises charge-transfer doping of arranging an acceptor on a surface of the semiconductor graphene to provide p-type conduction, or charge-transfer doping of arranging a donor on a surface of the semiconductor graphene to provide n-type conduction. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor
complementary graphene inverter
Materials described outside the worked examples.
semiconductor graphene
C
gate insulating layer oxide
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–100 nm | — |
Duration | 10–600 s |
Related documents with shared materials, methods, properties, or citations.
p-type dopant (B, Al, Ga, In)
n-type dopant (N, P, As, Sb)
silicon carbide substrate
SiC
| — |
— | ≥ 2.3 eV | — |
Thickness | ≥ 1 nm | — |
p-type dopant (B, Al, Ga, In)
n-type dopant (N, P, As, Sb)
silicon carbide substrate
SiC
| — |
— | ≥ 2.3 eV | — |
Thickness | ≥ 1 nm | — |
p-type dopant (B, Al, Ga, In)
n-type dopant (N, P, As, Sb)
silicon carbide substrate
SiC
| — |
— | ≥ 2.3 eV | — |
Thickness | ≥ 1 nm | — |
p-type dopant (B, Al, Ga, In)
n-type dopant (N, P, As, Sb)
silicon carbide substrate
SiC
| — |
— | ≥ 2.3 eV | — |
Thickness | ≥ 1 nm | — |