Patent
US 9,525,076MEMORY DEVICE USING GRAPHENE AS CHARGE-TRAP LAYER AND METHOD OF OPERATING THE SAME
Jae-ho LEE
US
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Atlas literature
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US 9,525,076Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; [0021]
FIG. 2 is a plan view of the memory device illustrated in
FIGS. 3A through 3G are band diagrams between a substrate and a graphene layer in order to describe the function of the memory device illustrated in
FIG. 4 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; 3 Atty. Dkt. No. 2557S 1 …
FIG. 5 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; and [0026]
FIG. 6 is a magnified view of a portion of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene memory comprising: a conductive semiconductor substrate; a source and a drain spaced apart from each other on a surface of the conductive semiconductor substrate; a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain when viewed from a plan view, the graphene layer being flat; a conductive layer directly on the graphene layer, the conductive layer facing the conductive semiconductor substrate with the graphene layer therebetween; and a gate electrode above the conductive layer, wherein a Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge- trap layer for storing charges, wherein the gate electrode covers the graphene layer and overlaps a portion of the conductive semiconductor substrate exposed by a periphery of the graphene layer when viewed from the plan view, and wherein the graphene layer includes one of at least one hole and at least one slit passing through the graphene layer, and wherein the conductive la y er includes one of p ol y silicon, aluminum (Al). g old (Au), beryllium (Be), bismuth (Bi), cobalt (Co), co p per (Cu), hafnium (Hf). indium (In). manganese (Mn), mol y bdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tantalum (Ta), tellurium (Te). titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr). Page 2 Application No.: 13/960,256 Attorney Docket No.: 2557 SI -001995-US
The graphene memory of claim 1, wherein the conductive semiconductor substrate includes one of silicon, ge rm anium, silicon-germanium, and a Group 11- V semiconductor.
The graphene memory of claim 1, wherein the graphene layer includes one to four layers of graphene.
The graphene memory of claim 1, wherein the conductive layer includes one of at least one hole and at least one slit passing through the conductive layer.
The graphene memory of claim 1, wherein a size of the Schottky barrier varies according to a voltage applied to the gate electrode.
A method of operating the graphene memory of claim 1, the method comprising: removing storage charges from the graphene layer by applying a drain voltage to the drain and applying a first gate voltage to the gate electrode; storing the storage charges in the graphene layer by applying a second gate voltage to the gate electrode, the second gate voltage having an opposite polarity to the first gate voltage; and applying a third gate voltage to the gate electrode, the third gate voltage having the same polarity as the second gate voltage, and measuring a drain current flowing through the dra in. Page 3 Application No.: 13/960,256 Attorney Docket No.: 2557S I -001995-US withdrawn
4-6.. canceled
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene memory (charge-trap non-volatile memory)
Materials described outside the worked examples.
graphene layer
conductive layer
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 3A through 3G are band diagrams between a substrate and a graphene layer in order to describe the function of the memory device illustrated in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer width | 20–150 nm | graphene layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,525,076Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; [0021]
FIG. 2 is a plan view of the memory device illustrated in
FIGS. 3A through 3G are band diagrams between a substrate and a graphene layer in order to describe the function of the memory device illustrated in
FIG. 4 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; 3 Atty. Dkt. No. 2557S 1 …
FIG. 5 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; and [0026]
FIG. 6 is a magnified view of a portion of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene memory comprising: a conductive semiconductor substrate; a source and a drain spaced apart from each other on a surface of the conductive semiconductor substrate; a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain when viewed from a plan view, the graphene layer being flat; a conductive layer directly on the graphene layer, the conductive layer facing the conductive semiconductor substrate with the graphene layer therebetween; and a gate electrode above the conductive layer, wherein a Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge- trap layer for storing charges, wherein the gate electrode covers the graphene layer and overlaps a portion of the conductive semiconductor substrate exposed by a periphery of the graphene layer when viewed from the plan view, and wherein the graphene layer includes one of at least one hole and at least one slit passing through the graphene layer, and wherein the conductive la y er includes one of p ol y silicon, aluminum (Al). g old (Au), beryllium (Be), bismuth (Bi), cobalt (Co), co p per (Cu), hafnium (Hf). indium (In). manganese (Mn), mol y bdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tantalum (Ta), tellurium (Te). titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr). Page 2 Application No.: 13/960,256 Attorney Docket No.: 2557 SI -001995-US
The graphene memory of claim 1, wherein the conductive semiconductor substrate includes one of silicon, ge rm anium, silicon-germanium, and a Group 11- V semiconductor.
The graphene memory of claim 1, wherein the graphene layer includes one to four layers of graphene.
The graphene memory of claim 1, wherein the conductive layer includes one of at least one hole and at least one slit passing through the conductive layer.
The graphene memory of claim 1, wherein a size of the Schottky barrier varies according to a voltage applied to the gate electrode.
A method of operating the graphene memory of claim 1, the method comprising: removing storage charges from the graphene layer by applying a drain voltage to the drain and applying a first gate voltage to the gate electrode; storing the storage charges in the graphene layer by applying a second gate voltage to the gate electrode, the second gate voltage having an opposite polarity to the first gate voltage; and applying a third gate voltage to the gate electrode, the third gate voltage having the same polarity as the second gate voltage, and measuring a drain current flowing through the dra in. Page 3 Application No.: 13/960,256 Attorney Docket No.: 2557S I -001995-US withdrawn
4-6.. canceled
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene memory (charge-trap non-volatile memory)
Materials described outside the worked examples.
graphene layer
conductive layer
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 3A through 3G are band diagrams between a substrate and a graphene layer in order to describe the function of the memory device illustrated in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer width | 20–150 nm | graphene layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,525,076Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; [0021]
FIG. 2 is a plan view of the memory device illustrated in
FIGS. 3A through 3G are band diagrams between a substrate and a graphene layer in order to describe the function of the memory device illustrated in
FIG. 4 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; 3 Atty. Dkt. No. 2557S 1 …
FIG. 5 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; and [0026]
FIG. 6 is a magnified view of a portion of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene memory comprising: a conductive semiconductor substrate; a source and a drain spaced apart from each other on a surface of the conductive semiconductor substrate; a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain when viewed from a plan view, the graphene layer being flat; a conductive layer directly on the graphene layer, the conductive layer facing the conductive semiconductor substrate with the graphene layer therebetween; and a gate electrode above the conductive layer, wherein a Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge- trap layer for storing charges, wherein the gate electrode covers the graphene layer and overlaps a portion of the conductive semiconductor substrate exposed by a periphery of the graphene layer when viewed from the plan view, and wherein the graphene layer includes one of at least one hole and at least one slit passing through the graphene layer, and wherein the conductive la y er includes one of p ol y silicon, aluminum (Al). g old (Au), beryllium (Be), bismuth (Bi), cobalt (Co), co p per (Cu), hafnium (Hf). indium (In). manganese (Mn), mol y bdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tantalum (Ta), tellurium (Te). titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr). Page 2 Application No.: 13/960,256 Attorney Docket No.: 2557 SI -001995-US
The graphene memory of claim 1, wherein the conductive semiconductor substrate includes one of silicon, ge rm anium, silicon-germanium, and a Group 11- V semiconductor.
The graphene memory of claim 1, wherein the graphene layer includes one to four layers of graphene.
The graphene memory of claim 1, wherein the conductive layer includes one of at least one hole and at least one slit passing through the conductive layer.
The graphene memory of claim 1, wherein a size of the Schottky barrier varies according to a voltage applied to the gate electrode.
A method of operating the graphene memory of claim 1, the method comprising: removing storage charges from the graphene layer by applying a drain voltage to the drain and applying a first gate voltage to the gate electrode; storing the storage charges in the graphene layer by applying a second gate voltage to the gate electrode, the second gate voltage having an opposite polarity to the first gate voltage; and applying a third gate voltage to the gate electrode, the third gate voltage having the same polarity as the second gate voltage, and measuring a drain current flowing through the dra in. Page 3 Application No.: 13/960,256 Attorney Docket No.: 2557S I -001995-US withdrawn
4-6.. canceled
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene memory (charge-trap non-volatile memory)
Materials described outside the worked examples.
graphene layer
conductive layer
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 3A through 3G are band diagrams between a substrate and a graphene layer in order to describe the function of the memory device illustrated in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer width | 20–150 nm | graphene layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,525,076Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; [0021]
FIG. 2 is a plan view of the memory device illustrated in
FIGS. 3A through 3G are band diagrams between a substrate and a graphene layer in order to describe the function of the memory device illustrated in
FIG. 4 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; 3 Atty. Dkt. No. 2557S 1 …
FIG. 5 is a cross-sectional view of a memory device using graphene as a charge-trap layer, according to example embodiments; and [0026]
FIG. 6 is a magnified view of a portion of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene memory comprising: a conductive semiconductor substrate; a source and a drain spaced apart from each other on a surface of the conductive semiconductor substrate; a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain when viewed from a plan view, the graphene layer being flat; a conductive layer directly on the graphene layer, the conductive layer facing the conductive semiconductor substrate with the graphene layer therebetween; and a gate electrode above the conductive layer, wherein a Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge- trap layer for storing charges, wherein the gate electrode covers the graphene layer and overlaps a portion of the conductive semiconductor substrate exposed by a periphery of the graphene layer when viewed from the plan view, and wherein the graphene layer includes one of at least one hole and at least one slit passing through the graphene layer, and wherein the conductive la y er includes one of p ol y silicon, aluminum (Al). g old (Au), beryllium (Be), bismuth (Bi), cobalt (Co), co p per (Cu), hafnium (Hf). indium (In). manganese (Mn), mol y bdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tantalum (Ta), tellurium (Te). titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr). Page 2 Application No.: 13/960,256 Attorney Docket No.: 2557 SI -001995-US
The graphene memory of claim 1, wherein the conductive semiconductor substrate includes one of silicon, ge rm anium, silicon-germanium, and a Group 11- V semiconductor.
The graphene memory of claim 1, wherein the graphene layer includes one to four layers of graphene.
The graphene memory of claim 1, wherein the conductive layer includes one of at least one hole and at least one slit passing through the conductive layer.
The graphene memory of claim 1, wherein a size of the Schottky barrier varies according to a voltage applied to the gate electrode.
A method of operating the graphene memory of claim 1, the method comprising: removing storage charges from the graphene layer by applying a drain voltage to the drain and applying a first gate voltage to the gate electrode; storing the storage charges in the graphene layer by applying a second gate voltage to the gate electrode, the second gate voltage having an opposite polarity to the first gate voltage; and applying a third gate voltage to the gate electrode, the third gate voltage having the same polarity as the second gate voltage, and measuring a drain current flowing through the dra in. Page 3 Application No.: 13/960,256 Attorney Docket No.: 2557S I -001995-US withdrawn
4-6.. canceled
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene memory (charge-trap non-volatile memory)
Materials described outside the worked examples.
graphene layer
conductive layer
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 3A through 3G are band diagrams between a substrate and a graphene layer in order to describe the function of the memory device illustrated in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer width | 20–150 nm | graphene layer |
Related documents with shared materials, methods, properties, or citations.
gate electrode
conductive semiconductor substrate
silicon oxide
SiO₂
alumina
Al₂O₃
hafnium oxide
HfO₂
gate electrode
conductive semiconductor substrate
silicon oxide
SiO₂
alumina
Al₂O₃
hafnium oxide
HfO₂
gate electrode
conductive semiconductor substrate
silicon oxide
SiO₂
alumina
Al₂O₃
hafnium oxide
HfO₂
gate electrode
conductive semiconductor substrate
silicon oxide
SiO₂
alumina
Al₂O₃
hafnium oxide
HfO₂