Patent
US 8,987,740A Graphene Photodetector
Phaedon Avouris
US
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Patent
Atlas literature
Patent
US 8,987,740Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of trenches in an insulator layer according to an embodiment of the present …
FIG. 2 is a vertical cross-sectional view of the exemplary structure after formation of buried electrodes according to an embodiment of the present invention. …
FIG. 3 is a vertical cross-sectional view of the exemplary structure after placement of a graphene layer on the top surface of the insulator layer according to …
FIG. 4 is a vertical cross-sectional view of the exemplary structure after forming of first upper electrodes and second upper electrodes according to an …
FIG. 5 is a schematic view of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement …
FIG. 6 is a schematic view of a variation of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fo rm ing an electromagnetic radiation detector comprising: forming at least one buried electrode in an insulator layer; forming a graphene layer over said insulator layer; forming at least one p-n junction within said graphene la y er, wherein one of said at least one p-n junction does not overlie, and is laterally offset from a sidewall of, one of said at least one buried ele ctrode; forming at least one first upper electrode, wherein each of said at least one first upper electrode has a pair of sidewalls that overlie a top surface of one of said at least one buried electrode; forming at least one second upper electrode that does not overlie, and is laterally offset from sidewalls of, said at least one buried electrode; and forming a measurement circuitry configured to measure an electrical current between, or an electrical voltage across, said at least one first upper electrode and said at least one second upper electrode.
The method of Claim 1, wherein said at least one buried electrode is formed by: 2 I:\IBM\ 1 05\29714Z\AMEND\29714Z. aml.doc forming at least one trench in said insulator layer; filling said at least one trench with at least one conductive material; and removing portions of said at least one conductive material from above a plane of a top surface of said insulator layer, wherein remaining portions of said at least one conductive material constitute said at least one buried electrode.
The method of Claim 1, wherein said at least one first upper electrode and said at least one second upper electrode are simultaneously formed by a masked directional deposition of a conductive material.
The method of Claim 1, wherein each of said at least one buried electrode includes a pair of sidewalls that extends along a lengthwise direction that is perpendicular to a spacing between one of said at least one first upper electrode and one of said at least one second upper electrode.
The method of Claim 1, wherein one of said at least one first upper electrode has a pair of parallel sidewalls separated by a first width and extending along a lengthwise direction, and one of said at least one second upper electrode has a pair of sidewalls separated by a second width and extending along said lengthwise direction.
The method of Claim 1, wherein said at least one first upper electrode is a plurality of first upper electrodes, said at least one second upper electrode is a plurality of second upper electrodes, and said plurality of first upper electrodes and said plurality of second upper electrodes are interlaced to provide an alternating arrangement of first and second upper electrodes along a horizontal direction.
The method of Claim 1, inducing charge carriers in regions of said graphene layer that overlie said at least one buried electrode by applying an electrical bias to said at least one buried electrode, wherein said charge carriers have a conductivity type that is the opposite of a first conductivity type of said graphene layer as provided said electrical bias.
4 1:\ I BM\ 1 05\29714Z\AMEND\29714Z.aml.doc on said insulator layer prior to application of said electrical bias is performed employing at least one buried electrode relative to said at at least one second upper electrode. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene electromagnetic radiation detector (photodetector)
Materials described outside the worked examples.
graphene
insulator layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a schematic view of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,987,740Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of trenches in an insulator layer according to an embodiment of the present …
FIG. 2 is a vertical cross-sectional view of the exemplary structure after formation of buried electrodes according to an embodiment of the present invention. …
FIG. 3 is a vertical cross-sectional view of the exemplary structure after placement of a graphene layer on the top surface of the insulator layer according to …
FIG. 4 is a vertical cross-sectional view of the exemplary structure after forming of first upper electrodes and second upper electrodes according to an …
FIG. 5 is a schematic view of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement …
FIG. 6 is a schematic view of a variation of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fo rm ing an electromagnetic radiation detector comprising: forming at least one buried electrode in an insulator layer; forming a graphene layer over said insulator layer; forming at least one p-n junction within said graphene la y er, wherein one of said at least one p-n junction does not overlie, and is laterally offset from a sidewall of, one of said at least one buried ele ctrode; forming at least one first upper electrode, wherein each of said at least one first upper electrode has a pair of sidewalls that overlie a top surface of one of said at least one buried electrode; forming at least one second upper electrode that does not overlie, and is laterally offset from sidewalls of, said at least one buried electrode; and forming a measurement circuitry configured to measure an electrical current between, or an electrical voltage across, said at least one first upper electrode and said at least one second upper electrode.
The method of Claim 1, wherein said at least one buried electrode is formed by: 2 I:\IBM\ 1 05\29714Z\AMEND\29714Z. aml.doc forming at least one trench in said insulator layer; filling said at least one trench with at least one conductive material; and removing portions of said at least one conductive material from above a plane of a top surface of said insulator layer, wherein remaining portions of said at least one conductive material constitute said at least one buried electrode.
The method of Claim 1, wherein said at least one first upper electrode and said at least one second upper electrode are simultaneously formed by a masked directional deposition of a conductive material.
The method of Claim 1, wherein each of said at least one buried electrode includes a pair of sidewalls that extends along a lengthwise direction that is perpendicular to a spacing between one of said at least one first upper electrode and one of said at least one second upper electrode.
The method of Claim 1, wherein one of said at least one first upper electrode has a pair of parallel sidewalls separated by a first width and extending along a lengthwise direction, and one of said at least one second upper electrode has a pair of sidewalls separated by a second width and extending along said lengthwise direction.
The method of Claim 1, wherein said at least one first upper electrode is a plurality of first upper electrodes, said at least one second upper electrode is a plurality of second upper electrodes, and said plurality of first upper electrodes and said plurality of second upper electrodes are interlaced to provide an alternating arrangement of first and second upper electrodes along a horizontal direction.
The method of Claim 1, inducing charge carriers in regions of said graphene layer that overlie said at least one buried electrode by applying an electrical bias to said at least one buried electrode, wherein said charge carriers have a conductivity type that is the opposite of a first conductivity type of said graphene layer as provided said electrical bias.
4 1:\ I BM\ 1 05\29714Z\AMEND\29714Z.aml.doc on said insulator layer prior to application of said electrical bias is performed employing at least one buried electrode relative to said at at least one second upper electrode. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene electromagnetic radiation detector (photodetector)
Materials described outside the worked examples.
graphene
insulator layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a schematic view of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,987,740Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of trenches in an insulator layer according to an embodiment of the present …
FIG. 2 is a vertical cross-sectional view of the exemplary structure after formation of buried electrodes according to an embodiment of the present invention. …
FIG. 3 is a vertical cross-sectional view of the exemplary structure after placement of a graphene layer on the top surface of the insulator layer according to …
FIG. 4 is a vertical cross-sectional view of the exemplary structure after forming of first upper electrodes and second upper electrodes according to an …
FIG. 5 is a schematic view of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement …
FIG. 6 is a schematic view of a variation of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fo rm ing an electromagnetic radiation detector comprising: forming at least one buried electrode in an insulator layer; forming a graphene layer over said insulator layer; forming at least one p-n junction within said graphene la y er, wherein one of said at least one p-n junction does not overlie, and is laterally offset from a sidewall of, one of said at least one buried ele ctrode; forming at least one first upper electrode, wherein each of said at least one first upper electrode has a pair of sidewalls that overlie a top surface of one of said at least one buried electrode; forming at least one second upper electrode that does not overlie, and is laterally offset from sidewalls of, said at least one buried electrode; and forming a measurement circuitry configured to measure an electrical current between, or an electrical voltage across, said at least one first upper electrode and said at least one second upper electrode.
The method of Claim 1, wherein said at least one buried electrode is formed by: 2 I:\IBM\ 1 05\29714Z\AMEND\29714Z. aml.doc forming at least one trench in said insulator layer; filling said at least one trench with at least one conductive material; and removing portions of said at least one conductive material from above a plane of a top surface of said insulator layer, wherein remaining portions of said at least one conductive material constitute said at least one buried electrode.
The method of Claim 1, wherein said at least one first upper electrode and said at least one second upper electrode are simultaneously formed by a masked directional deposition of a conductive material.
The method of Claim 1, wherein each of said at least one buried electrode includes a pair of sidewalls that extends along a lengthwise direction that is perpendicular to a spacing between one of said at least one first upper electrode and one of said at least one second upper electrode.
The method of Claim 1, wherein one of said at least one first upper electrode has a pair of parallel sidewalls separated by a first width and extending along a lengthwise direction, and one of said at least one second upper electrode has a pair of sidewalls separated by a second width and extending along said lengthwise direction.
The method of Claim 1, wherein said at least one first upper electrode is a plurality of first upper electrodes, said at least one second upper electrode is a plurality of second upper electrodes, and said plurality of first upper electrodes and said plurality of second upper electrodes are interlaced to provide an alternating arrangement of first and second upper electrodes along a horizontal direction.
The method of Claim 1, inducing charge carriers in regions of said graphene layer that overlie said at least one buried electrode by applying an electrical bias to said at least one buried electrode, wherein said charge carriers have a conductivity type that is the opposite of a first conductivity type of said graphene layer as provided said electrical bias.
4 1:\ I BM\ 1 05\29714Z\AMEND\29714Z.aml.doc on said insulator layer prior to application of said electrical bias is performed employing at least one buried electrode relative to said at at least one second upper electrode. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene electromagnetic radiation detector (photodetector)
Materials described outside the worked examples.
graphene
insulator layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a schematic view of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,987,740Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of an exemplary structure after formation of trenches in an insulator layer according to an embodiment of the present …
FIG. 2 is a vertical cross-sectional view of the exemplary structure after formation of buried electrodes according to an embodiment of the present invention. …
FIG. 3 is a vertical cross-sectional view of the exemplary structure after placement of a graphene layer on the top surface of the insulator layer according to …
FIG. 4 is a vertical cross-sectional view of the exemplary structure after forming of first upper electrodes and second upper electrodes according to an …
FIG. 5 is a schematic view of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement …
FIG. 6 is a schematic view of a variation of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fo rm ing an electromagnetic radiation detector comprising: forming at least one buried electrode in an insulator layer; forming a graphene layer over said insulator layer; forming at least one p-n junction within said graphene la y er, wherein one of said at least one p-n junction does not overlie, and is laterally offset from a sidewall of, one of said at least one buried ele ctrode; forming at least one first upper electrode, wherein each of said at least one first upper electrode has a pair of sidewalls that overlie a top surface of one of said at least one buried electrode; forming at least one second upper electrode that does not overlie, and is laterally offset from sidewalls of, said at least one buried electrode; and forming a measurement circuitry configured to measure an electrical current between, or an electrical voltage across, said at least one first upper electrode and said at least one second upper electrode.
The method of Claim 1, wherein said at least one buried electrode is formed by: 2 I:\IBM\ 1 05\29714Z\AMEND\29714Z. aml.doc forming at least one trench in said insulator layer; filling said at least one trench with at least one conductive material; and removing portions of said at least one conductive material from above a plane of a top surface of said insulator layer, wherein remaining portions of said at least one conductive material constitute said at least one buried electrode.
The method of Claim 1, wherein said at least one first upper electrode and said at least one second upper electrode are simultaneously formed by a masked directional deposition of a conductive material.
The method of Claim 1, wherein each of said at least one buried electrode includes a pair of sidewalls that extends along a lengthwise direction that is perpendicular to a spacing between one of said at least one first upper electrode and one of said at least one second upper electrode.
The method of Claim 1, wherein one of said at least one first upper electrode has a pair of parallel sidewalls separated by a first width and extending along a lengthwise direction, and one of said at least one second upper electrode has a pair of sidewalls separated by a second width and extending along said lengthwise direction.
The method of Claim 1, wherein said at least one first upper electrode is a plurality of first upper electrodes, said at least one second upper electrode is a plurality of second upper electrodes, and said plurality of first upper electrodes and said plurality of second upper electrodes are interlaced to provide an alternating arrangement of first and second upper electrodes along a horizontal direction.
The method of Claim 1, inducing charge carriers in regions of said graphene layer that overlie said at least one buried electrode by applying an electrical bias to said at least one buried electrode, wherein said charge carriers have a conductivity type that is the opposite of a first conductivity type of said graphene layer as provided said electrical bias.
4 1:\ I BM\ 1 05\29714Z\AMEND\29714Z.aml.doc on said insulator layer prior to application of said electrical bias is performed employing at least one buried electrode relative to said at at least one second upper electrode. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene electromagnetic radiation detector (photodetector)
Materials described outside the worked examples.
graphene
insulator layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a schematic view of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a measurement …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
conductive material (electrodes)
silicon oxide
SiO₂
silicon nitride
Si₃N₄
TiN
TaN
WN
Au
Ag
Ti
Ta
Al
Cu
Pt
FIG. 6 is a schematic view of a variation of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a …
| — |
Thickness | 50–5000 nm | — |
Thickness | 50–2000 nm | — |
Thickness | 1–10 nm | — |
Thickness | 25–1000 nm | — |
Thickness | 3–30 nm | — |
Voltage | 0.5–5 V | — |
Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes
conductive material (electrodes)
silicon oxide
SiO₂
silicon nitride
Si₃N₄
TiN
TaN
WN
Au
Ag
Ti
Ta
Al
Cu
Pt
FIG. 6 is a schematic view of a variation of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a …
| — |
Thickness | 50–5000 nm | — |
Thickness | 50–2000 nm | — |
Thickness | 1–10 nm | — |
Thickness | 25–1000 nm | — |
Thickness | 3–30 nm | — |
Voltage | 0.5–5 V | — |
Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes
conductive material (electrodes)
silicon oxide
SiO₂
silicon nitride
Si₃N₄
TiN
TaN
WN
Au
Ag
Ti
Ta
Al
Cu
Pt
FIG. 6 is a schematic view of a variation of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a …
| — |
Thickness | 50–5000 nm | — |
Thickness | 50–2000 nm | — |
Thickness | 1–10 nm | — |
Thickness | 25–1000 nm | — |
Thickness | 3–30 nm | — |
Voltage | 0.5–5 V | — |
Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes
conductive material (electrodes)
silicon oxide
SiO₂
silicon nitride
Si₃N₄
TiN
TaN
WN
Au
Ag
Ti
Ta
Al
Cu
Pt
FIG. 6 is a schematic view of a variation of the exemplary structure after formation of contact structures and electrical wiring for a bias circuitry and a …
| — |
Thickness | 50–5000 nm | — |
Thickness | 50–2000 nm | — |
Thickness | 1–10 nm | — |
Thickness | 25–1000 nm | — |
Thickness | 3–30 nm | — |
Voltage | 0.5–5 V | — |
Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes