Patent
US 9,362,379GRAPHENE HETEROSTRUCTURE FIELD EFFECT TRANSISTORS
Jeong-Sun MOON
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,362,379Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 4A shows a diagram of a p-type Gr/GrF/Gr H FET in accordance with the present disclosure; [0022]
FIG. 5 shows a method of fabricating a lateral graphene heterostructure FET in accordance with the present disclosure. DETAILED DESCRIPTION [0024] In the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method of fabricating a heterostructure FET comprises: forming graphene on a substrate; forming a graphene mesa by dry etching; forming a first ohmic contact for a source on one end of the graphene mesa; forming a second ohmic contact for a drain on an opposite end of the graphene mesa; forming an opening by masking and etching to expose a portion of the graphene between the first and second ohmic contacts; doping an exposed portion of the graphene with Fluorine; annealing to reduce defects; depositing a gate dielectric over the opening; and forming a gate over the gate dielectric.
The method of claim 14 wherein forming graphene on a substrate comprises epitiaxial processes to form graphene on the substrate, or using chemical vapor deposition (CVD) to deposit the graphene layer on a metal foil and then transferring the graphene layer to the substrate. New U.S. Divisional Patent Application Attorney Docket No. B-8016D I V 630020-4 Page 4
The method of claim 14 wherein doping the exposed portion of the graphene with Fluorine doping comprises using XeF₂ or other gas chemistry or gas plasma chemistry.
The method of claim 14 wherein: the graphene is n-type; and the first and second ohmic contacts are n-type.
The method of claim 14 wherein: the graphene is p-type; and the first and second ohmic contacts are p-type.
The method of claim 14 wherein the substrate comprises Si, SiO2, SiC, glass, or pyrex.
The method of claim 14 wherein the gate dielectric layer comprises silicon nitride (SiN), silicon dioxide (SiO₂), Boron Nitride (BN), aluminum oxide (A 1 2O₃), or hafnium oxide (HfO₂).
The method of claim 14 wherein the gate is formed to overlap the portion of the graphene doped with Fluorine.
Layer stacks claimed or described, ordered top of device to substrate.
lateral graphene heterostructure FET (HFET)
Materials described outside the worked examples.
graphene
fluorographene
GrF
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
on-off resistance ratio Gr/GrF/Gr HFET channel resistance | 100000 | grapheneGrF |
Ion/Ioff ratio at Vds=1V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,362,379Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 4A shows a diagram of a p-type Gr/GrF/Gr H FET in accordance with the present disclosure; [0022]
FIG. 5 shows a method of fabricating a lateral graphene heterostructure FET in accordance with the present disclosure. DETAILED DESCRIPTION [0024] In the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method of fabricating a heterostructure FET comprises: forming graphene on a substrate; forming a graphene mesa by dry etching; forming a first ohmic contact for a source on one end of the graphene mesa; forming a second ohmic contact for a drain on an opposite end of the graphene mesa; forming an opening by masking and etching to expose a portion of the graphene between the first and second ohmic contacts; doping an exposed portion of the graphene with Fluorine; annealing to reduce defects; depositing a gate dielectric over the opening; and forming a gate over the gate dielectric.
The method of claim 14 wherein forming graphene on a substrate comprises epitiaxial processes to form graphene on the substrate, or using chemical vapor deposition (CVD) to deposit the graphene layer on a metal foil and then transferring the graphene layer to the substrate. New U.S. Divisional Patent Application Attorney Docket No. B-8016D I V 630020-4 Page 4
The method of claim 14 wherein doping the exposed portion of the graphene with Fluorine doping comprises using XeF₂ or other gas chemistry or gas plasma chemistry.
The method of claim 14 wherein: the graphene is n-type; and the first and second ohmic contacts are n-type.
The method of claim 14 wherein: the graphene is p-type; and the first and second ohmic contacts are p-type.
The method of claim 14 wherein the substrate comprises Si, SiO2, SiC, glass, or pyrex.
The method of claim 14 wherein the gate dielectric layer comprises silicon nitride (SiN), silicon dioxide (SiO₂), Boron Nitride (BN), aluminum oxide (A 1 2O₃), or hafnium oxide (HfO₂).
The method of claim 14 wherein the gate is formed to overlap the portion of the graphene doped with Fluorine.
Layer stacks claimed or described, ordered top of device to substrate.
lateral graphene heterostructure FET (HFET)
Materials described outside the worked examples.
graphene
fluorographene
GrF
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
on-off resistance ratio Gr/GrF/Gr HFET channel resistance | 100000 | grapheneGrF |
Ion/Ioff ratio at Vds=1V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,362,379Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 4A shows a diagram of a p-type Gr/GrF/Gr H FET in accordance with the present disclosure; [0022]
FIG. 5 shows a method of fabricating a lateral graphene heterostructure FET in accordance with the present disclosure. DETAILED DESCRIPTION [0024] In the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-13. [Cancelled] canceled
canceled
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canceled
canceled
canceled
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A method of fabricating a heterostructure FET comprises: forming graphene on a substrate; forming a graphene mesa by dry etching; forming a first ohmic contact for a source on one end of the graphene mesa; forming a second ohmic contact for a drain on an opposite end of the graphene mesa; forming an opening by masking and etching to expose a portion of the graphene between the first and second ohmic contacts; doping an exposed portion of the graphene with Fluorine; annealing to reduce defects; depositing a gate dielectric over the opening; and forming a gate over the gate dielectric.
The method of claim 14 wherein forming graphene on a substrate comprises epitiaxial processes to form graphene on the substrate, or using chemical vapor deposition (CVD) to deposit the graphene layer on a metal foil and then transferring the graphene layer to the substrate. New U.S. Divisional Patent Application Attorney Docket No. B-8016D I V 630020-4 Page 4
The method of claim 14 wherein doping the exposed portion of the graphene with Fluorine doping comprises using XeF₂ or other gas chemistry or gas plasma chemistry.
The method of claim 14 wherein: the graphene is n-type; and the first and second ohmic contacts are n-type.
The method of claim 14 wherein: the graphene is p-type; and the first and second ohmic contacts are p-type.
The method of claim 14 wherein the substrate comprises Si, SiO2, SiC, glass, or pyrex.
The method of claim 14 wherein the gate dielectric layer comprises silicon nitride (SiN), silicon dioxide (SiO₂), Boron Nitride (BN), aluminum oxide (A 1 2O₃), or hafnium oxide (HfO₂).
The method of claim 14 wherein the gate is formed to overlap the portion of the graphene doped with Fluorine.
Layer stacks claimed or described, ordered top of device to substrate.
lateral graphene heterostructure FET (HFET)
Materials described outside the worked examples.
graphene
fluorographene
GrF
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
on-off resistance ratio Gr/GrF/Gr HFET channel resistance | 100000 | grapheneGrF |
Ion/Ioff ratio at Vds=1V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,362,379Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 4A shows a diagram of a p-type Gr/GrF/Gr H FET in accordance with the present disclosure; [0022]
FIG. 5 shows a method of fabricating a lateral graphene heterostructure FET in accordance with the present disclosure. DETAILED DESCRIPTION [0024] In the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-13. [Cancelled] canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
A method of fabricating a heterostructure FET comprises: forming graphene on a substrate; forming a graphene mesa by dry etching; forming a first ohmic contact for a source on one end of the graphene mesa; forming a second ohmic contact for a drain on an opposite end of the graphene mesa; forming an opening by masking and etching to expose a portion of the graphene between the first and second ohmic contacts; doping an exposed portion of the graphene with Fluorine; annealing to reduce defects; depositing a gate dielectric over the opening; and forming a gate over the gate dielectric.
The method of claim 14 wherein forming graphene on a substrate comprises epitiaxial processes to form graphene on the substrate, or using chemical vapor deposition (CVD) to deposit the graphene layer on a metal foil and then transferring the graphene layer to the substrate. New U.S. Divisional Patent Application Attorney Docket No. B-8016D I V 630020-4 Page 4
The method of claim 14 wherein doping the exposed portion of the graphene with Fluorine doping comprises using XeF₂ or other gas chemistry or gas plasma chemistry.
The method of claim 14 wherein: the graphene is n-type; and the first and second ohmic contacts are n-type.
The method of claim 14 wherein: the graphene is p-type; and the first and second ohmic contacts are p-type.
The method of claim 14 wherein the substrate comprises Si, SiO2, SiC, glass, or pyrex.
The method of claim 14 wherein the gate dielectric layer comprises silicon nitride (SiN), silicon dioxide (SiO₂), Boron Nitride (BN), aluminum oxide (A 1 2O₃), or hafnium oxide (HfO₂).
The method of claim 14 wherein the gate is formed to overlap the portion of the graphene doped with Fluorine.
Layer stacks claimed or described, ordered top of device to substrate.
lateral graphene heterostructure FET (HFET)
Materials described outside the worked examples.
graphene
fluorographene
GrF
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
on-off resistance ratio Gr/GrF/Gr HFET channel resistance | 100000 | grapheneGrF |
Ion/Ioff ratio at Vds=1V |
Related documents with shared materials, methods, properties, or citations.
gate dielectric
XeF₂
silicon
Si
silicon dioxide
SiO₂
silicon carbide
SiC
silicon nitride
SiN
boron nitride
BN
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
titanium
Ti
gold
Au
hexagonal boron nitride
h-BN
molybdenum disulfide
MoS₂
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 4A shows a diagram of a p-type Gr/GrF/Gr H FET in accordance with the present disclosure; [0022]
FIG. 5 shows a method of fabricating a lateral graphene heterostructure FET in accordance with the present disclosure. DETAILED DESCRIPTION [0024] In the …
| 7000 |
grapheneGrF |
off-state channel resistance | 3000000000 | grapheneGrF |
on-state channel resistance | 30000 | grapheneGrF |
turn-on gate voltage | 2 | grapheneGrF |
Voltage | 0–2 V | — |
Voltage | ≥ 2 V | — |
gate dielectric
XeF₂
silicon
Si
silicon dioxide
SiO₂
silicon carbide
SiC
silicon nitride
SiN
boron nitride
BN
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
titanium
Ti
gold
Au
hexagonal boron nitride
h-BN
molybdenum disulfide
MoS₂
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 4A shows a diagram of a p-type Gr/GrF/Gr H FET in accordance with the present disclosure; [0022]
FIG. 5 shows a method of fabricating a lateral graphene heterostructure FET in accordance with the present disclosure. DETAILED DESCRIPTION [0024] In the …
| 7000 |
grapheneGrF |
off-state channel resistance | 3000000000 | grapheneGrF |
on-state channel resistance | 30000 | grapheneGrF |
turn-on gate voltage | 2 | grapheneGrF |
Voltage | 0–2 V | — |
Voltage | ≥ 2 V | — |
gate dielectric
XeF₂
silicon
Si
silicon dioxide
SiO₂
silicon carbide
SiC
silicon nitride
SiN
boron nitride
BN
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
titanium
Ti
gold
Au
hexagonal boron nitride
h-BN
molybdenum disulfide
MoS₂
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 4A shows a diagram of a p-type Gr/GrF/Gr H FET in accordance with the present disclosure; [0022]
FIG. 5 shows a method of fabricating a lateral graphene heterostructure FET in accordance with the present disclosure. DETAILED DESCRIPTION [0024] In the …
| 7000 |
grapheneGrF |
off-state channel resistance | 3000000000 | grapheneGrF |
on-state channel resistance | 30000 | grapheneGrF |
turn-on gate voltage | 2 | grapheneGrF |
Voltage | 0–2 V | — |
Voltage | ≥ 2 V | — |
gate dielectric
XeF₂
silicon
Si
silicon dioxide
SiO₂
silicon carbide
SiC
silicon nitride
SiN
boron nitride
BN
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
titanium
Ti
gold
Au
hexagonal boron nitride
h-BN
molybdenum disulfide
MoS₂
FIG. 1 B shows a schematic sketch of the band alignment at zero source-drain bias for the graphene (Gr) 14, fluorographene (GrF) 16, and graphene (Gr) 18 H F ET …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 2A shows asimplified schematic sketch of the Gr/GrF/Gr band alignment at a finite source-drain bias. [0028] The current vs. voltage characteristics were …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 3 B shows a graph of the channel current versus Vds at room temperature for channel length Lds = 0.25 m and Lds = 0.5 m, respectively. The channel current …
FIG. 4A shows a diagram of a p-type Gr/GrF/Gr H FET in accordance with the present disclosure; [0022]
FIG. 5 shows a method of fabricating a lateral graphene heterostructure FET in accordance with the present disclosure. DETAILED DESCRIPTION [0024] In the …
| 7000 |
grapheneGrF |
off-state channel resistance | 3000000000 | grapheneGrF |
on-state channel resistance | 30000 | grapheneGrF |
turn-on gate voltage | 2 | grapheneGrF |
Voltage | 0–2 V | — |
Voltage | ≥ 2 V | — |