Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 2A and 2B illustrate an embodiment of a semiconductor structure 200 that includes such an electron stopping layer 202. The semiconductor structure 200 is …
FIG. 3A) may be relatively higher than the energy level of the conduction band 328 within the InGaN base layer 112 and/or the energy level of the conduction …
FIGS. 4A and 4B illustrate yet another embodiment of a semiconductor structure 400 of the present disclosure. The semiconductor structure 400 is similar to the …
FIG. 5B. Further, each of the band-gap energies 550 A-550 c of the quantum well regions 514 A-514 c may be substantially equal and may be less than each of the …
FIG. 6C. In greater detail and with reference to
FIG. 7. Although the following description describes embodiments for fabricating light emitting devices from semiconductor structure 100, it should be noted …
FIG. 8. As non-limiting examples, the luminary devices may be as described in, for example, U.S. Patent No. 6,600,175, which issued July 29, 2003 to Baretz et …
FIG. 9 illustrates a graph 900 showing the relationship between IQE (a.u.) and total strain energy (a.u.) for the semiconductor structures of the present …
FIGS. 10 A and lO B at an applied current density across the LED 556 of one hundred twenty-five amps per square centimeter (125 A/cm 2).
FIG. 11 E is a graph illustrating the calculated internal quantum efficiency as a function of applied current density across the active region of the LED of
FIGS. 12A and 12B illustrate another example of an embodiment of an LED 600 of the present disclosure. The LED 600 includes an active region 106 comprising five …
FIG. 13D, the LED 600 may exhibit an injection efficiency of about 75.6% at an applied current density of 125 A/cm 2, and may exhibit a carrier injection …
FIG. 14 illustrates an example of a luminary device that includes an LED of the present disclosure. DETAILED DESCRIPTION [0043] The illustrations presented …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a base layer comprising an In 1 Gai 11 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 Angstroms; an active region over the base layer and comprising: at least one well layer; and at least one barrier layer directly adjacent the at least one well layer; an electron blocking layer over the active region; a p-type bulk layer over the electron blocking layer; and a p-type contact layer over the p-type bulk layer.
The semiconductor structure of claim 1, wherein the base layer further comp ri ses: a support substrate; a dielectric material between the support substrate and the InGai 11 N layer; and an In s Gaips N seed layer between the dielectric material and the In 1 Gaip N layer, wherein 0.05 <s< 0.10 and a growth plane of the In s Gaips N seed layer is a polar plane having a growth plane lattice parameter of greater than about 3.2 Angstroms.
The semiconductor structure of claim 1, wherein the at least one well layer of the active region comprises InW Gai.. N, wherein 0. 10<w<0.40.
The semiconductor structure of claim 1, wherein the at least one barrier layer of the active region comprises In b Gaip b N, wherein 0.0 1<b<0. 10.
The semiconductor structure of claim 1, wherein the active region comprises: a first pair of adjacent active layers comprising: a first well layer comprising InwiGaipWi N, wherein 0. 10<wl<0.40; and a first barrier layer directly adjacent the first well layer and comprising In b1 Ga 1. b1 N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.1.svg 0.15 1.84 Black and white a second pair of adjacent active layers directly adjacent the first pair of adjacent active layers and comprising: a second well layer comprising Inw 2 Ga 1 -w 2 N, wherein 0. 10<w2<0.40; and a second barrier layer directly adjacent the second well layer and comprising In b2 Ga i-b2 N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.2.svg 0.13 1.54 Black and white
The semiconductor structure of claim 1, wherein the active region consists essentially of InGaN.
The semiconductor structure of claim 1, wherein one or more of the at least one well layer and the at least one barrier layer is doped with at least one n-type dopant, a concentration of the at least one n-type dopant in the one or more of the at least one well layer and the at least one barrier layer within a range from about 3e 1 cm⁻³ to about le 19 cm⁻³
The semiconductor structure of claim 1, further comprising one or more of: a spacer layer comprising Ins p Ga ips p N between the In 1 Gai. 1 N layer and the active region, wherein SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.3.svg 0.16 1.24 Black and white a cap layer comprising Inc p Ga ipc p N between the active region and the electron blocking layer, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.4.svg 0.16 1.53 Black and white 3 Serial No. 14/991,100
The semiconductor structure of claim 1, wherein the electron blocking layer is selected from the group consisting of: a single layer of IneGai- e N, wherein 0. 00 <e <0. 02; 0.00<e<0.02, a single layer of Al e1 Ga i- e1 N, wherein 0. 00 <el <0. 20; 0.00<el<0.20; alternating layers of GaN and I n e2 Ga i- e2 N, wherein 0. 01 <e2 <0. 02; 0.01<e2<0.02, and SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.5.svg 0.16 5.51 Black and white
The semiconductor structure of claim 1, wherein the electron blocking layer is doped with at least one p-type dopant, a concentration of the at least one p-type dopant in the electron blocking layer within a range from about le 1 cm -3 to about le21 cm -3
The semiconductor structure of claim 1, wherein the p-type bulk layer comprises InpGai- p N doped with at least one p-type dopant, wherein 0.01<p<0.0 8 and a concentration of the at least one p-type dopant in the p-type bulk layer is within a range from about l e" cm -3 to about le21 cm -3
The semiconductor structure of claim 1, wherein the p-type contact layer comprises In c Gai-c N doped with at least one p-type dopant, wherein 0.01 <c< 0.10 and a concentration of the at least one p-type dopant in the p-type contact layer is within a range from about l e" cm -3 to about le21 cm -3 4 Serial No. 14/991,100
The semiconductor structure of claim 1, further comprising: a spacer layer comprising I n sp Ga i- sp N doped with at least one n-type dopant between the base layer and the active region, wherein 0.0 1<sp 0.10 and a concentration of the at least one p-type dopant in the spacer layer is within a range from about 3e 17 cm⁻³ to about le 19 cm- 3; and a strain relief layer comprising a superlattice structure doped with at least one n-type dopant between the base layer and the spacer layer, the superlattice structure comprising alternating layers of I n sra Ga l-sra, wherein 0.0 1< sra <0.10, and In srb Ga l-srb, wherein 0.01< srb <0.10, a concentration of the at least one n-type dopant in the superlattice structure within a range from about 0. le 18 cm⁻³ to about 20e 18 cm -3
A method of forming a semiconductor structure, comprising: forming a base layer comprising an In 1 Gai. 1 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 A; forming an active region over the base layer, the active region comprising: at least one well layer comprising InWGaI.. N, wherein 0. 10<w< 0.40; and at least one barrier layer directly adjacent the well layer and comprising In b Ga l-b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.6.svg 0.15 1.46 Black and white forming an electron blocking layer over the active region; forming a p-type bulk layer over the electron blocking layer; and forming a p-type contact layer over the p-type bulk layer.
The method of claim 15, wherein the at least one well layer comprises InWGaI.. N and the at least one barrier layer comprises In b Ga l-b N, wherein 0. 10<w< 0.40 and SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.7.svg 0.13 0.87 Black and white 5 Serial No. 14/991,100
The method of claim 15, wherein forming a base layer comprises: forming an InGai s N seed layer over a support substrate, wherein 0.05 <s<0. 10 and a growth plane of the In s Gaip s N seed layer is a polar plane having a growth plane lattice parameter of greater than about 3.2 Angstroms; and forming the In 1 Gaip N layer on the In s Gaip s N seed layer.
The method of claim 15, wherein forming an active region over the base layer comprises: forming a first pair of adjacent active layers over the base layer, the first pair of adjacent active layers comprising: a first well layer comprising InWGai.. N, wherein 0. 10<w<0.40; and a first barrier layer directly adjacent the first well layer and comprising In b Gai b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.8.svg 0.15 1.75 Black and white forming a second pair of adjacent active layers directly adjacent the first pair of adjacent active layers, the second pair of adjacent active layers comprising: a second well layer comprising InWGa i.. N, wherein 0. 10<w<0.40; and a second barrier layer directly adjacent the second well layer and comprising In b Gai b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.9.svg 0.13 1.45 Black and white
The method of claim 15, further comprising one or more of: forming a spacer layer comprising In sp Ga ipS p N between the InGaip N layer and the active region, wherein 0.01<sp 0.10; and forming a cap layer comprising Inc p Ga ipc p N between the active region and the electron blocking layer, wherein 0.01 cp 0.10.
The method of claim 15, further comprising forming a strain relief layer between the base layer and the active region, the strain relief layer comprising alternating layers of Ins ra Ga i- sra, wherein 0.01 < sra <0.10, and Ins rb Gaib srb, wherein 0.01 < srb 0. 10.
A light emitting device, comprising: a base layer comprising an In 1 Ga l11 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 Angstroms; an active region over the base layer and comprising: at least one well layer; and at least one barrier layer directly adjacent the at least one well layer; an electron blocking layer over the active region; a p-type bulk layer over the electron blocking layer; and a p-type contact layer over the p-type bulk layer.
The light emitting device of claim 22, wherein a critical strain energy of the light emitting device is less than or equal to about 4500 (a.u.). 8
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure/LED
light emitting device
Materials described outside the worked examples.
InGaN base layer
InGaN
InGaN well layer
InwGa₁-wN
InGaN barrier layer
InbGa₁-bN
p-type InGaN bulk layer
InpGa₁-pN
p-type InGaN contact layer
IncGa₁-cN
InGaN seed layer
InsGa₁-sN
dielectric material
InGaN spacer layer
InspGa₁-spN
InGaN cap layer
IncpGa₁-cpN
InGaN electron blocking layer
IneGa₁-eN
AlGaN electron blocking layer
Ale1Ga₁-e1N
GaN (in electron blocking layer superlattice)
GaN
InGaN (in electron blocking layer superlattice)
Ine2Ga₁-e2N
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIG. 5B. Further, each of the band-gap energies 550 A-550 c of the quantum well regions 514 A-514 c may be substantially equal and may be less than each of the …
FIG. 8. As non-limiting examples, the luminary devices may be as described in, for example, U.S. Patent No. 6,600,175, which issued July 29, 2003 to Baretz et …
FIG. 9 illustrates a graph 900 showing the relationship between IQE (a.u.) and total strain energy (a.u.) for the semiconductor structures of the present …
FIGS. 10 A and lO B at an applied current density across the LED 556 of one hundred twenty-five amps per square centimeter (125 A/cm 2).
FIG. 11 E is a graph illustrating the calculated internal quantum efficiency as a function of applied current density across the active region of the LED of
FIGS. 12A and 12B illustrate another example of an embodiment of an LED 600 of the present disclosure. The LED 600 includes an active region 106 comprising five …
FIG. 13D, the LED 600 may exhibit an injection efficiency of about 75.6% at an applied current density of 125 A/cm 2, and may exhibit a carrier injection …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
growth plane lattice parameter of InGaN base layer (claimed minimum) | 3.2 Angstroms | InGaN |
critical strain energy of light emitting device (claimed maximum) | 4500 a.u. | — |
Thickness | 3.2–3.3 Å | — |
Pressure | 50–500 mTorr | — |
Pressure | 50–250 mTorr | — |
Temperature | 600–1000 °C | — |
Temperature | 600–950 °C | — |
Thickness | ≥ 3.2 Å | — |
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 2A and 2B illustrate an embodiment of a semiconductor structure 200 that includes such an electron stopping layer 202. The semiconductor structure 200 is …
FIG. 3A) may be relatively higher than the energy level of the conduction band 328 within the InGaN base layer 112 and/or the energy level of the conduction …
FIGS. 4A and 4B illustrate yet another embodiment of a semiconductor structure 400 of the present disclosure. The semiconductor structure 400 is similar to the …
FIG. 5B. Further, each of the band-gap energies 550 A-550 c of the quantum well regions 514 A-514 c may be substantially equal and may be less than each of the …
FIG. 6C. In greater detail and with reference to
FIG. 7. Although the following description describes embodiments for fabricating light emitting devices from semiconductor structure 100, it should be noted …
FIG. 8. As non-limiting examples, the luminary devices may be as described in, for example, U.S. Patent No. 6,600,175, which issued July 29, 2003 to Baretz et …
FIG. 9 illustrates a graph 900 showing the relationship between IQE (a.u.) and total strain energy (a.u.) for the semiconductor structures of the present …
FIGS. 10 A and lO B at an applied current density across the LED 556 of one hundred twenty-five amps per square centimeter (125 A/cm 2).
FIG. 11 E is a graph illustrating the calculated internal quantum efficiency as a function of applied current density across the active region of the LED of
FIGS. 12A and 12B illustrate another example of an embodiment of an LED 600 of the present disclosure. The LED 600 includes an active region 106 comprising five …
FIG. 13D, the LED 600 may exhibit an injection efficiency of about 75.6% at an applied current density of 125 A/cm 2, and may exhibit a carrier injection …
FIG. 14 illustrates an example of a luminary device that includes an LED of the present disclosure. DETAILED DESCRIPTION [0043] The illustrations presented …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a base layer comprising an In 1 Gai 11 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 Angstroms; an active region over the base layer and comprising: at least one well layer; and at least one barrier layer directly adjacent the at least one well layer; an electron blocking layer over the active region; a p-type bulk layer over the electron blocking layer; and a p-type contact layer over the p-type bulk layer.
The semiconductor structure of claim 1, wherein the base layer further comp ri ses: a support substrate; a dielectric material between the support substrate and the InGai 11 N layer; and an In s Gaips N seed layer between the dielectric material and the In 1 Gaip N layer, wherein 0.05 <s< 0.10 and a growth plane of the In s Gaips N seed layer is a polar plane having a growth plane lattice parameter of greater than about 3.2 Angstroms.
The semiconductor structure of claim 1, wherein the at least one well layer of the active region comprises InW Gai.. N, wherein 0. 10<w<0.40.
The semiconductor structure of claim 1, wherein the at least one barrier layer of the active region comprises In b Gaip b N, wherein 0.0 1<b<0. 10.
The semiconductor structure of claim 1, wherein the active region comprises: a first pair of adjacent active layers comprising: a first well layer comprising InwiGaipWi N, wherein 0. 10<wl<0.40; and a first barrier layer directly adjacent the first well layer and comprising In b1 Ga 1. b1 N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.1.svg 0.15 1.84 Black and white a second pair of adjacent active layers directly adjacent the first pair of adjacent active layers and comprising: a second well layer comprising Inw 2 Ga 1 -w 2 N, wherein 0. 10<w2<0.40; and a second barrier layer directly adjacent the second well layer and comprising In b2 Ga i-b2 N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.2.svg 0.13 1.54 Black and white
The semiconductor structure of claim 1, wherein the active region consists essentially of InGaN.
The semiconductor structure of claim 1, wherein one or more of the at least one well layer and the at least one barrier layer is doped with at least one n-type dopant, a concentration of the at least one n-type dopant in the one or more of the at least one well layer and the at least one barrier layer within a range from about 3e 1 cm⁻³ to about le 19 cm⁻³
The semiconductor structure of claim 1, further comprising one or more of: a spacer layer comprising Ins p Ga ips p N between the In 1 Gai. 1 N layer and the active region, wherein SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.3.svg 0.16 1.24 Black and white a cap layer comprising Inc p Ga ipc p N between the active region and the electron blocking layer, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.4.svg 0.16 1.53 Black and white 3 Serial No. 14/991,100
The semiconductor structure of claim 1, wherein the electron blocking layer is selected from the group consisting of: a single layer of IneGai- e N, wherein 0. 00 <e <0. 02; 0.00<e<0.02, a single layer of Al e1 Ga i- e1 N, wherein 0. 00 <el <0. 20; 0.00<el<0.20; alternating layers of GaN and I n e2 Ga i- e2 N, wherein 0. 01 <e2 <0. 02; 0.01<e2<0.02, and SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.5.svg 0.16 5.51 Black and white
The semiconductor structure of claim 1, wherein the electron blocking layer is doped with at least one p-type dopant, a concentration of the at least one p-type dopant in the electron blocking layer within a range from about le 1 cm -3 to about le21 cm -3
The semiconductor structure of claim 1, wherein the p-type bulk layer comprises InpGai- p N doped with at least one p-type dopant, wherein 0.01<p<0.0 8 and a concentration of the at least one p-type dopant in the p-type bulk layer is within a range from about l e" cm -3 to about le21 cm -3
The semiconductor structure of claim 1, wherein the p-type contact layer comprises In c Gai-c N doped with at least one p-type dopant, wherein 0.01 <c< 0.10 and a concentration of the at least one p-type dopant in the p-type contact layer is within a range from about l e" cm -3 to about le21 cm -3 4 Serial No. 14/991,100
The semiconductor structure of claim 1, further comprising: a spacer layer comprising I n sp Ga i- sp N doped with at least one n-type dopant between the base layer and the active region, wherein 0.0 1<sp 0.10 and a concentration of the at least one p-type dopant in the spacer layer is within a range from about 3e 17 cm⁻³ to about le 19 cm- 3; and a strain relief layer comprising a superlattice structure doped with at least one n-type dopant between the base layer and the spacer layer, the superlattice structure comprising alternating layers of I n sra Ga l-sra, wherein 0.0 1< sra <0.10, and In srb Ga l-srb, wherein 0.01< srb <0.10, a concentration of the at least one n-type dopant in the superlattice structure within a range from about 0. le 18 cm⁻³ to about 20e 18 cm -3
A method of forming a semiconductor structure, comprising: forming a base layer comprising an In 1 Gai. 1 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 A; forming an active region over the base layer, the active region comprising: at least one well layer comprising InWGaI.. N, wherein 0. 10<w< 0.40; and at least one barrier layer directly adjacent the well layer and comprising In b Ga l-b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.6.svg 0.15 1.46 Black and white forming an electron blocking layer over the active region; forming a p-type bulk layer over the electron blocking layer; and forming a p-type contact layer over the p-type bulk layer.
The method of claim 15, wherein the at least one well layer comprises InWGaI.. N and the at least one barrier layer comprises In b Ga l-b N, wherein 0. 10<w< 0.40 and SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.7.svg 0.13 0.87 Black and white 5 Serial No. 14/991,100
The method of claim 15, wherein forming a base layer comprises: forming an InGai s N seed layer over a support substrate, wherein 0.05 <s<0. 10 and a growth plane of the In s Gaip s N seed layer is a polar plane having a growth plane lattice parameter of greater than about 3.2 Angstroms; and forming the In 1 Gaip N layer on the In s Gaip s N seed layer.
The method of claim 15, wherein forming an active region over the base layer comprises: forming a first pair of adjacent active layers over the base layer, the first pair of adjacent active layers comprising: a first well layer comprising InWGai.. N, wherein 0. 10<w<0.40; and a first barrier layer directly adjacent the first well layer and comprising In b Gai b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.8.svg 0.15 1.75 Black and white forming a second pair of adjacent active layers directly adjacent the first pair of adjacent active layers, the second pair of adjacent active layers comprising: a second well layer comprising InWGa i.. N, wherein 0. 10<w<0.40; and a second barrier layer directly adjacent the second well layer and comprising In b Gai b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.9.svg 0.13 1.45 Black and white
The method of claim 15, further comprising one or more of: forming a spacer layer comprising In sp Ga ipS p N between the InGaip N layer and the active region, wherein 0.01<sp 0.10; and forming a cap layer comprising Inc p Ga ipc p N between the active region and the electron blocking layer, wherein 0.01 cp 0.10.
The method of claim 15, further comprising forming a strain relief layer between the base layer and the active region, the strain relief layer comprising alternating layers of Ins ra Ga i- sra, wherein 0.01 < sra <0.10, and Ins rb Gaib srb, wherein 0.01 < srb 0. 10.
A light emitting device, comprising: a base layer comprising an In 1 Ga l11 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 Angstroms; an active region over the base layer and comprising: at least one well layer; and at least one barrier layer directly adjacent the at least one well layer; an electron blocking layer over the active region; a p-type bulk layer over the electron blocking layer; and a p-type contact layer over the p-type bulk layer.
The light emitting device of claim 22, wherein a critical strain energy of the light emitting device is less than or equal to about 4500 (a.u.). 8
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure/LED
light emitting device
Materials described outside the worked examples.
InGaN base layer
InGaN
InGaN well layer
InwGa₁-wN
InGaN barrier layer
InbGa₁-bN
p-type InGaN bulk layer
InpGa₁-pN
p-type InGaN contact layer
IncGa₁-cN
InGaN seed layer
InsGa₁-sN
dielectric material
InGaN spacer layer
InspGa₁-spN
InGaN cap layer
IncpGa₁-cpN
InGaN electron blocking layer
IneGa₁-eN
AlGaN electron blocking layer
Ale1Ga₁-e1N
GaN (in electron blocking layer superlattice)
GaN
InGaN (in electron blocking layer superlattice)
Ine2Ga₁-e2N
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIG. 5B. Further, each of the band-gap energies 550 A-550 c of the quantum well regions 514 A-514 c may be substantially equal and may be less than each of the …
FIG. 8. As non-limiting examples, the luminary devices may be as described in, for example, U.S. Patent No. 6,600,175, which issued July 29, 2003 to Baretz et …
FIG. 9 illustrates a graph 900 showing the relationship between IQE (a.u.) and total strain energy (a.u.) for the semiconductor structures of the present …
FIGS. 10 A and lO B at an applied current density across the LED 556 of one hundred twenty-five amps per square centimeter (125 A/cm 2).
FIG. 11 E is a graph illustrating the calculated internal quantum efficiency as a function of applied current density across the active region of the LED of
FIGS. 12A and 12B illustrate another example of an embodiment of an LED 600 of the present disclosure. The LED 600 includes an active region 106 comprising five …
FIG. 13D, the LED 600 may exhibit an injection efficiency of about 75.6% at an applied current density of 125 A/cm 2, and may exhibit a carrier injection …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
growth plane lattice parameter of InGaN base layer (claimed minimum) | 3.2 Angstroms | InGaN |
critical strain energy of light emitting device (claimed maximum) | 4500 a.u. | — |
Thickness | 3.2–3.3 Å | — |
Pressure | 50–500 mTorr | — |
Pressure | 50–250 mTorr | — |
Temperature | 600–1000 °C | — |
Temperature | 600–950 °C | — |
Thickness | ≥ 3.2 Å | — |
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GRAPHENE SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, ORGANIC LIGHT EMITTING DISPLAY, AND MEMORY INCLUDING GRAPHENE SEMICONDUCTOR DEVICE
GALLIUM NITRIDE COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LIGHT SOURCE PROVIDED WITH SAID LIGHT EMITTING ELEMENT
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 2A and 2B illustrate an embodiment of a semiconductor structure 200 that includes such an electron stopping layer 202. The semiconductor structure 200 is …
FIG. 3A) may be relatively higher than the energy level of the conduction band 328 within the InGaN base layer 112 and/or the energy level of the conduction …
FIGS. 4A and 4B illustrate yet another embodiment of a semiconductor structure 400 of the present disclosure. The semiconductor structure 400 is similar to the …
FIG. 5B. Further, each of the band-gap energies 550 A-550 c of the quantum well regions 514 A-514 c may be substantially equal and may be less than each of the …
FIG. 6C. In greater detail and with reference to
FIG. 7. Although the following description describes embodiments for fabricating light emitting devices from semiconductor structure 100, it should be noted …
FIG. 8. As non-limiting examples, the luminary devices may be as described in, for example, U.S. Patent No. 6,600,175, which issued July 29, 2003 to Baretz et …
FIG. 9 illustrates a graph 900 showing the relationship between IQE (a.u.) and total strain energy (a.u.) for the semiconductor structures of the present …
FIGS. 10 A and lO B at an applied current density across the LED 556 of one hundred twenty-five amps per square centimeter (125 A/cm 2).
FIG. 11 E is a graph illustrating the calculated internal quantum efficiency as a function of applied current density across the active region of the LED of
FIGS. 12A and 12B illustrate another example of an embodiment of an LED 600 of the present disclosure. The LED 600 includes an active region 106 comprising five …
FIG. 13D, the LED 600 may exhibit an injection efficiency of about 75.6% at an applied current density of 125 A/cm 2, and may exhibit a carrier injection …
FIG. 14 illustrates an example of a luminary device that includes an LED of the present disclosure. DETAILED DESCRIPTION [0043] The illustrations presented …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a base layer comprising an In 1 Gai 11 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 Angstroms; an active region over the base layer and comprising: at least one well layer; and at least one barrier layer directly adjacent the at least one well layer; an electron blocking layer over the active region; a p-type bulk layer over the electron blocking layer; and a p-type contact layer over the p-type bulk layer.
The semiconductor structure of claim 1, wherein the base layer further comp ri ses: a support substrate; a dielectric material between the support substrate and the InGai 11 N layer; and an In s Gaips N seed layer between the dielectric material and the In 1 Gaip N layer, wherein 0.05 <s< 0.10 and a growth plane of the In s Gaips N seed layer is a polar plane having a growth plane lattice parameter of greater than about 3.2 Angstroms.
The semiconductor structure of claim 1, wherein the at least one well layer of the active region comprises InW Gai.. N, wherein 0. 10<w<0.40.
The semiconductor structure of claim 1, wherein the at least one barrier layer of the active region comprises In b Gaip b N, wherein 0.0 1<b<0. 10.
The semiconductor structure of claim 1, wherein the active region comprises: a first pair of adjacent active layers comprising: a first well layer comprising InwiGaipWi N, wherein 0. 10<wl<0.40; and a first barrier layer directly adjacent the first well layer and comprising In b1 Ga 1. b1 N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.1.svg 0.15 1.84 Black and white a second pair of adjacent active layers directly adjacent the first pair of adjacent active layers and comprising: a second well layer comprising Inw 2 Ga 1 -w 2 N, wherein 0. 10<w2<0.40; and a second barrier layer directly adjacent the second well layer and comprising In b2 Ga i-b2 N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.2.svg 0.13 1.54 Black and white
The semiconductor structure of claim 1, wherein the active region consists essentially of InGaN.
The semiconductor structure of claim 1, wherein one or more of the at least one well layer and the at least one barrier layer is doped with at least one n-type dopant, a concentration of the at least one n-type dopant in the one or more of the at least one well layer and the at least one barrier layer within a range from about 3e 1 cm⁻³ to about le 19 cm⁻³
The semiconductor structure of claim 1, further comprising one or more of: a spacer layer comprising Ins p Ga ips p N between the In 1 Gai. 1 N layer and the active region, wherein SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.3.svg 0.16 1.24 Black and white a cap layer comprising Inc p Ga ipc p N between the active region and the electron blocking layer, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.4.svg 0.16 1.53 Black and white 3 Serial No. 14/991,100
The semiconductor structure of claim 1, wherein the electron blocking layer is selected from the group consisting of: a single layer of IneGai- e N, wherein 0. 00 <e <0. 02; 0.00<e<0.02, a single layer of Al e1 Ga i- e1 N, wherein 0. 00 <el <0. 20; 0.00<el<0.20; alternating layers of GaN and I n e2 Ga i- e2 N, wherein 0. 01 <e2 <0. 02; 0.01<e2<0.02, and SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.5.svg 0.16 5.51 Black and white
The semiconductor structure of claim 1, wherein the electron blocking layer is doped with at least one p-type dopant, a concentration of the at least one p-type dopant in the electron blocking layer within a range from about le 1 cm -3 to about le21 cm -3
The semiconductor structure of claim 1, wherein the p-type bulk layer comprises InpGai- p N doped with at least one p-type dopant, wherein 0.01<p<0.0 8 and a concentration of the at least one p-type dopant in the p-type bulk layer is within a range from about l e" cm -3 to about le21 cm -3
The semiconductor structure of claim 1, wherein the p-type contact layer comprises In c Gai-c N doped with at least one p-type dopant, wherein 0.01 <c< 0.10 and a concentration of the at least one p-type dopant in the p-type contact layer is within a range from about l e" cm -3 to about le21 cm -3 4 Serial No. 14/991,100
The semiconductor structure of claim 1, further comprising: a spacer layer comprising I n sp Ga i- sp N doped with at least one n-type dopant between the base layer and the active region, wherein 0.0 1<sp 0.10 and a concentration of the at least one p-type dopant in the spacer layer is within a range from about 3e 17 cm⁻³ to about le 19 cm- 3; and a strain relief layer comprising a superlattice structure doped with at least one n-type dopant between the base layer and the spacer layer, the superlattice structure comprising alternating layers of I n sra Ga l-sra, wherein 0.0 1< sra <0.10, and In srb Ga l-srb, wherein 0.01< srb <0.10, a concentration of the at least one n-type dopant in the superlattice structure within a range from about 0. le 18 cm⁻³ to about 20e 18 cm -3
A method of forming a semiconductor structure, comprising: forming a base layer comprising an In 1 Gai. 1 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 A; forming an active region over the base layer, the active region comprising: at least one well layer comprising InWGaI.. N, wherein 0. 10<w< 0.40; and at least one barrier layer directly adjacent the well layer and comprising In b Ga l-b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.6.svg 0.15 1.46 Black and white forming an electron blocking layer over the active region; forming a p-type bulk layer over the electron blocking layer; and forming a p-type contact layer over the p-type bulk layer.
The method of claim 15, wherein the at least one well layer comprises InWGaI.. N and the at least one barrier layer comprises In b Ga l-b N, wherein 0. 10<w< 0.40 and SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.7.svg 0.13 0.87 Black and white 5 Serial No. 14/991,100
The method of claim 15, wherein forming a base layer comprises: forming an InGai s N seed layer over a support substrate, wherein 0.05 <s<0. 10 and a growth plane of the In s Gaip s N seed layer is a polar plane having a growth plane lattice parameter of greater than about 3.2 Angstroms; and forming the In 1 Gaip N layer on the In s Gaip s N seed layer.
The method of claim 15, wherein forming an active region over the base layer comprises: forming a first pair of adjacent active layers over the base layer, the first pair of adjacent active layers comprising: a first well layer comprising InWGai.. N, wherein 0. 10<w<0.40; and a first barrier layer directly adjacent the first well layer and comprising In b Gai b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.8.svg 0.15 1.75 Black and white forming a second pair of adjacent active layers directly adjacent the first pair of adjacent active layers, the second pair of adjacent active layers comprising: a second well layer comprising InWGa i.. N, wherein 0. 10<w<0.40; and a second barrier layer directly adjacent the second well layer and comprising In b Gai b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.9.svg 0.13 1.45 Black and white
The method of claim 15, further comprising one or more of: forming a spacer layer comprising In sp Ga ipS p N between the InGaip N layer and the active region, wherein 0.01<sp 0.10; and forming a cap layer comprising Inc p Ga ipc p N between the active region and the electron blocking layer, wherein 0.01 cp 0.10.
The method of claim 15, further comprising forming a strain relief layer between the base layer and the active region, the strain relief layer comprising alternating layers of Ins ra Ga i- sra, wherein 0.01 < sra <0.10, and Ins rb Gaib srb, wherein 0.01 < srb 0. 10.
A light emitting device, comprising: a base layer comprising an In 1 Ga l11 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 Angstroms; an active region over the base layer and comprising: at least one well layer; and at least one barrier layer directly adjacent the at least one well layer; an electron blocking layer over the active region; a p-type bulk layer over the electron blocking layer; and a p-type contact layer over the p-type bulk layer.
The light emitting device of claim 22, wherein a critical strain energy of the light emitting device is less than or equal to about 4500 (a.u.). 8
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure/LED
light emitting device
Materials described outside the worked examples.
InGaN base layer
InGaN
InGaN well layer
InwGa₁-wN
InGaN barrier layer
InbGa₁-bN
p-type InGaN bulk layer
InpGa₁-pN
p-type InGaN contact layer
IncGa₁-cN
InGaN seed layer
InsGa₁-sN
dielectric material
InGaN spacer layer
InspGa₁-spN
InGaN cap layer
IncpGa₁-cpN
InGaN electron blocking layer
IneGa₁-eN
AlGaN electron blocking layer
Ale1Ga₁-e1N
GaN (in electron blocking layer superlattice)
GaN
InGaN (in electron blocking layer superlattice)
Ine2Ga₁-e2N
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIG. 5B. Further, each of the band-gap energies 550 A-550 c of the quantum well regions 514 A-514 c may be substantially equal and may be less than each of the …
FIG. 8. As non-limiting examples, the luminary devices may be as described in, for example, U.S. Patent No. 6,600,175, which issued July 29, 2003 to Baretz et …
FIG. 9 illustrates a graph 900 showing the relationship between IQE (a.u.) and total strain energy (a.u.) for the semiconductor structures of the present …
FIGS. 10 A and lO B at an applied current density across the LED 556 of one hundred twenty-five amps per square centimeter (125 A/cm 2).
FIG. 11 E is a graph illustrating the calculated internal quantum efficiency as a function of applied current density across the active region of the LED of
FIGS. 12A and 12B illustrate another example of an embodiment of an LED 600 of the present disclosure. The LED 600 includes an active region 106 comprising five …
FIG. 13D, the LED 600 may exhibit an injection efficiency of about 75.6% at an applied current density of 125 A/cm 2, and may exhibit a carrier injection …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
growth plane lattice parameter of InGaN base layer (claimed minimum) | 3.2 Angstroms | InGaN |
critical strain energy of light emitting device (claimed maximum) | 4500 a.u. | — |
Thickness | 3.2–3.3 Å | — |
Pressure | 50–500 mTorr | — |
Pressure | 50–250 mTorr | — |
Temperature | 600–1000 °C | — |
Temperature | 600–950 °C | — |
Thickness | ≥ 3.2 Å | — |
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 2A and 2B illustrate an embodiment of a semiconductor structure 200 that includes such an electron stopping layer 202. The semiconductor structure 200 is …
FIG. 3A) may be relatively higher than the energy level of the conduction band 328 within the InGaN base layer 112 and/or the energy level of the conduction …
FIGS. 4A and 4B illustrate yet another embodiment of a semiconductor structure 400 of the present disclosure. The semiconductor structure 400 is similar to the …
FIG. 5B. Further, each of the band-gap energies 550 A-550 c of the quantum well regions 514 A-514 c may be substantially equal and may be less than each of the …
FIG. 6C. In greater detail and with reference to
FIG. 7. Although the following description describes embodiments for fabricating light emitting devices from semiconductor structure 100, it should be noted …
FIG. 8. As non-limiting examples, the luminary devices may be as described in, for example, U.S. Patent No. 6,600,175, which issued July 29, 2003 to Baretz et …
FIG. 9 illustrates a graph 900 showing the relationship between IQE (a.u.) and total strain energy (a.u.) for the semiconductor structures of the present …
FIGS. 10 A and lO B at an applied current density across the LED 556 of one hundred twenty-five amps per square centimeter (125 A/cm 2).
FIG. 11 E is a graph illustrating the calculated internal quantum efficiency as a function of applied current density across the active region of the LED of
FIGS. 12A and 12B illustrate another example of an embodiment of an LED 600 of the present disclosure. The LED 600 includes an active region 106 comprising five …
FIG. 13D, the LED 600 may exhibit an injection efficiency of about 75.6% at an applied current density of 125 A/cm 2, and may exhibit a carrier injection …
FIG. 14 illustrates an example of a luminary device that includes an LED of the present disclosure. DETAILED DESCRIPTION [0043] The illustrations presented …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a base layer comprising an In 1 Gai 11 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 Angstroms; an active region over the base layer and comprising: at least one well layer; and at least one barrier layer directly adjacent the at least one well layer; an electron blocking layer over the active region; a p-type bulk layer over the electron blocking layer; and a p-type contact layer over the p-type bulk layer.
The semiconductor structure of claim 1, wherein the base layer further comp ri ses: a support substrate; a dielectric material between the support substrate and the InGai 11 N layer; and an In s Gaips N seed layer between the dielectric material and the In 1 Gaip N layer, wherein 0.05 <s< 0.10 and a growth plane of the In s Gaips N seed layer is a polar plane having a growth plane lattice parameter of greater than about 3.2 Angstroms.
The semiconductor structure of claim 1, wherein the at least one well layer of the active region comprises InW Gai.. N, wherein 0. 10<w<0.40.
The semiconductor structure of claim 1, wherein the at least one barrier layer of the active region comprises In b Gaip b N, wherein 0.0 1<b<0. 10.
The semiconductor structure of claim 1, wherein the active region comprises: a first pair of adjacent active layers comprising: a first well layer comprising InwiGaipWi N, wherein 0. 10<wl<0.40; and a first barrier layer directly adjacent the first well layer and comprising In b1 Ga 1. b1 N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.1.svg 0.15 1.84 Black and white a second pair of adjacent active layers directly adjacent the first pair of adjacent active layers and comprising: a second well layer comprising Inw 2 Ga 1 -w 2 N, wherein 0. 10<w2<0.40; and a second barrier layer directly adjacent the second well layer and comprising In b2 Ga i-b2 N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.2.svg 0.13 1.54 Black and white
The semiconductor structure of claim 1, wherein the active region consists essentially of InGaN.
The semiconductor structure of claim 1, wherein one or more of the at least one well layer and the at least one barrier layer is doped with at least one n-type dopant, a concentration of the at least one n-type dopant in the one or more of the at least one well layer and the at least one barrier layer within a range from about 3e 1 cm⁻³ to about le 19 cm⁻³
The semiconductor structure of claim 1, further comprising one or more of: a spacer layer comprising Ins p Ga ips p N between the In 1 Gai. 1 N layer and the active region, wherein SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.3.svg 0.16 1.24 Black and white a cap layer comprising Inc p Ga ipc p N between the active region and the electron blocking layer, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.4.svg 0.16 1.53 Black and white 3 Serial No. 14/991,100
The semiconductor structure of claim 1, wherein the electron blocking layer is selected from the group consisting of: a single layer of IneGai- e N, wherein 0. 00 <e <0. 02; 0.00<e<0.02, a single layer of Al e1 Ga i- e1 N, wherein 0. 00 <el <0. 20; 0.00<el<0.20; alternating layers of GaN and I n e2 Ga i- e2 N, wherein 0. 01 <e2 <0. 02; 0.01<e2<0.02, and SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.5.svg 0.16 5.51 Black and white
The semiconductor structure of claim 1, wherein the electron blocking layer is doped with at least one p-type dopant, a concentration of the at least one p-type dopant in the electron blocking layer within a range from about le 1 cm -3 to about le21 cm -3
The semiconductor structure of claim 1, wherein the p-type bulk layer comprises InpGai- p N doped with at least one p-type dopant, wherein 0.01<p<0.0 8 and a concentration of the at least one p-type dopant in the p-type bulk layer is within a range from about l e" cm -3 to about le21 cm -3
The semiconductor structure of claim 1, wherein the p-type contact layer comprises In c Gai-c N doped with at least one p-type dopant, wherein 0.01 <c< 0.10 and a concentration of the at least one p-type dopant in the p-type contact layer is within a range from about l e" cm -3 to about le21 cm -3 4 Serial No. 14/991,100
The semiconductor structure of claim 1, further comprising: a spacer layer comprising I n sp Ga i- sp N doped with at least one n-type dopant between the base layer and the active region, wherein 0.0 1<sp 0.10 and a concentration of the at least one p-type dopant in the spacer layer is within a range from about 3e 17 cm⁻³ to about le 19 cm- 3; and a strain relief layer comprising a superlattice structure doped with at least one n-type dopant between the base layer and the spacer layer, the superlattice structure comprising alternating layers of I n sra Ga l-sra, wherein 0.0 1< sra <0.10, and In srb Ga l-srb, wherein 0.01< srb <0.10, a concentration of the at least one n-type dopant in the superlattice structure within a range from about 0. le 18 cm⁻³ to about 20e 18 cm -3
A method of forming a semiconductor structure, comprising: forming a base layer comprising an In 1 Gai. 1 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 A; forming an active region over the base layer, the active region comprising: at least one well layer comprising InWGaI.. N, wherein 0. 10<w< 0.40; and at least one barrier layer directly adjacent the well layer and comprising In b Ga l-b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.6.svg 0.15 1.46 Black and white forming an electron blocking layer over the active region; forming a p-type bulk layer over the electron blocking layer; and forming a p-type contact layer over the p-type bulk layer.
The method of claim 15, wherein the at least one well layer comprises InWGaI.. N and the at least one barrier layer comprises In b Ga l-b N, wherein 0. 10<w< 0.40 and SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.7.svg 0.13 0.87 Black and white 5 Serial No. 14/991,100
The method of claim 15, wherein forming a base layer comprises: forming an InGai s N seed layer over a support substrate, wherein 0.05 <s<0. 10 and a growth plane of the In s Gaip s N seed layer is a polar plane having a growth plane lattice parameter of greater than about 3.2 Angstroms; and forming the In 1 Gaip N layer on the In s Gaip s N seed layer.
The method of claim 15, wherein forming an active region over the base layer comprises: forming a first pair of adjacent active layers over the base layer, the first pair of adjacent active layers comprising: a first well layer comprising InWGai.. N, wherein 0. 10<w<0.40; and a first barrier layer directly adjacent the first well layer and comprising In b Gai b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.8.svg 0.15 1.75 Black and white forming a second pair of adjacent active layers directly adjacent the first pair of adjacent active layers, the second pair of adjacent active layers comprising: a second well layer comprising InWGa i.. N, wherein 0. 10<w<0.40; and a second barrier layer directly adjacent the second well layer and comprising In b Gai b N, SVG 14991100.03-10-2017.J04B₀DQKRXEAPX3.CLM.9.svg 0.13 1.45 Black and white
The method of claim 15, further comprising one or more of: forming a spacer layer comprising In sp Ga ipS p N between the InGaip N layer and the active region, wherein 0.01<sp 0.10; and forming a cap layer comprising Inc p Ga ipc p N between the active region and the electron blocking layer, wherein 0.01 cp 0.10.
The method of claim 15, further comprising forming a strain relief layer between the base layer and the active region, the strain relief layer comprising alternating layers of Ins ra Ga i- sra, wherein 0.01 < sra <0.10, and Ins rb Gaib srb, wherein 0.01 < srb 0. 10.
A light emitting device, comprising: a base layer comprising an In 1 Ga l11 N layer having a polar growth plane with a growth plane lattice parameter of greater than about 3.2 Angstroms; an active region over the base layer and comprising: at least one well layer; and at least one barrier layer directly adjacent the at least one well layer; an electron blocking layer over the active region; a p-type bulk layer over the electron blocking layer; and a p-type contact layer over the p-type bulk layer.
The light emitting device of claim 22, wherein a critical strain energy of the light emitting device is less than or equal to about 4500 (a.u.). 8
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure/LED
light emitting device
Materials described outside the worked examples.
InGaN base layer
InGaN
InGaN well layer
InwGa₁-wN
InGaN barrier layer
InbGa₁-bN
p-type InGaN bulk layer
InpGa₁-pN
p-type InGaN contact layer
IncGa₁-cN
InGaN seed layer
InsGa₁-sN
dielectric material
InGaN spacer layer
InspGa₁-spN
InGaN cap layer
IncpGa₁-cpN
InGaN electron blocking layer
IneGa₁-eN
AlGaN electron blocking layer
Ale1Ga₁-e1N
GaN (in electron blocking layer superlattice)
GaN
InGaN (in electron blocking layer superlattice)
Ine2Ga₁-e2N
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIGS. 1A and 1 B, may be configured, and the energy band structure thereof designed, such that the active region 106 exhibits a reduced piezoelectric …
FIG. 5B. Further, each of the band-gap energies 550 A-550 c of the quantum well regions 514 A-514 c may be substantially equal and may be less than each of the …
FIG. 8. As non-limiting examples, the luminary devices may be as described in, for example, U.S. Patent No. 6,600,175, which issued July 29, 2003 to Baretz et …
FIG. 9 illustrates a graph 900 showing the relationship between IQE (a.u.) and total strain energy (a.u.) for the semiconductor structures of the present …
FIGS. 10 A and lO B at an applied current density across the LED 556 of one hundred twenty-five amps per square centimeter (125 A/cm 2).
FIG. 11 E is a graph illustrating the calculated internal quantum efficiency as a function of applied current density across the active region of the LED of
FIGS. 12A and 12B illustrate another example of an embodiment of an LED 600 of the present disclosure. The LED 600 includes an active region 106 comprising five …
FIG. 13D, the LED 600 may exhibit an injection efficiency of about 75.6% at an applied current density of 125 A/cm 2, and may exhibit a carrier injection …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
growth plane lattice parameter of InGaN base layer (claimed minimum) | 3.2 Angstroms | InGaN |
critical strain energy of light emitting device (claimed maximum) | 4500 a.u. | — |
Thickness | 3.2–3.3 Å | — |
Pressure | 50–500 mTorr | — |
Pressure | 50–250 mTorr | — |
Temperature | 600–1000 °C | — |
Temperature | 600–950 °C | — |
Thickness | ≥ 3.2 Å | — |
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