Patent
US 10,923,630P-GAN-DOWN MICRO-LED ON SEMI-POLAR ORIENTED GAN
Christopher Pynn
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,923,630Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The scanning instructions may be used by image source assembly 2810 to generate image light. The scanning instructions may specify, for example, a type …
FIGS. 2 and 3. Additionally, in various embodiments, the functionality described herein may be used in a headset that combines images of an environment …
FIG. 3 is a perspective view of an example of a near-eye display 300 in the form of a pair of glasses for implementing some of the examples disclosed herein. …
FIG. 4A illustrates an example of a light emitting diode 400 including a vertical mesa structure. LED 400 may be a micro-LED made of inorganic materials, such …
FIG. 5, the optical emission power of a micro-LED device may be low when the current density (and thus the charge carrier density N) is low, where the low …
FIG. 6A. When index c of a plane is nonzero, and any of the al and a2 indices of the plane is nonzero, the plane is a semi-polar plane. If index c of a plane …
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 8, the micro-LED devices are fabricated on I II -nitride materials grown on the c-plane of a substrate. Curve 810 shows the external quantum efficiency as a …
FIG. 9B illustrates another example of a semi-polar plane 920 in crystal materia l 900 having a hexagonal crystal lattice structure according to certain …
FIG. 10 and may emit green light. Curve 1210 illustrates the external quantum efficiency as a function of the current density for a micro-LED device having a …
FIG. 11. In some embodiments, additional operations, such as reactor conditioning and/or surface treatment, may be performed, for example, after growing the …
FIG. 12 illustrates the relationship between external quantum efficiency and current density for examples of semi-polar micro-LED devices having different sizes …
FIG. 13 illustrates the relationship between the center wavelength of the emitted light and the bias current density for semi-polar micro-LEDs including …
FIG. 14 illustrates a curve 1410 that shows the polarization charge densities at the interfaces of quantum well structures (e.g., InGaN/GaN QWs) having …
FIG. 15A illustrates the polarization-induced internal field and the built-in electric field in a light emitting diode 1500 fabricated in (2021) plane-oriented …
FIG. 16 illustrates the polarization-induced internal field and the built-in electric field in a light emitting diode 1600 fabricated in (20 21) plane-oriented …
FIG. 17 illustrates a p-GaN-down light emitting diode 1700 fabricated in epitaxially grown (2021) plane-oriented GaN layers according to certain embodiments. …
FIG. 18 illustrates a p-GaN-down micro light emitting diode 1800 fabricated in epitaxially grown (2021) plane-oriented GaN layers and bonded to a backplane …
FIG. 19 is a flow chart 1900 illustrating an example of a method of fabricating a p- GaN- down micro-LED device in (20 2 1) plane-oriented GaN layers according …
FIG. 20. At least some micro-LEDs in micro-LED array 2500 may share a common anode (e.g., contact layer 2320, which may be transparent). Micro-LED array 2500 …
FIG. 21 illustrates an example of a p-GaN-down micro-LED device epitaxially grown on a (2021) plane-oriented substrate and bonded to a carrier according to …
FIG. 22 illustrates an example of a p-GaN-down micro-LED device 2200 bonded to a carrier (e.g., carrier 2110) according to certain embodiments. Micro-LED …
FIG. 23 illustrates an example of a p-GaN-down micro-LED device 2300 bonded to a carrier (e.g., carrier 2110) according to certain embodiments. Micro-LED …
FIG. 24 illustrates an example of a micro-LED device 2400 bonded to a silicon backplane 2410 according to certain embodiments. Micro-LED device 2400 may be …
FIG. 25 illustrates an assembled p-GaN-down micro-LED array 2500 on a silicon backplane (e.g., silicon backplane 2410) according to certain embodiments. …
FIG. 26. Coupler 2782 may also couple portions of the light propagating within waveguide display 2780 out of waveguide display 2780 and towards user's eye …
FIG. 27A. As such, at the exit pupil of the waveguide display, each discrete portion is presented in a different respective location. While each discrete …
FIG. 28 is shown as a stand-alone unit that is separate from controller 2820 and driver circuit 2844, image processor 2830 may be a sub-unit of controller 2820 …
FIG. 29 is a simplified block diagram of an example electronic system 2900 of an example near-eye display (e.g., HMD device) for implementing some of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method comprising: forming, on a semi-polar plane-oriented surface of a substrate, an n-i-n junction that includes a sacrificial layer sandwiched by a first n-type I II -nitride material layer and a second n- type I II -nitride material layer; forming, on the second n-type I II -nitride material layer, a p-type I II -nitride material layer; growing, on the p-type I II -nitride material layer, a light emi t ting region that includes one or more I II -nitride material layers; forming, on the light emi t ting region, a third n-type I II -nitride material layer; etching the third n-type I II -nitride material layer, the light emitting region, and the p-type I II -nitride material layer to form one or more mesa structures and one or more anchor sites; etching the p-type I II -nitride material layer and the n-i-n junction to expose the sacrificial layer; bonding a first carrier to the anchor sites; and laterally etching the sacrificial layer using photoelectrochemical etching to detach the substrate.
The method of claim 1, wherein an angle between the semi-polar plane-oriented surface of the substrate and a c-plane of the substrate is between 45 0 and 90 0.
The method of claim 1, further comprising, after forming the p-type I II -nitride material layer, at least one of: conditioning a process chamber used to dope the p-type I II -nitride material layer to remove remaining dopants in the process chamber; or treating a surface of the p-type I II-nitride material layer to remove dopants built on the surface of the p-type I II -nitride material layer.
The method of claim 1, wherein forming the p-type I II -nitride material layer includes growing the p-type I II -nitride material layer at a temperature higher than a temperature 3 for growing the light emitting region.
1 5. The method of claim 1, further comprising: 2 etching the second n-type I II -nitride material layer to expose the p-type I II -nitride material layer; forming, on the p-type I II -nitride material layer, a p + -type I II -nitride material layer; activating the p-type I II -nitride material layer and the p + -type I II -nitride material layer; and SVG 16575246.09-18-2019.K₀PVXTKGRXEAPX2.CLM.1.svg 0.17 5.45 Black and white
A wafer comprising: a substrate including a semi-polar plane-oriented surface; an n-i-n junction grown on the semi-polar plane-oriented surface of the substrate, the n-i- n junction including a sacrificial layer sandwiched by a first n-type I II -nitride material layer and a second n-type I II-nitride material layer; a p-type I II -nitride material layer on the second n-type I II -nitride material layer; a light emitting region on the p-type I II -nitride material layer, the light emitting region including one or more I II -nitride material layers; and a third n-type I II -nitride material layer on the light emitting region.
The wafer of claim 7, wherein an angle between the semi-polar plane-oriented surface of the substrate and a c-plane of the substrate is between 45 0 and 90 0.
The wafer of claim 7, wherein the semi-polar plane-oriented surface is parallel to 2 a (2021) plane or (1122) plane of the substrate.
1 10. The wafer of claim 7, wherein the substrate includes G aN, sapphire, silicon 2 carbide, silicon, zin c oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinel, or quate rn ary tetragonal oxide having a beta-LiA lO 2 structure.
The wafer of claim 7, further comprising a buffer layer between the substrate and the n-i-n junction.
A light source comprising: a semiconductor substrate including electrical circuits fabricated thereon; and a light emitting diode bonded to the semiconductor substrate, the light emitting diode comprising: an n-type I II -nitride material layer bonded to the electrical circuits on the semiconductor substrate; a light emitting region including one or more I II -nitride material layers; and a p-type I II -nitride material layer, wherein: the light emitting region includes a side surface that is at least partially covered by a passivation layer; a bottom surface of the light emitting region is parallel to a semi-polar plane of a hexagonal lattice; and the light emitting region is characterized by a polarization-induced electric field opposite to a built-in depletion electric field in the light emitting region.
The light source of claim 12, wherein the p-type I II -nitride material layer is vertically rather than laterally activated.
The light source of claim 12, wherein an angle between the semi-polar plane and a c-plane of the hexagonal lattice is between 45 0 and 90 0.
The light source of claim 12, wherein a direction from the p-type I II -nitride 2 material layer to the n-type I II -nitride material layer is a [2021] or [1122] direction.
1 16. The light source of claim 12, wherein the light emitting region includes a single 2 InGaN/GaN quantum-well structure or an InGaN/GaN multiple-quantum-well structure.
The light source of claim 12, wherein the polarization-induced electric field and the built-in depletion electric field are antiparallel.
The light source of claim 12, wherein a majority of transistors in the electrical circuits are N M OS transistors.
The light source of claim 12, wherein the light emitting diode is characterized by a blue-shift less than 15 nm when a current density of the light emitting diode is increased ten 3 times.
Layer stacks claimed or described, ordered top of device to substrate.
semi-polar III-nitride LED structure on substrate (method claim 1)
Materials described outside the worked examples.
III-nitride sacrificial layer
p-type III-nitride material layer
Mg-doped GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5, the optical emission power of a micro-LED device may be low when the current density (and thus the charge carrier density N) is low, where the low …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
blue-shift upon 10x current density increase | ≤ 15 nm | — |
Thickness | 380–750 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,923,630Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The scanning instructions may be used by image source assembly 2810 to generate image light. The scanning instructions may specify, for example, a type …
FIGS. 2 and 3. Additionally, in various embodiments, the functionality described herein may be used in a headset that combines images of an environment …
FIG. 3 is a perspective view of an example of a near-eye display 300 in the form of a pair of glasses for implementing some of the examples disclosed herein. …
FIG. 4A illustrates an example of a light emitting diode 400 including a vertical mesa structure. LED 400 may be a micro-LED made of inorganic materials, such …
FIG. 5, the optical emission power of a micro-LED device may be low when the current density (and thus the charge carrier density N) is low, where the low …
FIG. 6A. When index c of a plane is nonzero, and any of the al and a2 indices of the plane is nonzero, the plane is a semi-polar plane. If index c of a plane …
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 8, the micro-LED devices are fabricated on I II -nitride materials grown on the c-plane of a substrate. Curve 810 shows the external quantum efficiency as a …
FIG. 9B illustrates another example of a semi-polar plane 920 in crystal materia l 900 having a hexagonal crystal lattice structure according to certain …
FIG. 10 and may emit green light. Curve 1210 illustrates the external quantum efficiency as a function of the current density for a micro-LED device having a …
FIG. 11. In some embodiments, additional operations, such as reactor conditioning and/or surface treatment, may be performed, for example, after growing the …
FIG. 12 illustrates the relationship between external quantum efficiency and current density for examples of semi-polar micro-LED devices having different sizes …
FIG. 13 illustrates the relationship between the center wavelength of the emitted light and the bias current density for semi-polar micro-LEDs including …
FIG. 14 illustrates a curve 1410 that shows the polarization charge densities at the interfaces of quantum well structures (e.g., InGaN/GaN QWs) having …
FIG. 15A illustrates the polarization-induced internal field and the built-in electric field in a light emitting diode 1500 fabricated in (2021) plane-oriented …
FIG. 16 illustrates the polarization-induced internal field and the built-in electric field in a light emitting diode 1600 fabricated in (20 21) plane-oriented …
FIG. 17 illustrates a p-GaN-down light emitting diode 1700 fabricated in epitaxially grown (2021) plane-oriented GaN layers according to certain embodiments. …
FIG. 18 illustrates a p-GaN-down micro light emitting diode 1800 fabricated in epitaxially grown (2021) plane-oriented GaN layers and bonded to a backplane …
FIG. 19 is a flow chart 1900 illustrating an example of a method of fabricating a p- GaN- down micro-LED device in (20 2 1) plane-oriented GaN layers according …
FIG. 20. At least some micro-LEDs in micro-LED array 2500 may share a common anode (e.g., contact layer 2320, which may be transparent). Micro-LED array 2500 …
FIG. 21 illustrates an example of a p-GaN-down micro-LED device epitaxially grown on a (2021) plane-oriented substrate and bonded to a carrier according to …
FIG. 22 illustrates an example of a p-GaN-down micro-LED device 2200 bonded to a carrier (e.g., carrier 2110) according to certain embodiments. Micro-LED …
FIG. 23 illustrates an example of a p-GaN-down micro-LED device 2300 bonded to a carrier (e.g., carrier 2110) according to certain embodiments. Micro-LED …
FIG. 24 illustrates an example of a micro-LED device 2400 bonded to a silicon backplane 2410 according to certain embodiments. Micro-LED device 2400 may be …
FIG. 25 illustrates an assembled p-GaN-down micro-LED array 2500 on a silicon backplane (e.g., silicon backplane 2410) according to certain embodiments. …
FIG. 26. Coupler 2782 may also couple portions of the light propagating within waveguide display 2780 out of waveguide display 2780 and towards user's eye …
FIG. 27A. As such, at the exit pupil of the waveguide display, each discrete portion is presented in a different respective location. While each discrete …
FIG. 28 is shown as a stand-alone unit that is separate from controller 2820 and driver circuit 2844, image processor 2830 may be a sub-unit of controller 2820 …
FIG. 29 is a simplified block diagram of an example electronic system 2900 of an example near-eye display (e.g., HMD device) for implementing some of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method comprising: forming, on a semi-polar plane-oriented surface of a substrate, an n-i-n junction that includes a sacrificial layer sandwiched by a first n-type I II -nitride material layer and a second n- type I II -nitride material layer; forming, on the second n-type I II -nitride material layer, a p-type I II -nitride material layer; growing, on the p-type I II -nitride material layer, a light emi t ting region that includes one or more I II -nitride material layers; forming, on the light emi t ting region, a third n-type I II -nitride material layer; etching the third n-type I II -nitride material layer, the light emitting region, and the p-type I II -nitride material layer to form one or more mesa structures and one or more anchor sites; etching the p-type I II -nitride material layer and the n-i-n junction to expose the sacrificial layer; bonding a first carrier to the anchor sites; and laterally etching the sacrificial layer using photoelectrochemical etching to detach the substrate.
The method of claim 1, wherein an angle between the semi-polar plane-oriented surface of the substrate and a c-plane of the substrate is between 45 0 and 90 0.
The method of claim 1, further comprising, after forming the p-type I II -nitride material layer, at least one of: conditioning a process chamber used to dope the p-type I II -nitride material layer to remove remaining dopants in the process chamber; or treating a surface of the p-type I II-nitride material layer to remove dopants built on the surface of the p-type I II -nitride material layer.
The method of claim 1, wherein forming the p-type I II -nitride material layer includes growing the p-type I II -nitride material layer at a temperature higher than a temperature 3 for growing the light emitting region.
1 5. The method of claim 1, further comprising: 2 etching the second n-type I II -nitride material layer to expose the p-type I II -nitride material layer; forming, on the p-type I II -nitride material layer, a p + -type I II -nitride material layer; activating the p-type I II -nitride material layer and the p + -type I II -nitride material layer; and SVG 16575246.09-18-2019.K₀PVXTKGRXEAPX2.CLM.1.svg 0.17 5.45 Black and white
A wafer comprising: a substrate including a semi-polar plane-oriented surface; an n-i-n junction grown on the semi-polar plane-oriented surface of the substrate, the n-i- n junction including a sacrificial layer sandwiched by a first n-type I II -nitride material layer and a second n-type I II-nitride material layer; a p-type I II -nitride material layer on the second n-type I II -nitride material layer; a light emitting region on the p-type I II -nitride material layer, the light emitting region including one or more I II -nitride material layers; and a third n-type I II -nitride material layer on the light emitting region.
The wafer of claim 7, wherein an angle between the semi-polar plane-oriented surface of the substrate and a c-plane of the substrate is between 45 0 and 90 0.
The wafer of claim 7, wherein the semi-polar plane-oriented surface is parallel to 2 a (2021) plane or (1122) plane of the substrate.
1 10. The wafer of claim 7, wherein the substrate includes G aN, sapphire, silicon 2 carbide, silicon, zin c oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinel, or quate rn ary tetragonal oxide having a beta-LiA lO 2 structure.
The wafer of claim 7, further comprising a buffer layer between the substrate and the n-i-n junction.
A light source comprising: a semiconductor substrate including electrical circuits fabricated thereon; and a light emitting diode bonded to the semiconductor substrate, the light emitting diode comprising: an n-type I II -nitride material layer bonded to the electrical circuits on the semiconductor substrate; a light emitting region including one or more I II -nitride material layers; and a p-type I II -nitride material layer, wherein: the light emitting region includes a side surface that is at least partially covered by a passivation layer; a bottom surface of the light emitting region is parallel to a semi-polar plane of a hexagonal lattice; and the light emitting region is characterized by a polarization-induced electric field opposite to a built-in depletion electric field in the light emitting region.
The light source of claim 12, wherein the p-type I II -nitride material layer is vertically rather than laterally activated.
The light source of claim 12, wherein an angle between the semi-polar plane and a c-plane of the hexagonal lattice is between 45 0 and 90 0.
The light source of claim 12, wherein a direction from the p-type I II -nitride 2 material layer to the n-type I II -nitride material layer is a [2021] or [1122] direction.
1 16. The light source of claim 12, wherein the light emitting region includes a single 2 InGaN/GaN quantum-well structure or an InGaN/GaN multiple-quantum-well structure.
The light source of claim 12, wherein the polarization-induced electric field and the built-in depletion electric field are antiparallel.
The light source of claim 12, wherein a majority of transistors in the electrical circuits are N M OS transistors.
The light source of claim 12, wherein the light emitting diode is characterized by a blue-shift less than 15 nm when a current density of the light emitting diode is increased ten 3 times.
Layer stacks claimed or described, ordered top of device to substrate.
semi-polar III-nitride LED structure on substrate (method claim 1)
Materials described outside the worked examples.
III-nitride sacrificial layer
p-type III-nitride material layer
Mg-doped GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5, the optical emission power of a micro-LED device may be low when the current density (and thus the charge carrier density N) is low, where the low …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
blue-shift upon 10x current density increase | ≤ 15 nm | — |
Thickness | 380–750 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,923,630Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The scanning instructions may be used by image source assembly 2810 to generate image light. The scanning instructions may specify, for example, a type …
FIGS. 2 and 3. Additionally, in various embodiments, the functionality described herein may be used in a headset that combines images of an environment …
FIG. 3 is a perspective view of an example of a near-eye display 300 in the form of a pair of glasses for implementing some of the examples disclosed herein. …
FIG. 4A illustrates an example of a light emitting diode 400 including a vertical mesa structure. LED 400 may be a micro-LED made of inorganic materials, such …
FIG. 5, the optical emission power of a micro-LED device may be low when the current density (and thus the charge carrier density N) is low, where the low …
FIG. 6A. When index c of a plane is nonzero, and any of the al and a2 indices of the plane is nonzero, the plane is a semi-polar plane. If index c of a plane …
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 8, the micro-LED devices are fabricated on I II -nitride materials grown on the c-plane of a substrate. Curve 810 shows the external quantum efficiency as a …
FIG. 9B illustrates another example of a semi-polar plane 920 in crystal materia l 900 having a hexagonal crystal lattice structure according to certain …
FIG. 10 and may emit green light. Curve 1210 illustrates the external quantum efficiency as a function of the current density for a micro-LED device having a …
FIG. 11. In some embodiments, additional operations, such as reactor conditioning and/or surface treatment, may be performed, for example, after growing the …
FIG. 12 illustrates the relationship between external quantum efficiency and current density for examples of semi-polar micro-LED devices having different sizes …
FIG. 13 illustrates the relationship between the center wavelength of the emitted light and the bias current density for semi-polar micro-LEDs including …
FIG. 14 illustrates a curve 1410 that shows the polarization charge densities at the interfaces of quantum well structures (e.g., InGaN/GaN QWs) having …
FIG. 15A illustrates the polarization-induced internal field and the built-in electric field in a light emitting diode 1500 fabricated in (2021) plane-oriented …
FIG. 16 illustrates the polarization-induced internal field and the built-in electric field in a light emitting diode 1600 fabricated in (20 21) plane-oriented …
FIG. 17 illustrates a p-GaN-down light emitting diode 1700 fabricated in epitaxially grown (2021) plane-oriented GaN layers according to certain embodiments. …
FIG. 18 illustrates a p-GaN-down micro light emitting diode 1800 fabricated in epitaxially grown (2021) plane-oriented GaN layers and bonded to a backplane …
FIG. 19 is a flow chart 1900 illustrating an example of a method of fabricating a p- GaN- down micro-LED device in (20 2 1) plane-oriented GaN layers according …
FIG. 20. At least some micro-LEDs in micro-LED array 2500 may share a common anode (e.g., contact layer 2320, which may be transparent). Micro-LED array 2500 …
FIG. 21 illustrates an example of a p-GaN-down micro-LED device epitaxially grown on a (2021) plane-oriented substrate and bonded to a carrier according to …
FIG. 22 illustrates an example of a p-GaN-down micro-LED device 2200 bonded to a carrier (e.g., carrier 2110) according to certain embodiments. Micro-LED …
FIG. 23 illustrates an example of a p-GaN-down micro-LED device 2300 bonded to a carrier (e.g., carrier 2110) according to certain embodiments. Micro-LED …
FIG. 24 illustrates an example of a micro-LED device 2400 bonded to a silicon backplane 2410 according to certain embodiments. Micro-LED device 2400 may be …
FIG. 25 illustrates an assembled p-GaN-down micro-LED array 2500 on a silicon backplane (e.g., silicon backplane 2410) according to certain embodiments. …
FIG. 26. Coupler 2782 may also couple portions of the light propagating within waveguide display 2780 out of waveguide display 2780 and towards user's eye …
FIG. 27A. As such, at the exit pupil of the waveguide display, each discrete portion is presented in a different respective location. While each discrete …
FIG. 28 is shown as a stand-alone unit that is separate from controller 2820 and driver circuit 2844, image processor 2830 may be a sub-unit of controller 2820 …
FIG. 29 is a simplified block diagram of an example electronic system 2900 of an example near-eye display (e.g., HMD device) for implementing some of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method comprising: forming, on a semi-polar plane-oriented surface of a substrate, an n-i-n junction that includes a sacrificial layer sandwiched by a first n-type I II -nitride material layer and a second n- type I II -nitride material layer; forming, on the second n-type I II -nitride material layer, a p-type I II -nitride material layer; growing, on the p-type I II -nitride material layer, a light emi t ting region that includes one or more I II -nitride material layers; forming, on the light emi t ting region, a third n-type I II -nitride material layer; etching the third n-type I II -nitride material layer, the light emitting region, and the p-type I II -nitride material layer to form one or more mesa structures and one or more anchor sites; etching the p-type I II -nitride material layer and the n-i-n junction to expose the sacrificial layer; bonding a first carrier to the anchor sites; and laterally etching the sacrificial layer using photoelectrochemical etching to detach the substrate.
The method of claim 1, wherein an angle between the semi-polar plane-oriented surface of the substrate and a c-plane of the substrate is between 45 0 and 90 0.
The method of claim 1, further comprising, after forming the p-type I II -nitride material layer, at least one of: conditioning a process chamber used to dope the p-type I II -nitride material layer to remove remaining dopants in the process chamber; or treating a surface of the p-type I II-nitride material layer to remove dopants built on the surface of the p-type I II -nitride material layer.
The method of claim 1, wherein forming the p-type I II -nitride material layer includes growing the p-type I II -nitride material layer at a temperature higher than a temperature 3 for growing the light emitting region.
1 5. The method of claim 1, further comprising: 2 etching the second n-type I II -nitride material layer to expose the p-type I II -nitride material layer; forming, on the p-type I II -nitride material layer, a p + -type I II -nitride material layer; activating the p-type I II -nitride material layer and the p + -type I II -nitride material layer; and SVG 16575246.09-18-2019.K₀PVXTKGRXEAPX2.CLM.1.svg 0.17 5.45 Black and white
A wafer comprising: a substrate including a semi-polar plane-oriented surface; an n-i-n junction grown on the semi-polar plane-oriented surface of the substrate, the n-i- n junction including a sacrificial layer sandwiched by a first n-type I II -nitride material layer and a second n-type I II-nitride material layer; a p-type I II -nitride material layer on the second n-type I II -nitride material layer; a light emitting region on the p-type I II -nitride material layer, the light emitting region including one or more I II -nitride material layers; and a third n-type I II -nitride material layer on the light emitting region.
The wafer of claim 7, wherein an angle between the semi-polar plane-oriented surface of the substrate and a c-plane of the substrate is between 45 0 and 90 0.
The wafer of claim 7, wherein the semi-polar plane-oriented surface is parallel to 2 a (2021) plane or (1122) plane of the substrate.
1 10. The wafer of claim 7, wherein the substrate includes G aN, sapphire, silicon 2 carbide, silicon, zin c oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinel, or quate rn ary tetragonal oxide having a beta-LiA lO 2 structure.
The wafer of claim 7, further comprising a buffer layer between the substrate and the n-i-n junction.
A light source comprising: a semiconductor substrate including electrical circuits fabricated thereon; and a light emitting diode bonded to the semiconductor substrate, the light emitting diode comprising: an n-type I II -nitride material layer bonded to the electrical circuits on the semiconductor substrate; a light emitting region including one or more I II -nitride material layers; and a p-type I II -nitride material layer, wherein: the light emitting region includes a side surface that is at least partially covered by a passivation layer; a bottom surface of the light emitting region is parallel to a semi-polar plane of a hexagonal lattice; and the light emitting region is characterized by a polarization-induced electric field opposite to a built-in depletion electric field in the light emitting region.
The light source of claim 12, wherein the p-type I II -nitride material layer is vertically rather than laterally activated.
The light source of claim 12, wherein an angle between the semi-polar plane and a c-plane of the hexagonal lattice is between 45 0 and 90 0.
The light source of claim 12, wherein a direction from the p-type I II -nitride 2 material layer to the n-type I II -nitride material layer is a [2021] or [1122] direction.
1 16. The light source of claim 12, wherein the light emitting region includes a single 2 InGaN/GaN quantum-well structure or an InGaN/GaN multiple-quantum-well structure.
The light source of claim 12, wherein the polarization-induced electric field and the built-in depletion electric field are antiparallel.
The light source of claim 12, wherein a majority of transistors in the electrical circuits are N M OS transistors.
The light source of claim 12, wherein the light emitting diode is characterized by a blue-shift less than 15 nm when a current density of the light emitting diode is increased ten 3 times.
Layer stacks claimed or described, ordered top of device to substrate.
semi-polar III-nitride LED structure on substrate (method claim 1)
Materials described outside the worked examples.
III-nitride sacrificial layer
p-type III-nitride material layer
Mg-doped GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5, the optical emission power of a micro-LED device may be low when the current density (and thus the charge carrier density N) is low, where the low …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
blue-shift upon 10x current density increase | ≤ 15 nm | — |
Thickness | 380–750 nm |
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US 10,923,630Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The scanning instructions may be used by image source assembly 2810 to generate image light. The scanning instructions may specify, for example, a type …
FIGS. 2 and 3. Additionally, in various embodiments, the functionality described herein may be used in a headset that combines images of an environment …
FIG. 3 is a perspective view of an example of a near-eye display 300 in the form of a pair of glasses for implementing some of the examples disclosed herein. …
FIG. 4A illustrates an example of a light emitting diode 400 including a vertical mesa structure. LED 400 may be a micro-LED made of inorganic materials, such …
FIG. 5, the optical emission power of a micro-LED device may be low when the current density (and thus the charge carrier density N) is low, where the low …
FIG. 6A. When index c of a plane is nonzero, and any of the al and a2 indices of the plane is nonzero, the plane is a semi-polar plane. If index c of a plane …
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 8, the micro-LED devices are fabricated on I II -nitride materials grown on the c-plane of a substrate. Curve 810 shows the external quantum efficiency as a …
FIG. 9B illustrates another example of a semi-polar plane 920 in crystal materia l 900 having a hexagonal crystal lattice structure according to certain …
FIG. 10 and may emit green light. Curve 1210 illustrates the external quantum efficiency as a function of the current density for a micro-LED device having a …
FIG. 11. In some embodiments, additional operations, such as reactor conditioning and/or surface treatment, may be performed, for example, after growing the …
FIG. 12 illustrates the relationship between external quantum efficiency and current density for examples of semi-polar micro-LED devices having different sizes …
FIG. 13 illustrates the relationship between the center wavelength of the emitted light and the bias current density for semi-polar micro-LEDs including …
FIG. 14 illustrates a curve 1410 that shows the polarization charge densities at the interfaces of quantum well structures (e.g., InGaN/GaN QWs) having …
FIG. 15A illustrates the polarization-induced internal field and the built-in electric field in a light emitting diode 1500 fabricated in (2021) plane-oriented …
FIG. 16 illustrates the polarization-induced internal field and the built-in electric field in a light emitting diode 1600 fabricated in (20 21) plane-oriented …
FIG. 17 illustrates a p-GaN-down light emitting diode 1700 fabricated in epitaxially grown (2021) plane-oriented GaN layers according to certain embodiments. …
FIG. 18 illustrates a p-GaN-down micro light emitting diode 1800 fabricated in epitaxially grown (2021) plane-oriented GaN layers and bonded to a backplane …
FIG. 19 is a flow chart 1900 illustrating an example of a method of fabricating a p- GaN- down micro-LED device in (20 2 1) plane-oriented GaN layers according …
FIG. 20. At least some micro-LEDs in micro-LED array 2500 may share a common anode (e.g., contact layer 2320, which may be transparent). Micro-LED array 2500 …
FIG. 21 illustrates an example of a p-GaN-down micro-LED device epitaxially grown on a (2021) plane-oriented substrate and bonded to a carrier according to …
FIG. 22 illustrates an example of a p-GaN-down micro-LED device 2200 bonded to a carrier (e.g., carrier 2110) according to certain embodiments. Micro-LED …
FIG. 23 illustrates an example of a p-GaN-down micro-LED device 2300 bonded to a carrier (e.g., carrier 2110) according to certain embodiments. Micro-LED …
FIG. 24 illustrates an example of a micro-LED device 2400 bonded to a silicon backplane 2410 according to certain embodiments. Micro-LED device 2400 may be …
FIG. 25 illustrates an assembled p-GaN-down micro-LED array 2500 on a silicon backplane (e.g., silicon backplane 2410) according to certain embodiments. …
FIG. 26. Coupler 2782 may also couple portions of the light propagating within waveguide display 2780 out of waveguide display 2780 and towards user's eye …
FIG. 27A. As such, at the exit pupil of the waveguide display, each discrete portion is presented in a different respective location. While each discrete …
FIG. 28 is shown as a stand-alone unit that is separate from controller 2820 and driver circuit 2844, image processor 2830 may be a sub-unit of controller 2820 …
FIG. 29 is a simplified block diagram of an example electronic system 2900 of an example near-eye display (e.g., HMD device) for implementing some of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method comprising: forming, on a semi-polar plane-oriented surface of a substrate, an n-i-n junction that includes a sacrificial layer sandwiched by a first n-type I II -nitride material layer and a second n- type I II -nitride material layer; forming, on the second n-type I II -nitride material layer, a p-type I II -nitride material layer; growing, on the p-type I II -nitride material layer, a light emi t ting region that includes one or more I II -nitride material layers; forming, on the light emi t ting region, a third n-type I II -nitride material layer; etching the third n-type I II -nitride material layer, the light emitting region, and the p-type I II -nitride material layer to form one or more mesa structures and one or more anchor sites; etching the p-type I II -nitride material layer and the n-i-n junction to expose the sacrificial layer; bonding a first carrier to the anchor sites; and laterally etching the sacrificial layer using photoelectrochemical etching to detach the substrate.
The method of claim 1, wherein an angle between the semi-polar plane-oriented surface of the substrate and a c-plane of the substrate is between 45 0 and 90 0.
The method of claim 1, further comprising, after forming the p-type I II -nitride material layer, at least one of: conditioning a process chamber used to dope the p-type I II -nitride material layer to remove remaining dopants in the process chamber; or treating a surface of the p-type I II-nitride material layer to remove dopants built on the surface of the p-type I II -nitride material layer.
The method of claim 1, wherein forming the p-type I II -nitride material layer includes growing the p-type I II -nitride material layer at a temperature higher than a temperature 3 for growing the light emitting region.
1 5. The method of claim 1, further comprising: 2 etching the second n-type I II -nitride material layer to expose the p-type I II -nitride material layer; forming, on the p-type I II -nitride material layer, a p + -type I II -nitride material layer; activating the p-type I II -nitride material layer and the p + -type I II -nitride material layer; and SVG 16575246.09-18-2019.K₀PVXTKGRXEAPX2.CLM.1.svg 0.17 5.45 Black and white
A wafer comprising: a substrate including a semi-polar plane-oriented surface; an n-i-n junction grown on the semi-polar plane-oriented surface of the substrate, the n-i- n junction including a sacrificial layer sandwiched by a first n-type I II -nitride material layer and a second n-type I II-nitride material layer; a p-type I II -nitride material layer on the second n-type I II -nitride material layer; a light emitting region on the p-type I II -nitride material layer, the light emitting region including one or more I II -nitride material layers; and a third n-type I II -nitride material layer on the light emitting region.
The wafer of claim 7, wherein an angle between the semi-polar plane-oriented surface of the substrate and a c-plane of the substrate is between 45 0 and 90 0.
The wafer of claim 7, wherein the semi-polar plane-oriented surface is parallel to 2 a (2021) plane or (1122) plane of the substrate.
1 10. The wafer of claim 7, wherein the substrate includes G aN, sapphire, silicon 2 carbide, silicon, zin c oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinel, or quate rn ary tetragonal oxide having a beta-LiA lO 2 structure.
The wafer of claim 7, further comprising a buffer layer between the substrate and the n-i-n junction.
A light source comprising: a semiconductor substrate including electrical circuits fabricated thereon; and a light emitting diode bonded to the semiconductor substrate, the light emitting diode comprising: an n-type I II -nitride material layer bonded to the electrical circuits on the semiconductor substrate; a light emitting region including one or more I II -nitride material layers; and a p-type I II -nitride material layer, wherein: the light emitting region includes a side surface that is at least partially covered by a passivation layer; a bottom surface of the light emitting region is parallel to a semi-polar plane of a hexagonal lattice; and the light emitting region is characterized by a polarization-induced electric field opposite to a built-in depletion electric field in the light emitting region.
The light source of claim 12, wherein the p-type I II -nitride material layer is vertically rather than laterally activated.
The light source of claim 12, wherein an angle between the semi-polar plane and a c-plane of the hexagonal lattice is between 45 0 and 90 0.
The light source of claim 12, wherein a direction from the p-type I II -nitride 2 material layer to the n-type I II -nitride material layer is a [2021] or [1122] direction.
1 16. The light source of claim 12, wherein the light emitting region includes a single 2 InGaN/GaN quantum-well structure or an InGaN/GaN multiple-quantum-well structure.
The light source of claim 12, wherein the polarization-induced electric field and the built-in depletion electric field are antiparallel.
The light source of claim 12, wherein a majority of transistors in the electrical circuits are N M OS transistors.
The light source of claim 12, wherein the light emitting diode is characterized by a blue-shift less than 15 nm when a current density of the light emitting diode is increased ten 3 times.
Layer stacks claimed or described, ordered top of device to substrate.
semi-polar III-nitride LED structure on substrate (method claim 1)
Materials described outside the worked examples.
III-nitride sacrificial layer
p-type III-nitride material layer
Mg-doped GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5, the optical emission power of a micro-LED device may be low when the current density (and thus the charge carrier density N) is low, where the low …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
blue-shift upon 10x current density increase | ≤ 15 nm | — |
Thickness | 380–750 nm |
Related documents with shared materials, methods, properties, or citations.
semi-polar III-nitride wafer (claim 7)
semi-polar micro-LED light source bonded to semiconductor substrate (claim 12)
n-type III-nitride material layer (third/top n-layer)
III-nitride light emitting region
p+-type III-nitride material layer
substrate material
InGaN/GaN quantum-well structure
passivation layer
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 8, the micro-LED devices are fabricated on I II -nitride materials grown on the c-plane of a substrate. Curve 810 shows the external quantum efficiency as a …
FIG. 10 and may emit green light. Curve 1210 illustrates the external quantum efficiency as a function of the current density for a micro-LED device having a …
FIG. 12 illustrates the relationship between external quantum efficiency and current density for examples of semi-polar micro-LED devices having different sizes …
FIG. 13 illustrates the relationship between the center wavelength of the emitted light and the bias current density for semi-polar micro-LEDs including …
| — |
Thickness | 750–1000000 nm | — |
Thickness | 10–380 nm | — |
Thickness | 650–2600 nm | — |
Thickness | 800–1000 nm | — |
Thickness | 1–10 mm | — |
Thickness | 1–2 mm | — |
Temperature | 250–300 °C | — |
Thickness | ≤ 1 mm | — |
Thickness | ≥ 30 nm | — |
semi-polar III-nitride wafer (claim 7)
semi-polar micro-LED light source bonded to semiconductor substrate (claim 12)
n-type III-nitride material layer (third/top n-layer)
III-nitride light emitting region
p+-type III-nitride material layer
substrate material
InGaN/GaN quantum-well structure
passivation layer
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 8, the micro-LED devices are fabricated on I II -nitride materials grown on the c-plane of a substrate. Curve 810 shows the external quantum efficiency as a …
FIG. 10 and may emit green light. Curve 1210 illustrates the external quantum efficiency as a function of the current density for a micro-LED device having a …
FIG. 12 illustrates the relationship between external quantum efficiency and current density for examples of semi-polar micro-LED devices having different sizes …
FIG. 13 illustrates the relationship between the center wavelength of the emitted light and the bias current density for semi-polar micro-LEDs including …
| — |
Thickness | 750–1000000 nm | — |
Thickness | 10–380 nm | — |
Thickness | 650–2600 nm | — |
Thickness | 800–1000 nm | — |
Thickness | 1–10 mm | — |
Thickness | 1–2 mm | — |
Temperature | 250–300 °C | — |
Thickness | ≤ 1 mm | — |
Thickness | ≥ 30 nm | — |
semi-polar III-nitride wafer (claim 7)
semi-polar micro-LED light source bonded to semiconductor substrate (claim 12)
n-type III-nitride material layer (third/top n-layer)
III-nitride light emitting region
p+-type III-nitride material layer
substrate material
InGaN/GaN quantum-well structure
passivation layer
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 8, the micro-LED devices are fabricated on I II -nitride materials grown on the c-plane of a substrate. Curve 810 shows the external quantum efficiency as a …
FIG. 10 and may emit green light. Curve 1210 illustrates the external quantum efficiency as a function of the current density for a micro-LED device having a …
FIG. 12 illustrates the relationship between external quantum efficiency and current density for examples of semi-polar micro-LED devices having different sizes …
FIG. 13 illustrates the relationship between the center wavelength of the emitted light and the bias current density for semi-polar micro-LEDs including …
| — |
Thickness | 750–1000000 nm | — |
Thickness | 10–380 nm | — |
Thickness | 650–2600 nm | — |
Thickness | 800–1000 nm | — |
Thickness | 1–10 mm | — |
Thickness | 1–2 mm | — |
Temperature | 250–300 °C | — |
Thickness | ≤ 1 mm | — |
Thickness | ≥ 30 nm | — |
semi-polar III-nitride wafer (claim 7)
semi-polar micro-LED light source bonded to semiconductor substrate (claim 12)
n-type III-nitride material layer (third/top n-layer)
III-nitride light emitting region
p+-type III-nitride material layer
substrate material
InGaN/GaN quantum-well structure
passivation layer
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 7A, the electron energy leve l 712 in conduction band 710 may shift to lower energy levels, while the hole energy leve l 722 in valence band 720 may shift …
FIG. 8, the micro-LED devices are fabricated on I II -nitride materials grown on the c-plane of a substrate. Curve 810 shows the external quantum efficiency as a …
FIG. 10 and may emit green light. Curve 1210 illustrates the external quantum efficiency as a function of the current density for a micro-LED device having a …
FIG. 12 illustrates the relationship between external quantum efficiency and current density for examples of semi-polar micro-LED devices having different sizes …
FIG. 13 illustrates the relationship between the center wavelength of the emitted light and the bias current density for semi-polar micro-LEDs including …
| — |
Thickness | 750–1000000 nm | — |
Thickness | 10–380 nm | — |
Thickness | 650–2600 nm | — |
Thickness | 800–1000 nm | — |
Thickness | 1–10 mm | — |
Thickness | 1–2 mm | — |
Temperature | 250–300 °C | — |
Thickness | ≤ 1 mm | — |
Thickness | ≥ 30 nm | — |