Patent
US 10,211,328NORMALLY-OFF, CUBIC PHASE
Can Bayram, Ryan William Grady, Kihoon Park
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,211,328Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 D is a diagram illustrating an alternative substrate for use in building the c-GaN FET illustrated in Figure l A, according to various embodiments.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 9 is a diagram illustrating layers of a p-channel, cubic gallium nitride (c-GaN) field-effect transistor (FET), as a function of various embodiments.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 14A is the diagram of
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 15 is a graph illustrating both conduction band offset and valence band offset of, respectively, the conduction and valence bands of the A l GaN capping layer, according to various embodiments.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 20 is an electrical schematic diagram of a ring oscillator using the disclosed c-GaN FETs within a series of inverters, according to one embodiment.
Figures 21A and 21B are graphs illustrating simulation of the ring oscillator of
Figure 22 is an electrical schematic diagram of one of the inverters of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently amended) A normally-off, heterojunction field effect transistor, comprising: SVG 15703850.08-27-2018.JLCJPIT₂RXEAPX4.CLM.1.svg 0.16 3.87 Black and white an aluminum gallium nitride (AlGaN) capping layer disposed on the c-GaN substrate, wherein the AlGaN capping layer comprises: a first sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; and a second sublayer of doped c-phase A lx Ga 1 -x N disposed on the first sublayer, wherein the second sublayer is of a second thickness and is doped with a dopant; an insulating layer disposed on an entirety of the AlGaN capping layer, wherein the insulating layer is of a fourth thickness; a source electrode positioned adjacent a first side of the insulating layer; a drain electrode positioned adjacent a second side of the insulating layer opposite from the first side; and a gate electrode disposed on the insulating layer and positioned between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode are connectable to function as a logic device. Currently amended
The transistor of claim 1, wherein the dopant is a p-type impurity within a delta-doped layer, the dopant comprising one of magnesium, carbon, or a combination thereof. Original
The transistor of claim 1, wherein the dopant is an n-type impurity within a delta-doped layer, the dopant comprising one of silicon, germanium, or a combination thereof. Original
The transistor of claim 1, wherein the insulating layer is of a material comprising one of A l N, SiO 2, SiN, HfO 2, Zr O 2, A₁ 2 0, or a combination thereof. Original
The transistor of claim 1, wherein the first thickness is between approximately 2 nm and 10 nm. Original
The transistor of claim 1, wherein the second thickness is between approximately 1 nm and 5 nm. Original
The transistor of claim 1, wherein the AlGaN capping layer further comprises a third sublayer of intrinsic c-phase A l x Ga 1x N disposed on the second sublayer, wherein the third sublayer is of a third thickness. Original
The transistor of claim 1, wherein the fourth thickness is between approximately 1 nm and 10 nm. Original
The transistor of claim 1, wherein aluminum content, x, of the AlGaN capping layer is between approximately 10% and 50% of total content. Original
The transistor of claim 1, wherein the dopant is a p-type impurity, and the aluminum content, x, of the AlGaN capping layer is between approximately 38% and 42% of total content. Original
The transistor of claim 1, wherein the dopant is an n-type impurity, and wherein the aluminum content, x, of the AlGaN capping layer is between approximately 23% and 27% of total content. Original
The transistor of claim 1, wherein the gate electrode is made of a metal selected from one of Pt, Ni, Cu, W, Ti, TiN, or a combination thereof, which comprises a work function greater than 4V. Original
The transistor of claim 1, further comprising: a first GaN contact region disposed between the c-phase GaN substrate and the source electrode to create a first ohmic contact between the source electrode and the first GaN contact region; and a second GaN contact region disposed between the c-phase GaN substrate and the drain electrode to create a second ohmic contact between the drain electrode and the second GaN contact region, and wherein the AlGaN capping layer is disposed between the first GaN contact region and the second GaN contact region. Original
The transistor of claim 1, wherein the dopant is a p-type impurity, and wherein the source electrode and the drain electrode are made of a metal comprising one of Ni, Pt, Au, Pb, or a combination thereof. Original
The transistor of claim 1, wherein the dopant is an n-type impurity, and wherein the source electrode and the drain electrode are of a metal comprising one of Ti, Al, Pd, Ag, Nd, or a combination thereof. Original
(Cu rr ently amended) A complementary logic circuit comprising a first of the transistor of claim 1, wherein the second sublayer is n-doped and a second of the transistor of claim 1, wherein the second sublayer is p-doped. Currently amended
(Cu rr ently amended) A normally-off, heterojunction field effect transistor, comprising: SVG 15703850.08-27-2018.JLCJPIT₂RXEAPX4.CLM.2.svg 0.16 3.87 Black and white an aluminum gallium nitride (AlGaN) capping layer disposed on the c-GaN substrate, wherein the AlGaN capping layer comprises: a first sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; a second sublayer of doped c-phase A lx Ga 1 x N disposed on the first sublayer, wherein the second sublayer is of a second thickness and is doped with a dopant; and a third sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the second sublayer, wherein the third sublayer is of a third thickness; Application No.: 15/703,850 -5- Attorney Docket No.: 30831.40 (L0040) an insulating layer disposed on an entirety of the third sublayer, wherein the insulating layer is of a fourth thickness; a source electrode positioned adjacent to a first side of the insulating layer; a drain electrode positioned adjacent to a second side of the insulating layer opposite from the first side; and a gate electrode disposed on the insulating layer and positioned between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode are connectable to function as a logic device. Currently amended
(Cu rr ently amended) A complementary logic circuit comprising a first of the transistor of claim 18, wherein the second sublayer is n-doped and a second of the transistor of claim 18, wherein the second sublayer is p-doped. Currently amended
The transistor of claim 18, wherein the fourth thickness is between approximately 1 nm and 10 nm. New
The transistor of claim 18, wherein the dopant is an n-type impurity within a delta-doped layer, the dopant comprising one of silicon, germanium, or a combination thereof. New
- 20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
normally-off heterojunction FET (2-sublayer AlGaN cap)
complementary logic circuit (n- and p-channel FETs, 2-sublayer)
No layer stack recorded.
normally-off heterojunction FET (3-sublayer AlGaN cap)
Materials described outside the worked examples.
cubic-phase gallium nitride substrate
GaN
aluminum gallium nitride capping layer
AlxGa₁-xN
insulating layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–9 nm | — |
Voltage |
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US 10,211,328Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 D is a diagram illustrating an alternative substrate for use in building the c-GaN FET illustrated in Figure l A, according to various embodiments.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 9 is a diagram illustrating layers of a p-channel, cubic gallium nitride (c-GaN) field-effect transistor (FET), as a function of various embodiments.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 14A is the diagram of
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 15 is a graph illustrating both conduction band offset and valence band offset of, respectively, the conduction and valence bands of the A l GaN capping layer, according to various embodiments.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 20 is an electrical schematic diagram of a ring oscillator using the disclosed c-GaN FETs within a series of inverters, according to one embodiment.
Figures 21A and 21B are graphs illustrating simulation of the ring oscillator of
Figure 22 is an electrical schematic diagram of one of the inverters of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently amended) A normally-off, heterojunction field effect transistor, comprising: SVG 15703850.08-27-2018.JLCJPIT₂RXEAPX4.CLM.1.svg 0.16 3.87 Black and white an aluminum gallium nitride (AlGaN) capping layer disposed on the c-GaN substrate, wherein the AlGaN capping layer comprises: a first sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; and a second sublayer of doped c-phase A lx Ga 1 -x N disposed on the first sublayer, wherein the second sublayer is of a second thickness and is doped with a dopant; an insulating layer disposed on an entirety of the AlGaN capping layer, wherein the insulating layer is of a fourth thickness; a source electrode positioned adjacent a first side of the insulating layer; a drain electrode positioned adjacent a second side of the insulating layer opposite from the first side; and a gate electrode disposed on the insulating layer and positioned between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode are connectable to function as a logic device. Currently amended
The transistor of claim 1, wherein the dopant is a p-type impurity within a delta-doped layer, the dopant comprising one of magnesium, carbon, or a combination thereof. Original
The transistor of claim 1, wherein the dopant is an n-type impurity within a delta-doped layer, the dopant comprising one of silicon, germanium, or a combination thereof. Original
The transistor of claim 1, wherein the insulating layer is of a material comprising one of A l N, SiO 2, SiN, HfO 2, Zr O 2, A₁ 2 0, or a combination thereof. Original
The transistor of claim 1, wherein the first thickness is between approximately 2 nm and 10 nm. Original
The transistor of claim 1, wherein the second thickness is between approximately 1 nm and 5 nm. Original
The transistor of claim 1, wherein the AlGaN capping layer further comprises a third sublayer of intrinsic c-phase A l x Ga 1x N disposed on the second sublayer, wherein the third sublayer is of a third thickness. Original
The transistor of claim 1, wherein the fourth thickness is between approximately 1 nm and 10 nm. Original
The transistor of claim 1, wherein aluminum content, x, of the AlGaN capping layer is between approximately 10% and 50% of total content. Original
The transistor of claim 1, wherein the dopant is a p-type impurity, and the aluminum content, x, of the AlGaN capping layer is between approximately 38% and 42% of total content. Original
The transistor of claim 1, wherein the dopant is an n-type impurity, and wherein the aluminum content, x, of the AlGaN capping layer is between approximately 23% and 27% of total content. Original
The transistor of claim 1, wherein the gate electrode is made of a metal selected from one of Pt, Ni, Cu, W, Ti, TiN, or a combination thereof, which comprises a work function greater than 4V. Original
The transistor of claim 1, further comprising: a first GaN contact region disposed between the c-phase GaN substrate and the source electrode to create a first ohmic contact between the source electrode and the first GaN contact region; and a second GaN contact region disposed between the c-phase GaN substrate and the drain electrode to create a second ohmic contact between the drain electrode and the second GaN contact region, and wherein the AlGaN capping layer is disposed between the first GaN contact region and the second GaN contact region. Original
The transistor of claim 1, wherein the dopant is a p-type impurity, and wherein the source electrode and the drain electrode are made of a metal comprising one of Ni, Pt, Au, Pb, or a combination thereof. Original
The transistor of claim 1, wherein the dopant is an n-type impurity, and wherein the source electrode and the drain electrode are of a metal comprising one of Ti, Al, Pd, Ag, Nd, or a combination thereof. Original
(Cu rr ently amended) A complementary logic circuit comprising a first of the transistor of claim 1, wherein the second sublayer is n-doped and a second of the transistor of claim 1, wherein the second sublayer is p-doped. Currently amended
(Cu rr ently amended) A normally-off, heterojunction field effect transistor, comprising: SVG 15703850.08-27-2018.JLCJPIT₂RXEAPX4.CLM.2.svg 0.16 3.87 Black and white an aluminum gallium nitride (AlGaN) capping layer disposed on the c-GaN substrate, wherein the AlGaN capping layer comprises: a first sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; a second sublayer of doped c-phase A lx Ga 1 x N disposed on the first sublayer, wherein the second sublayer is of a second thickness and is doped with a dopant; and a third sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the second sublayer, wherein the third sublayer is of a third thickness; Application No.: 15/703,850 -5- Attorney Docket No.: 30831.40 (L0040) an insulating layer disposed on an entirety of the third sublayer, wherein the insulating layer is of a fourth thickness; a source electrode positioned adjacent to a first side of the insulating layer; a drain electrode positioned adjacent to a second side of the insulating layer opposite from the first side; and a gate electrode disposed on the insulating layer and positioned between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode are connectable to function as a logic device. Currently amended
(Cu rr ently amended) A complementary logic circuit comprising a first of the transistor of claim 18, wherein the second sublayer is n-doped and a second of the transistor of claim 18, wherein the second sublayer is p-doped. Currently amended
The transistor of claim 18, wherein the fourth thickness is between approximately 1 nm and 10 nm. New
The transistor of claim 18, wherein the dopant is an n-type impurity within a delta-doped layer, the dopant comprising one of silicon, germanium, or a combination thereof. New
- 20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
normally-off heterojunction FET (2-sublayer AlGaN cap)
complementary logic circuit (n- and p-channel FETs, 2-sublayer)
No layer stack recorded.
normally-off heterojunction FET (3-sublayer AlGaN cap)
Materials described outside the worked examples.
cubic-phase gallium nitride substrate
GaN
aluminum gallium nitride capping layer
AlxGa₁-xN
insulating layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–9 nm | — |
Voltage |
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US 10,211,328Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 D is a diagram illustrating an alternative substrate for use in building the c-GaN FET illustrated in Figure l A, according to various embodiments.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 9 is a diagram illustrating layers of a p-channel, cubic gallium nitride (c-GaN) field-effect transistor (FET), as a function of various embodiments.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 14A is the diagram of
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 15 is a graph illustrating both conduction band offset and valence band offset of, respectively, the conduction and valence bands of the A l GaN capping layer, according to various embodiments.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 20 is an electrical schematic diagram of a ring oscillator using the disclosed c-GaN FETs within a series of inverters, according to one embodiment.
Figures 21A and 21B are graphs illustrating simulation of the ring oscillator of
Figure 22 is an electrical schematic diagram of one of the inverters of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently amended) A normally-off, heterojunction field effect transistor, comprising: SVG 15703850.08-27-2018.JLCJPIT₂RXEAPX4.CLM.1.svg 0.16 3.87 Black and white an aluminum gallium nitride (AlGaN) capping layer disposed on the c-GaN substrate, wherein the AlGaN capping layer comprises: a first sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; and a second sublayer of doped c-phase A lx Ga 1 -x N disposed on the first sublayer, wherein the second sublayer is of a second thickness and is doped with a dopant; an insulating layer disposed on an entirety of the AlGaN capping layer, wherein the insulating layer is of a fourth thickness; a source electrode positioned adjacent a first side of the insulating layer; a drain electrode positioned adjacent a second side of the insulating layer opposite from the first side; and a gate electrode disposed on the insulating layer and positioned between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode are connectable to function as a logic device. Currently amended
The transistor of claim 1, wherein the dopant is a p-type impurity within a delta-doped layer, the dopant comprising one of magnesium, carbon, or a combination thereof. Original
The transistor of claim 1, wherein the dopant is an n-type impurity within a delta-doped layer, the dopant comprising one of silicon, germanium, or a combination thereof. Original
The transistor of claim 1, wherein the insulating layer is of a material comprising one of A l N, SiO 2, SiN, HfO 2, Zr O 2, A₁ 2 0, or a combination thereof. Original
The transistor of claim 1, wherein the first thickness is between approximately 2 nm and 10 nm. Original
The transistor of claim 1, wherein the second thickness is between approximately 1 nm and 5 nm. Original
The transistor of claim 1, wherein the AlGaN capping layer further comprises a third sublayer of intrinsic c-phase A l x Ga 1x N disposed on the second sublayer, wherein the third sublayer is of a third thickness. Original
The transistor of claim 1, wherein the fourth thickness is between approximately 1 nm and 10 nm. Original
The transistor of claim 1, wherein aluminum content, x, of the AlGaN capping layer is between approximately 10% and 50% of total content. Original
The transistor of claim 1, wherein the dopant is a p-type impurity, and the aluminum content, x, of the AlGaN capping layer is between approximately 38% and 42% of total content. Original
The transistor of claim 1, wherein the dopant is an n-type impurity, and wherein the aluminum content, x, of the AlGaN capping layer is between approximately 23% and 27% of total content. Original
The transistor of claim 1, wherein the gate electrode is made of a metal selected from one of Pt, Ni, Cu, W, Ti, TiN, or a combination thereof, which comprises a work function greater than 4V. Original
The transistor of claim 1, further comprising: a first GaN contact region disposed between the c-phase GaN substrate and the source electrode to create a first ohmic contact between the source electrode and the first GaN contact region; and a second GaN contact region disposed between the c-phase GaN substrate and the drain electrode to create a second ohmic contact between the drain electrode and the second GaN contact region, and wherein the AlGaN capping layer is disposed between the first GaN contact region and the second GaN contact region. Original
The transistor of claim 1, wherein the dopant is a p-type impurity, and wherein the source electrode and the drain electrode are made of a metal comprising one of Ni, Pt, Au, Pb, or a combination thereof. Original
The transistor of claim 1, wherein the dopant is an n-type impurity, and wherein the source electrode and the drain electrode are of a metal comprising one of Ti, Al, Pd, Ag, Nd, or a combination thereof. Original
(Cu rr ently amended) A complementary logic circuit comprising a first of the transistor of claim 1, wherein the second sublayer is n-doped and a second of the transistor of claim 1, wherein the second sublayer is p-doped. Currently amended
(Cu rr ently amended) A normally-off, heterojunction field effect transistor, comprising: SVG 15703850.08-27-2018.JLCJPIT₂RXEAPX4.CLM.2.svg 0.16 3.87 Black and white an aluminum gallium nitride (AlGaN) capping layer disposed on the c-GaN substrate, wherein the AlGaN capping layer comprises: a first sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; a second sublayer of doped c-phase A lx Ga 1 x N disposed on the first sublayer, wherein the second sublayer is of a second thickness and is doped with a dopant; and a third sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the second sublayer, wherein the third sublayer is of a third thickness; Application No.: 15/703,850 -5- Attorney Docket No.: 30831.40 (L0040) an insulating layer disposed on an entirety of the third sublayer, wherein the insulating layer is of a fourth thickness; a source electrode positioned adjacent to a first side of the insulating layer; a drain electrode positioned adjacent to a second side of the insulating layer opposite from the first side; and a gate electrode disposed on the insulating layer and positioned between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode are connectable to function as a logic device. Currently amended
(Cu rr ently amended) A complementary logic circuit comprising a first of the transistor of claim 18, wherein the second sublayer is n-doped and a second of the transistor of claim 18, wherein the second sublayer is p-doped. Currently amended
The transistor of claim 18, wherein the fourth thickness is between approximately 1 nm and 10 nm. New
The transistor of claim 18, wherein the dopant is an n-type impurity within a delta-doped layer, the dopant comprising one of silicon, germanium, or a combination thereof. New
- 20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
normally-off heterojunction FET (2-sublayer AlGaN cap)
complementary logic circuit (n- and p-channel FETs, 2-sublayer)
No layer stack recorded.
normally-off heterojunction FET (3-sublayer AlGaN cap)
Materials described outside the worked examples.
cubic-phase gallium nitride substrate
GaN
aluminum gallium nitride capping layer
AlxGa₁-xN
insulating layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–9 nm | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
PASSIVE LAYER FOR ATTENUATION OF NEAR-FIELD ELECTROMAGNETIC WAVES AND HEATDISSIPATION INCLUDING GRAPHENE, AND ELECTROMAGNETIC DEVICE INCLUDING THE SAME
EPITAXIAL GALLIUM NITRIDE BASED LIGHT EMITTING DIODE AND METHOD OF MAKING THEREOF
Patent
Atlas literature
Patent
US 10,211,328Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 D is a diagram illustrating an alternative substrate for use in building the c-GaN FET illustrated in Figure l A, according to various embodiments.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 9 is a diagram illustrating layers of a p-channel, cubic gallium nitride (c-GaN) field-effect transistor (FET), as a function of various embodiments.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 14A is the diagram of
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 15 is a graph illustrating both conduction band offset and valence band offset of, respectively, the conduction and valence bands of the A l GaN capping layer, according to various embodiments.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 20 is an electrical schematic diagram of a ring oscillator using the disclosed c-GaN FETs within a series of inverters, according to one embodiment.
Figures 21A and 21B are graphs illustrating simulation of the ring oscillator of
Figure 22 is an electrical schematic diagram of one of the inverters of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently amended) A normally-off, heterojunction field effect transistor, comprising: SVG 15703850.08-27-2018.JLCJPIT₂RXEAPX4.CLM.1.svg 0.16 3.87 Black and white an aluminum gallium nitride (AlGaN) capping layer disposed on the c-GaN substrate, wherein the AlGaN capping layer comprises: a first sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; and a second sublayer of doped c-phase A lx Ga 1 -x N disposed on the first sublayer, wherein the second sublayer is of a second thickness and is doped with a dopant; an insulating layer disposed on an entirety of the AlGaN capping layer, wherein the insulating layer is of a fourth thickness; a source electrode positioned adjacent a first side of the insulating layer; a drain electrode positioned adjacent a second side of the insulating layer opposite from the first side; and a gate electrode disposed on the insulating layer and positioned between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode are connectable to function as a logic device. Currently amended
The transistor of claim 1, wherein the dopant is a p-type impurity within a delta-doped layer, the dopant comprising one of magnesium, carbon, or a combination thereof. Original
The transistor of claim 1, wherein the dopant is an n-type impurity within a delta-doped layer, the dopant comprising one of silicon, germanium, or a combination thereof. Original
The transistor of claim 1, wherein the insulating layer is of a material comprising one of A l N, SiO 2, SiN, HfO 2, Zr O 2, A₁ 2 0, or a combination thereof. Original
The transistor of claim 1, wherein the first thickness is between approximately 2 nm and 10 nm. Original
The transistor of claim 1, wherein the second thickness is between approximately 1 nm and 5 nm. Original
The transistor of claim 1, wherein the AlGaN capping layer further comprises a third sublayer of intrinsic c-phase A l x Ga 1x N disposed on the second sublayer, wherein the third sublayer is of a third thickness. Original
The transistor of claim 1, wherein the fourth thickness is between approximately 1 nm and 10 nm. Original
The transistor of claim 1, wherein aluminum content, x, of the AlGaN capping layer is between approximately 10% and 50% of total content. Original
The transistor of claim 1, wherein the dopant is a p-type impurity, and the aluminum content, x, of the AlGaN capping layer is between approximately 38% and 42% of total content. Original
The transistor of claim 1, wherein the dopant is an n-type impurity, and wherein the aluminum content, x, of the AlGaN capping layer is between approximately 23% and 27% of total content. Original
The transistor of claim 1, wherein the gate electrode is made of a metal selected from one of Pt, Ni, Cu, W, Ti, TiN, or a combination thereof, which comprises a work function greater than 4V. Original
The transistor of claim 1, further comprising: a first GaN contact region disposed between the c-phase GaN substrate and the source electrode to create a first ohmic contact between the source electrode and the first GaN contact region; and a second GaN contact region disposed between the c-phase GaN substrate and the drain electrode to create a second ohmic contact between the drain electrode and the second GaN contact region, and wherein the AlGaN capping layer is disposed between the first GaN contact region and the second GaN contact region. Original
The transistor of claim 1, wherein the dopant is a p-type impurity, and wherein the source electrode and the drain electrode are made of a metal comprising one of Ni, Pt, Au, Pb, or a combination thereof. Original
The transistor of claim 1, wherein the dopant is an n-type impurity, and wherein the source electrode and the drain electrode are of a metal comprising one of Ti, Al, Pd, Ag, Nd, or a combination thereof. Original
(Cu rr ently amended) A complementary logic circuit comprising a first of the transistor of claim 1, wherein the second sublayer is n-doped and a second of the transistor of claim 1, wherein the second sublayer is p-doped. Currently amended
(Cu rr ently amended) A normally-off, heterojunction field effect transistor, comprising: SVG 15703850.08-27-2018.JLCJPIT₂RXEAPX4.CLM.2.svg 0.16 3.87 Black and white an aluminum gallium nitride (AlGaN) capping layer disposed on the c-GaN substrate, wherein the AlGaN capping layer comprises: a first sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; a second sublayer of doped c-phase A lx Ga 1 x N disposed on the first sublayer, wherein the second sublayer is of a second thickness and is doped with a dopant; and a third sublayer of intrinsic c-phase A l x Ga 1 _ x N disposed on the second sublayer, wherein the third sublayer is of a third thickness; Application No.: 15/703,850 -5- Attorney Docket No.: 30831.40 (L0040) an insulating layer disposed on an entirety of the third sublayer, wherein the insulating layer is of a fourth thickness; a source electrode positioned adjacent to a first side of the insulating layer; a drain electrode positioned adjacent to a second side of the insulating layer opposite from the first side; and a gate electrode disposed on the insulating layer and positioned between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the gate electrode are connectable to function as a logic device. Currently amended
(Cu rr ently amended) A complementary logic circuit comprising a first of the transistor of claim 18, wherein the second sublayer is n-doped and a second of the transistor of claim 18, wherein the second sublayer is p-doped. Currently amended
The transistor of claim 18, wherein the fourth thickness is between approximately 1 nm and 10 nm. New
The transistor of claim 18, wherein the dopant is an n-type impurity within a delta-doped layer, the dopant comprising one of silicon, germanium, or a combination thereof. New
- 20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
normally-off heterojunction FET (2-sublayer AlGaN cap)
complementary logic circuit (n- and p-channel FETs, 2-sublayer)
No layer stack recorded.
normally-off heterojunction FET (3-sublayer AlGaN cap)
Materials described outside the worked examples.
cubic-phase gallium nitride substrate
GaN
aluminum gallium nitride capping layer
AlxGa₁-xN
insulating layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–9 nm | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
PASSIVE LAYER FOR ATTENUATION OF NEAR-FIELD ELECTROMAGNETIC WAVES AND HEATDISSIPATION INCLUDING GRAPHENE, AND ELECTROMAGNETIC DEVICE INCLUDING THE SAME
EPITAXIAL GALLIUM NITRIDE BASED LIGHT EMITTING DIODE AND METHOD OF MAKING THEREOF
complementary logic circuit (n- and p-channel FETs, 3-sublayer)
No layer stack recorded.
p-type dopant (magnesium or carbon)
n-type dopant (silicon or germanium)
insulating layer material
gate electrode metal (Pt, Ni, Cu, W, Ti, or TiN)
source/drain electrode metal for p-type (Ni, Pt, Au, or Pb)
source/drain electrode metal for n-type (Ti, Al, Pd, Ag, or Nd)
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 D is a diagram illustrating an alternative substrate for use in building the c-GaN FET illustrated in Figure l A, according to various embodiments.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 9 is a diagram illustrating layers of a p-channel, cubic gallium nitride (c-GaN) field-effect transistor (FET), as a function of various embodiments.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 15 is a graph illustrating both conduction band offset and valence band offset of, respectively, the conduction and valence bands of the A l GaN capping layer, according to various embodiments.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 20 is an electrical schematic diagram of a ring oscillator using the disclosed c-GaN FETs within a series of inverters, according to one embodiment.
Figure 22 is an electrical schematic diagram of one of the inverters of
| — |
— | 4.33–5.27 eV | — |
Thickness | 5–25 nm | — |
— | ≥ 10 W | — |
Temperature | ≥ 200 °C | — |
Voltage | ≥ 4.55 V | — |
Thickness | 2–10 nm | — |
Thickness | 1–5 nm | — |
Thickness | 10–25 nm | — |
Thickness | 1–10 nm | — |
Voltage | ≥ 4 V | — |
complementary logic circuit (n- and p-channel FETs, 3-sublayer)
No layer stack recorded.
p-type dopant (magnesium or carbon)
n-type dopant (silicon or germanium)
insulating layer material
gate electrode metal (Pt, Ni, Cu, W, Ti, or TiN)
source/drain electrode metal for p-type (Ni, Pt, Au, or Pb)
source/drain electrode metal for n-type (Ti, Al, Pd, Ag, or Nd)
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 D is a diagram illustrating an alternative substrate for use in building the c-GaN FET illustrated in Figure l A, according to various embodiments.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 9 is a diagram illustrating layers of a p-channel, cubic gallium nitride (c-GaN) field-effect transistor (FET), as a function of various embodiments.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 15 is a graph illustrating both conduction band offset and valence band offset of, respectively, the conduction and valence bands of the A l GaN capping layer, according to various embodiments.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 20 is an electrical schematic diagram of a ring oscillator using the disclosed c-GaN FETs within a series of inverters, according to one embodiment.
Figure 22 is an electrical schematic diagram of one of the inverters of
| — |
— | 4.33–5.27 eV | — |
Thickness | 5–25 nm | — |
— | ≥ 10 W | — |
Temperature | ≥ 200 °C | — |
Voltage | ≥ 4.55 V | — |
Thickness | 2–10 nm | — |
Thickness | 1–5 nm | — |
Thickness | 10–25 nm | — |
Thickness | 1–10 nm | — |
Voltage | ≥ 4 V | — |
complementary logic circuit (n- and p-channel FETs, 3-sublayer)
No layer stack recorded.
p-type dopant (magnesium or carbon)
n-type dopant (silicon or germanium)
insulating layer material
gate electrode metal (Pt, Ni, Cu, W, Ti, or TiN)
source/drain electrode metal for p-type (Ni, Pt, Au, or Pb)
source/drain electrode metal for n-type (Ti, Al, Pd, Ag, or Nd)
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 D is a diagram illustrating an alternative substrate for use in building the c-GaN FET illustrated in Figure l A, according to various embodiments.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 9 is a diagram illustrating layers of a p-channel, cubic gallium nitride (c-GaN) field-effect transistor (FET), as a function of various embodiments.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 15 is a graph illustrating both conduction band offset and valence band offset of, respectively, the conduction and valence bands of the A l GaN capping layer, according to various embodiments.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 20 is an electrical schematic diagram of a ring oscillator using the disclosed c-GaN FETs within a series of inverters, according to one embodiment.
Figure 22 is an electrical schematic diagram of one of the inverters of
| — |
— | 4.33–5.27 eV | — |
Thickness | 5–25 nm | — |
— | ≥ 10 W | — |
Temperature | ≥ 200 °C | — |
Voltage | ≥ 4.55 V | — |
Thickness | 2–10 nm | — |
Thickness | 1–5 nm | — |
Thickness | 10–25 nm | — |
Thickness | 1–10 nm | — |
Voltage | ≥ 4 V | — |
complementary logic circuit (n- and p-channel FETs, 3-sublayer)
No layer stack recorded.
p-type dopant (magnesium or carbon)
n-type dopant (silicon or germanium)
insulating layer material
gate electrode metal (Pt, Ni, Cu, W, Ti, or TiN)
source/drain electrode metal for p-type (Ni, Pt, Au, or Pb)
source/drain electrode metal for n-type (Ti, Al, Pd, Ag, or Nd)
Figure 1 B is a more-detailed diagram of the cubic-GaN FET of Figure lA, further illustrating sublayers of the aluminum gallium nitride (A l GaN) capping layer, with first thickness (t i), second thickness (t 2), and third thickness (t 3), and a fourth thickness (t i es) of an optional insulating …
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 C is a graph illustrating an equilibrium band structure of the c-GaN FET illustrated in
Figure 1 D is a diagram illustrating an alternative substrate for use in building the c-GaN FET illustrated in Figure l A, according to various embodiments.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 2B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 3B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing second thickness (t 2) of the second Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 4B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of decreasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 5 B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6A is a graph illustrating simulation results of conduction band energy of the n-channel, c-GaN FET as a function of a decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 6B is a graph illustrating simulation results of electron concentration of the n-channel, c-GaN FET as a function of decreasing work function of gate metal, according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 7 is a graph illustrating turn on voltage of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and third thickness (t 3), according to one embodiment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 8 is a graph illustrating 2DEG density of the disclosed c-GaN FET without the optional insulating layer as a function of aluminum content and gate bias (V G S), a cco rding to o ne emb o diment.
Figure 9 is a diagram illustrating layers of a p-channel, cubic gallium nitride (c-GaN) field-effect transistor (FET), as a function of various embodiments.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 10 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of a decreasing first thickness (t i) of the first Al GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 11 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing second thickness (t 2) of the second A l GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 12 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of an increasing third thickness (t 3) of the third Al GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 13 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing S -doping of the second A l GaN sublayer, according to one embodiment.
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 14B is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing aluminum content of the A l GaN capping layer, according to one embodiment.
Figure 15 is a graph illustrating both conduction band offset and valence band offset of, respectively, the conduction and valence bands of the A l GaN capping layer, according to various embodiments.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 16 is a graph illustrating simulation results of valence band energy of the p-channel, c-GaN FET as a function of increasing work function of the gate metal of the gate electrode, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 17 is a graph illustrating simulation results of valence band energy and hole density of the p-channel, c-GaN FET as a function of gate bias, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 18 is a graph illustrating simulation of drain current versus drain bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 19 is a graph illustrating simulation results of drain current versus gate bias of the p-channel, c-GaN FET, according to one embodiment.
Figure 20 is an electrical schematic diagram of a ring oscillator using the disclosed c-GaN FETs within a series of inverters, according to one embodiment.
Figure 22 is an electrical schematic diagram of one of the inverters of
| — |
— | 4.33–5.27 eV | — |
Thickness | 5–25 nm | — |
— | ≥ 10 W | — |
Temperature | ≥ 200 °C | — |
Voltage | ≥ 4.55 V | — |
Thickness | 2–10 nm | — |
Thickness | 1–5 nm | — |
Thickness | 10–25 nm | — |
Thickness | 1–10 nm | — |
Voltage | ≥ 4 V | — |