Patent
US 12,154,982 B2GALLIUM NITRIDE TRANSISTOR
Göhkan Atmaca
Commissariat a` l’E´ nergie Atomique et aux E´ nergies Alternatives, Paris (FR)·Nov. 26, 2024·US
Copyright © 2026 Matter42. All rights reserved.
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US 12,154,982 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (described above) is a cross-section view of a device described in the publication by I. Hwang et al. cited in the background section;
FIG. 2 is a graph plotting drain current Id and gate current Ig as a function of gate voltage Vgs for the device of
FIG. 3 for a gate voltage Vgs greater than a hole injection voltage VHoleInjection of the device;
FIG. 4A is a cross-section view of an HEMT device without any layer of p-InGaN for a gate voltage Vgs below the threshold voltage Vth1 of the device;
FIG. 5B is a cross-section view of the HEMT device of
FIG. 6B is a cross-section view of the HEMT device of 10
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 8A is a graph representing conduction band energy Ec in line with the gate of the devices of
FIG. 9 is a graph representing 2DEG density in a channel of the devices of
FIG. 10A is a graph representing gate current Ig as a 25 function of gate-source voltage Vgs for the devices of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 15A is a graph representing gate current Ig as a function of the gate-source voltage Vgs of the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
FIG. 17 is a cross-section view of an HEMT device similar to the one of
FIG. 65 4A, and of the device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device comprising: a layer of aluminum gallium nitride (AlGaN) extending between a source and a drain of the device; a gallium nitride (GaN) channel layer extending under the layer of AlGaN; a gate stack comprising a layer of p-doped GaN; and a layer of p-doped indium gallium nitride (InGaN) of at least 5 nm in thickness positioned between the layer of AlGaN and the layer of p-doped GaN, the layer of p-doped InGaN having a length greater than a length of the gate stack and of the layer of p-doped GaN, wherein a drain-side edge of the layer of p-doped InGaN is separated from the drain and/or a source-side edge of the layer of p-doped InGaN is separated from the source.
The transistor device of claim 1, wherein the length of the layer of p-doped InGaN is of at least 6 µm.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an Mg doping concentration of at least 5×1018 cm⁻³.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an In mole faction of at least 0.05.
The transistor device of claim 1, wherein the layer of p-doped InGaN extends beyond a drain-side edge of the gate stack by at least 2.0 µm, the layer of p-doped InGaN being aligned on a side of the source with a source edge of the gate stack.
The transistor device of claim 1, wherein the drain-side edge of the layer of p-doped InGaN is separated from the drain by a spacing of at least 4.0 µm.
The transistor device of claim 1, wherein the gate stack comprises a gate metal of Ni, W, or TiN.
The transistor device of claim 1, wherein the layer of p-doped InGaN has a thickness of 7.5 nm or less.
The transistor device of claim 1, comprising a source field plate extending from the source over the gate stack.
An integrated circuit comprising at least one transistor device according to claim 1.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an Mg doping concentration of at least 7.5×1018 cm⁻³.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an In mole faction of between 0.10 and 0.20. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN gate HEMT with p-InGaN interlayer
Materials described outside the worked examples.
aluminum gallium nitride
AlGaN
Al0.25Ga0.75N barrier layer
Al0.25Ga0.75N
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph plotting drain current Id and gate current Ig as a function of gate voltage Vgs for the device of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage Vth (Ni gate p-GaN HEMT, prior art) | 1.23 V | — |
Threshold voltage Vth (W gate p-GaN HEMT, prior art) | 3.03 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 7
Related documents with shared materials, methods, properties, or citations.
Patent
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Patent
US 12,154,982 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (described above) is a cross-section view of a device described in the publication by I. Hwang et al. cited in the background section;
FIG. 2 is a graph plotting drain current Id and gate current Ig as a function of gate voltage Vgs for the device of
FIG. 3 for a gate voltage Vgs greater than a hole injection voltage VHoleInjection of the device;
FIG. 4A is a cross-section view of an HEMT device without any layer of p-InGaN for a gate voltage Vgs below the threshold voltage Vth1 of the device;
FIG. 5B is a cross-section view of the HEMT device of
FIG. 6B is a cross-section view of the HEMT device of 10
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 8A is a graph representing conduction band energy Ec in line with the gate of the devices of
FIG. 9 is a graph representing 2DEG density in a channel of the devices of
FIG. 10A is a graph representing gate current Ig as a 25 function of gate-source voltage Vgs for the devices of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 15A is a graph representing gate current Ig as a function of the gate-source voltage Vgs of the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
FIG. 17 is a cross-section view of an HEMT device similar to the one of
FIG. 65 4A, and of the device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device comprising: a layer of aluminum gallium nitride (AlGaN) extending between a source and a drain of the device; a gallium nitride (GaN) channel layer extending under the layer of AlGaN; a gate stack comprising a layer of p-doped GaN; and a layer of p-doped indium gallium nitride (InGaN) of at least 5 nm in thickness positioned between the layer of AlGaN and the layer of p-doped GaN, the layer of p-doped InGaN having a length greater than a length of the gate stack and of the layer of p-doped GaN, wherein a drain-side edge of the layer of p-doped InGaN is separated from the drain and/or a source-side edge of the layer of p-doped InGaN is separated from the source.
The transistor device of claim 1, wherein the length of the layer of p-doped InGaN is of at least 6 µm.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an Mg doping concentration of at least 5×1018 cm⁻³.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an In mole faction of at least 0.05.
The transistor device of claim 1, wherein the layer of p-doped InGaN extends beyond a drain-side edge of the gate stack by at least 2.0 µm, the layer of p-doped InGaN being aligned on a side of the source with a source edge of the gate stack.
The transistor device of claim 1, wherein the drain-side edge of the layer of p-doped InGaN is separated from the drain by a spacing of at least 4.0 µm.
The transistor device of claim 1, wherein the gate stack comprises a gate metal of Ni, W, or TiN.
The transistor device of claim 1, wherein the layer of p-doped InGaN has a thickness of 7.5 nm or less.
The transistor device of claim 1, comprising a source field plate extending from the source over the gate stack.
An integrated circuit comprising at least one transistor device according to claim 1.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an Mg doping concentration of at least 7.5×1018 cm⁻³.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an In mole faction of between 0.10 and 0.20. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN gate HEMT with p-InGaN interlayer
Materials described outside the worked examples.
aluminum gallium nitride
AlGaN
Al0.25Ga0.75N barrier layer
Al0.25Ga0.75N
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph plotting drain current Id and gate current Ig as a function of gate voltage Vgs for the device of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage Vth (Ni gate p-GaN HEMT, prior art) | 1.23 V | — |
Threshold voltage Vth (W gate p-GaN HEMT, prior art) | 3.03 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,154,982 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (described above) is a cross-section view of a device described in the publication by I. Hwang et al. cited in the background section;
FIG. 2 is a graph plotting drain current Id and gate current Ig as a function of gate voltage Vgs for the device of
FIG. 3 for a gate voltage Vgs greater than a hole injection voltage VHoleInjection of the device;
FIG. 4A is a cross-section view of an HEMT device without any layer of p-InGaN for a gate voltage Vgs below the threshold voltage Vth1 of the device;
FIG. 5B is a cross-section view of the HEMT device of
FIG. 6B is a cross-section view of the HEMT device of 10
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 8A is a graph representing conduction band energy Ec in line with the gate of the devices of
FIG. 9 is a graph representing 2DEG density in a channel of the devices of
FIG. 10A is a graph representing gate current Ig as a 25 function of gate-source voltage Vgs for the devices of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 15A is a graph representing gate current Ig as a function of the gate-source voltage Vgs of the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
FIG. 17 is a cross-section view of an HEMT device similar to the one of
FIG. 65 4A, and of the device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device comprising: a layer of aluminum gallium nitride (AlGaN) extending between a source and a drain of the device; a gallium nitride (GaN) channel layer extending under the layer of AlGaN; a gate stack comprising a layer of p-doped GaN; and a layer of p-doped indium gallium nitride (InGaN) of at least 5 nm in thickness positioned between the layer of AlGaN and the layer of p-doped GaN, the layer of p-doped InGaN having a length greater than a length of the gate stack and of the layer of p-doped GaN, wherein a drain-side edge of the layer of p-doped InGaN is separated from the drain and/or a source-side edge of the layer of p-doped InGaN is separated from the source.
The transistor device of claim 1, wherein the length of the layer of p-doped InGaN is of at least 6 µm.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an Mg doping concentration of at least 5×1018 cm⁻³.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an In mole faction of at least 0.05.
The transistor device of claim 1, wherein the layer of p-doped InGaN extends beyond a drain-side edge of the gate stack by at least 2.0 µm, the layer of p-doped InGaN being aligned on a side of the source with a source edge of the gate stack.
The transistor device of claim 1, wherein the drain-side edge of the layer of p-doped InGaN is separated from the drain by a spacing of at least 4.0 µm.
The transistor device of claim 1, wherein the gate stack comprises a gate metal of Ni, W, or TiN.
The transistor device of claim 1, wherein the layer of p-doped InGaN has a thickness of 7.5 nm or less.
The transistor device of claim 1, comprising a source field plate extending from the source over the gate stack.
An integrated circuit comprising at least one transistor device according to claim 1.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an Mg doping concentration of at least 7.5×1018 cm⁻³.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an In mole faction of between 0.10 and 0.20. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN gate HEMT with p-InGaN interlayer
Materials described outside the worked examples.
aluminum gallium nitride
AlGaN
Al0.25Ga0.75N barrier layer
Al0.25Ga0.75N
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph plotting drain current Id and gate current Ig as a function of gate voltage Vgs for the device of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage Vth (Ni gate p-GaN HEMT, prior art) | 1.23 V | — |
Threshold voltage Vth (W gate p-GaN HEMT, prior art) | 3.03 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,154,982 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 (described above) is a cross-section view of a device described in the publication by I. Hwang et al. cited in the background section;
FIG. 2 is a graph plotting drain current Id and gate current Ig as a function of gate voltage Vgs for the device of
FIG. 3 for a gate voltage Vgs greater than a hole injection voltage VHoleInjection of the device;
FIG. 4A is a cross-section view of an HEMT device without any layer of p-InGaN for a gate voltage Vgs below the threshold voltage Vth1 of the device;
FIG. 5B is a cross-section view of the HEMT device of
FIG. 6B is a cross-section view of the HEMT device of 10
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 8A is a graph representing conduction band energy Ec in line with the gate of the devices of
FIG. 9 is a graph representing 2DEG density in a channel of the devices of
FIG. 10A is a graph representing gate current Ig as a 25 function of gate-source voltage Vgs for the devices of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 15A is a graph representing gate current Ig as a function of the gate-source voltage Vgs of the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
FIG. 17 is a cross-section view of an HEMT device similar to the one of
FIG. 65 4A, and of the device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device comprising: a layer of aluminum gallium nitride (AlGaN) extending between a source and a drain of the device; a gallium nitride (GaN) channel layer extending under the layer of AlGaN; a gate stack comprising a layer of p-doped GaN; and a layer of p-doped indium gallium nitride (InGaN) of at least 5 nm in thickness positioned between the layer of AlGaN and the layer of p-doped GaN, the layer of p-doped InGaN having a length greater than a length of the gate stack and of the layer of p-doped GaN, wherein a drain-side edge of the layer of p-doped InGaN is separated from the drain and/or a source-side edge of the layer of p-doped InGaN is separated from the source.
The transistor device of claim 1, wherein the length of the layer of p-doped InGaN is of at least 6 µm.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an Mg doping concentration of at least 5×1018 cm⁻³.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an In mole faction of at least 0.05.
The transistor device of claim 1, wherein the layer of p-doped InGaN extends beyond a drain-side edge of the gate stack by at least 2.0 µm, the layer of p-doped InGaN being aligned on a side of the source with a source edge of the gate stack.
The transistor device of claim 1, wherein the drain-side edge of the layer of p-doped InGaN is separated from the drain by a spacing of at least 4.0 µm.
The transistor device of claim 1, wherein the gate stack comprises a gate metal of Ni, W, or TiN.
The transistor device of claim 1, wherein the layer of p-doped InGaN has a thickness of 7.5 nm or less.
The transistor device of claim 1, comprising a source field plate extending from the source over the gate stack.
An integrated circuit comprising at least one transistor device according to claim 1.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an Mg doping concentration of at least 7.5×1018 cm⁻³.
The transistor device of claim 1, wherein the layer of p-doped InGaN has an In mole faction of between 0.10 and 0.20. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN gate HEMT with p-InGaN interlayer
Materials described outside the worked examples.
aluminum gallium nitride
AlGaN
Al0.25Ga0.75N barrier layer
Al0.25Ga0.75N
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph plotting drain current Id and gate current Ig as a function of gate voltage Vgs for the device of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage Vth (Ni gate p-GaN HEMT, prior art) | 1.23 V | — |
Threshold voltage Vth (W gate p-GaN HEMT, prior art) | 3.03 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 7
Related documents with shared materials, methods, properties, or citations.
HEMT device 300 (embodiment with p-InGaN, Ni gate)
gallium nitride channel layer
GaN
p-doped gallium nitride gate layer
p-GaN
p-doped indium gallium nitride
p-InGaN
gate metal (Ni, W, or TiN)
nickel gate metal
Ni
silicon substrate
Si
silicon nitride
SiN
FIG. 3 for a gate voltage Vgs greater than a hole injection voltage VHoleInjection of the device;
FIG. 4A is a cross-section view of an HEMT device without any layer of p-InGaN for a gate voltage Vgs below the threshold voltage Vth1 of the device;
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 8A is a graph representing conduction band energy Ec in line with the gate of the devices of
FIG. 9 is a graph representing 2DEG density in a channel of the devices of
FIG. 10A is a graph representing gate current Ig as a 25 function of gate-source voltage Vgs for the devices of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 15A is a graph representing gate current Ig as a function of the gate-source voltage Vgs of the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
| — |
Voltage | 0–1 V | — |
Voltage | 4–5 V | — |
Thickness | 0.1–0.3 µm | — |
Thickness | 1–4 µm | — |
Thickness | ≥ 5 nm | — |
Thickness | ≥ 6 µm | — |
Thickness | ≥ 4 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 2 µm | — |
HEMT device 300 (embodiment with p-InGaN, Ni gate)
gallium nitride channel layer
GaN
p-doped gallium nitride gate layer
p-GaN
p-doped indium gallium nitride
p-InGaN
gate metal (Ni, W, or TiN)
nickel gate metal
Ni
silicon substrate
Si
silicon nitride
SiN
FIG. 3 for a gate voltage Vgs greater than a hole injection voltage VHoleInjection of the device;
FIG. 4A is a cross-section view of an HEMT device without any layer of p-InGaN for a gate voltage Vgs below the threshold voltage Vth1 of the device;
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 8A is a graph representing conduction band energy Ec in line with the gate of the devices of
FIG. 9 is a graph representing 2DEG density in a channel of the devices of
FIG. 10A is a graph representing gate current Ig as a 25 function of gate-source voltage Vgs for the devices of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 15A is a graph representing gate current Ig as a function of the gate-source voltage Vgs of the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
| — |
Voltage | 0–1 V | — |
Voltage | 4–5 V | — |
Thickness | 0.1–0.3 µm | — |
Thickness | 1–4 µm | — |
Thickness | ≥ 5 nm | — |
Thickness | ≥ 6 µm | — |
Thickness | ≥ 4 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 2 µm | — |
HEMT device 300 (embodiment with p-InGaN, Ni gate)
gallium nitride channel layer
GaN
p-doped gallium nitride gate layer
p-GaN
p-doped indium gallium nitride
p-InGaN
gate metal (Ni, W, or TiN)
nickel gate metal
Ni
silicon substrate
Si
silicon nitride
SiN
FIG. 3 for a gate voltage Vgs greater than a hole injection voltage VHoleInjection of the device;
FIG. 4A is a cross-section view of an HEMT device without any layer of p-InGaN for a gate voltage Vgs below the threshold voltage Vth1 of the device;
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 8A is a graph representing conduction band energy Ec in line with the gate of the devices of
FIG. 9 is a graph representing 2DEG density in a channel of the devices of
FIG. 10A is a graph representing gate current Ig as a 25 function of gate-source voltage Vgs for the devices of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 15A is a graph representing gate current Ig as a function of the gate-source voltage Vgs of the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
| — |
Voltage | 0–1 V | — |
Voltage | 4–5 V | — |
Thickness | 0.1–0.3 µm | — |
Thickness | 1–4 µm | — |
Thickness | ≥ 5 nm | — |
Thickness | ≥ 6 µm | — |
Thickness | ≥ 4 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 2 µm | — |
HEMT device 300 (embodiment with p-InGaN, Ni gate)
gallium nitride channel layer
GaN
p-doped gallium nitride gate layer
p-GaN
p-doped indium gallium nitride
p-InGaN
gate metal (Ni, W, or TiN)
nickel gate metal
Ni
silicon substrate
Si
silicon nitride
SiN
FIG. 3 for a gate voltage Vgs greater than a hole injection voltage VHoleInjection of the device;
FIG. 4A is a cross-section view of an HEMT device without any layer of p-InGaN for a gate voltage Vgs below the threshold voltage Vth1 of the device;
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 7A is a graph representing a drain-source current Ids of the devices of
FIG. 8A is a graph representing conduction band energy Ec in line with the gate of the devices of
FIG. 9 is a graph representing 2DEG density in a channel of the devices of
FIG. 10A is a graph representing gate current Ig as a 25 function of gate-source voltage Vgs for the devices of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 11 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 12A is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 35
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 13 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 14 is a graph representing drain-source current Ids as a function of the gate-source voltage Vgs of the device of 50
FIG. 15A is a graph representing gate current Ig as a function of the gate-source voltage Vgs of the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
FIG. 16D is a graph representing an electric field EF in the channel as a function of distance from the source for the device of
| — |
Voltage | 0–1 V | — |
Voltage | 4–5 V | — |
Thickness | 0.1–0.3 µm | — |
Thickness | 1–4 µm | — |
Thickness | ≥ 5 nm | — |
Thickness | ≥ 6 µm | — |
Thickness | ≥ 4 µm | — |
Thickness | ≥ 10 µm | — |
Thickness | ≥ 0.1 µm | — |
Thickness | ≥ 2 µm | — |