Patent
Atlas literature
Patent
US 11,961,837 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C is a top view of an integrated circuit more specifically showing a top view a diamond-based FET and an exemplary type of GaN-based FET, according to …
FIG. 2 is a flow chart showing an example process for monolithically integrating, during their fabrication, the FETs of
FIG. 3 is diagram illustrating formation of a structure, for example, by seeding and growing PCD particles on an example GaN-based layer while under pressure, …
FIG. 4 is cross section diagram illustrating example diamond-on-GaN architectures, according to certain exem- plary aspects of the present disclosure;
FIG. 5B is a cross-sectional view illustrating an example polycrystalline diamond grown on top of GaN, according to certain exemplary aspects of the present …
FIG. 6 is a Raman spectra graph and top view micro- graphs illustrating an example diamond-on-GaN growth method implemented at various pressures, according to …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: forming a diamond layer section; 35 a GaN-based substrate including GaN and AlGaN and including a dielectric layer; and forming an integrated circuit that includes a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, 40 a diamond-based FET (“diamond FET”) integrated with a portion of the diamond layer section, the diamond FET being electrically coupled to the GaN-based FET and situated over or against a surface region of the GaN-based substrate, and interconnects to electrically interconnect the GaN-based FET and the diamond-based FET, wherein the dielectric layer is formed on the diamond layer section and the dielectric layer is to facilitate stability during operation of the integrated circuit at tempera-tures greater than 250° C. by at least one of: having a selected thickness to mitigate dielectric layer leak-age current or breakdown of the dielectric layer; and being formed using a sufficiently-high deposition temperature of greater than 350° C.
The method of claim 1, wherein the AlGaN is charac-terized as AlxGayN (0<x<1; x+y=1), the GaN-based FET is an n-channel FET and the diamond FET is a p-channel diamond FET, and the diamond layer section is combined with the GaN-based substrate by bonding or by growing a PCD (polycrystalline diamond) over or against the surface region of the GaN-based substrate.
The method of claim 1, wherein the method further includes providing pressure-based control to form the dia-mond layer section with a targeted grain size of diamond particles which are grown through use of chemical vapor deposition (CVD).
The method of claim 1, wherein said forming an integrated circuit includes using a thermocompression-bonding method to bond respective portions of the diamond layer section and the GaN-based substrate, wherein the diamond layer section is formed without use of chemical vapor deposition (CVD).
The method of claim 1, wherein forming the dielectric layer includes using atomic-layer deposition (ALD) at a temperature in a range from 450° C. to 500° C., or using plasma-enhanced chemical vapor deposition (PECVD) at a temperature in a range not exceeding 500° C., and causing the dielectric layer to have a thickness, between the GaN-based substrate and the diamond layer section, in a range from 30 nm to 50 nm.
The method of claim 1, further including forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET, and wherein the GaN-based FET and the diamond FET are interconnected and configured to form a complementary FET.
The method of claim 1, wherein the method further includes a cooling process during growth of PCD (polycrys-talline diamond) particles to form a PCD, and further includes controlling growth parameters of the PCD particles, wherein the controlled growth parameters include controlled pressure and controlled temperature to realize a targeted grain size of the PCD particles.
The method of claim 1, wherein controlled growth pressure and plasma power are applied to set a targeted grain size of PCD (polycrystalline diamond) particles in the diamond layer section, the targeted grain size corresponding to or associated with sp2 and hydrogen content in the diamond layer section, and further including using the controlled growth pressure and plasma power for growing the PCD particles.
The method of claim 1, wherein the GaN-based FET is part of a circuit that includes a plurality of GaN-type FETs, and the method further includes using the diamond layer section to spread heat while the GaN-based FET and the diamond FET are being operated.
The method of claim 1, wherein the diamond-based FET and the GaN-based FET are interconnected by a monolithic integration process including: deposition and growth of PC diamond on the GaN-based substrate; fabri-cating the GaN-based FET on a portion of the GaN-based substrate not covered by the diamond layer section; and forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET.
The method of claim 1, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is formed, the method further including using interconnecting contact pads of the diamond FET with contact pads of the GaN-based FET through use of a thermocompression process.
The method of claim 1, further including hydrogen-terminating the diamond FET and then forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET, and wherein the dielectric layer has a thickness in a range from 30 nm to 60 nm.
The method of claim 1, wherein the diamond layer section is polycrystalline in nature, and is grown from PCD (polycrystalline diamond) particles that are characterized as having a targeted grain size provided by controlling growth of the PCD particles, wherein the targeted grain size is within a range from 650 nanometers to 2.5 microns.
The method of claim 1, wherein the dielectric layer is formed using atomic-layer deposition with the sufficiently-high deposition temperature being in a range from 450° C. to 500° C.
An apparatus comprising: a GaN-based substrate including GaN and AlGaN and including a dielectric layer; a diamond layer section that is single- or poly-crystalline in nature; and an integrated circuit that includes a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, and a diamond FET integrated with a portion of the dia-mond layer section, the diamond FET being electri-cally coupled to the GaN-based FET by intercon-nects and situated over or against a surface region of the GaN-based substrate, the dielectric layer being formed on the diamond layer section and the dielec-tric layer to facilitate stability during operation of the integrated circuit at temperatures greater than 250° C. by at least one of: having a selected thickness to mitigate dielectric layer leakage current or break-down of the dielectric layer; and being formed using a sufficiently-high deposition temperature of greater than 350° C.
The apparatus of claim 16, wherein the GaN-based FET is part of a circuit that includes a plurality of GaN-type FETs, and wherein the diamond layer section is to spread heat while the GaN-based FET and the diamond FET are being operated, and wherein the dielectric layer has a thickness in a range from 30 nm to 60 nm.
The apparatus of claim 16, wherein the diamond FET and the GaN-based FET are monolithically integrated and B₂ have respective sets of contact pads interconnected, and wherein the diamond layer section is polycrystalline in nature.
The apparatus of claim 16, wherein the diamond FET is a p-channel diamond FET and the GaN-based FET is an n-channel GaN-based HEMT (high-electron-mobility tran-sistor).
The apparatus of claim 16, wherein the GaN-based FET and the diamond FET are cooperatively configured to provide a complementary FET (C-FET) in which the GaN-based FET is an n-channel HEMT (high-electron-mobility transistor) and the diamond FET is a p-channel FET.
The apparatus of claim 16, wherein the integrated circuit includes at least one diamond FET and at least one of a MESFET (metal—semiconductor field-effect transistor) and a HEMT (high-electron-mobility transistor).
The apparatus of claim 16, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is situated, and the first portion and the second portion are of a commonly-formed wafer die.
The apparatus of claim 16, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is situated, and the first portion and the second portion correspond to separately-formed wafer dice.
The apparatus of claim 16, wherein a portion of the diamond layer section is etched.
The apparatus of claim 16, wherein the dielectric layer is characterized as having electrons transferred from a diamond conduction band. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based FET/HEMT
diamond FET (p-channel)
complementary FET (C-FET) integrated circuit
Materials described outside the worked examples.
diamond layer section
C
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1C is a top view of an integrated circuit more specifically showing a top view a diamond-based FET and an exemplary type of GaN-based FET, according to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 500–950 nm | — |
Temperature |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 15
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,961,837 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C is a top view of an integrated circuit more specifically showing a top view a diamond-based FET and an exemplary type of GaN-based FET, according to …
FIG. 2 is a flow chart showing an example process for monolithically integrating, during their fabrication, the FETs of
FIG. 3 is diagram illustrating formation of a structure, for example, by seeding and growing PCD particles on an example GaN-based layer while under pressure, …
FIG. 4 is cross section diagram illustrating example diamond-on-GaN architectures, according to certain exem- plary aspects of the present disclosure;
FIG. 5B is a cross-sectional view illustrating an example polycrystalline diamond grown on top of GaN, according to certain exemplary aspects of the present …
FIG. 6 is a Raman spectra graph and top view micro- graphs illustrating an example diamond-on-GaN growth method implemented at various pressures, according to …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: forming a diamond layer section; 35 a GaN-based substrate including GaN and AlGaN and including a dielectric layer; and forming an integrated circuit that includes a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, 40 a diamond-based FET (“diamond FET”) integrated with a portion of the diamond layer section, the diamond FET being electrically coupled to the GaN-based FET and situated over or against a surface region of the GaN-based substrate, and interconnects to electrically interconnect the GaN-based FET and the diamond-based FET, wherein the dielectric layer is formed on the diamond layer section and the dielectric layer is to facilitate stability during operation of the integrated circuit at tempera-tures greater than 250° C. by at least one of: having a selected thickness to mitigate dielectric layer leak-age current or breakdown of the dielectric layer; and being formed using a sufficiently-high deposition temperature of greater than 350° C.
The method of claim 1, wherein the AlGaN is charac-terized as AlxGayN (0<x<1; x+y=1), the GaN-based FET is an n-channel FET and the diamond FET is a p-channel diamond FET, and the diamond layer section is combined with the GaN-based substrate by bonding or by growing a PCD (polycrystalline diamond) over or against the surface region of the GaN-based substrate.
The method of claim 1, wherein the method further includes providing pressure-based control to form the dia-mond layer section with a targeted grain size of diamond particles which are grown through use of chemical vapor deposition (CVD).
The method of claim 1, wherein said forming an integrated circuit includes using a thermocompression-bonding method to bond respective portions of the diamond layer section and the GaN-based substrate, wherein the diamond layer section is formed without use of chemical vapor deposition (CVD).
The method of claim 1, wherein forming the dielectric layer includes using atomic-layer deposition (ALD) at a temperature in a range from 450° C. to 500° C., or using plasma-enhanced chemical vapor deposition (PECVD) at a temperature in a range not exceeding 500° C., and causing the dielectric layer to have a thickness, between the GaN-based substrate and the diamond layer section, in a range from 30 nm to 50 nm.
The method of claim 1, further including forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET, and wherein the GaN-based FET and the diamond FET are interconnected and configured to form a complementary FET.
The method of claim 1, wherein the method further includes a cooling process during growth of PCD (polycrys-talline diamond) particles to form a PCD, and further includes controlling growth parameters of the PCD particles, wherein the controlled growth parameters include controlled pressure and controlled temperature to realize a targeted grain size of the PCD particles.
The method of claim 1, wherein controlled growth pressure and plasma power are applied to set a targeted grain size of PCD (polycrystalline diamond) particles in the diamond layer section, the targeted grain size corresponding to or associated with sp2 and hydrogen content in the diamond layer section, and further including using the controlled growth pressure and plasma power for growing the PCD particles.
The method of claim 1, wherein the GaN-based FET is part of a circuit that includes a plurality of GaN-type FETs, and the method further includes using the diamond layer section to spread heat while the GaN-based FET and the diamond FET are being operated.
The method of claim 1, wherein the diamond-based FET and the GaN-based FET are interconnected by a monolithic integration process including: deposition and growth of PC diamond on the GaN-based substrate; fabri-cating the GaN-based FET on a portion of the GaN-based substrate not covered by the diamond layer section; and forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET.
The method of claim 1, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is formed, the method further including using interconnecting contact pads of the diamond FET with contact pads of the GaN-based FET through use of a thermocompression process.
The method of claim 1, further including hydrogen-terminating the diamond FET and then forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET, and wherein the dielectric layer has a thickness in a range from 30 nm to 60 nm.
The method of claim 1, wherein the diamond layer section is polycrystalline in nature, and is grown from PCD (polycrystalline diamond) particles that are characterized as having a targeted grain size provided by controlling growth of the PCD particles, wherein the targeted grain size is within a range from 650 nanometers to 2.5 microns.
The method of claim 1, wherein the dielectric layer is formed using atomic-layer deposition with the sufficiently-high deposition temperature being in a range from 450° C. to 500° C.
An apparatus comprising: a GaN-based substrate including GaN and AlGaN and including a dielectric layer; a diamond layer section that is single- or poly-crystalline in nature; and an integrated circuit that includes a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, and a diamond FET integrated with a portion of the dia-mond layer section, the diamond FET being electri-cally coupled to the GaN-based FET by intercon-nects and situated over or against a surface region of the GaN-based substrate, the dielectric layer being formed on the diamond layer section and the dielec-tric layer to facilitate stability during operation of the integrated circuit at temperatures greater than 250° C. by at least one of: having a selected thickness to mitigate dielectric layer leakage current or break-down of the dielectric layer; and being formed using a sufficiently-high deposition temperature of greater than 350° C.
The apparatus of claim 16, wherein the GaN-based FET is part of a circuit that includes a plurality of GaN-type FETs, and wherein the diamond layer section is to spread heat while the GaN-based FET and the diamond FET are being operated, and wherein the dielectric layer has a thickness in a range from 30 nm to 60 nm.
The apparatus of claim 16, wherein the diamond FET and the GaN-based FET are monolithically integrated and B₂ have respective sets of contact pads interconnected, and wherein the diamond layer section is polycrystalline in nature.
The apparatus of claim 16, wherein the diamond FET is a p-channel diamond FET and the GaN-based FET is an n-channel GaN-based HEMT (high-electron-mobility tran-sistor).
The apparatus of claim 16, wherein the GaN-based FET and the diamond FET are cooperatively configured to provide a complementary FET (C-FET) in which the GaN-based FET is an n-channel HEMT (high-electron-mobility transistor) and the diamond FET is a p-channel FET.
The apparatus of claim 16, wherein the integrated circuit includes at least one diamond FET and at least one of a MESFET (metal—semiconductor field-effect transistor) and a HEMT (high-electron-mobility transistor).
The apparatus of claim 16, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is situated, and the first portion and the second portion are of a commonly-formed wafer die.
The apparatus of claim 16, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is situated, and the first portion and the second portion correspond to separately-formed wafer dice.
The apparatus of claim 16, wherein a portion of the diamond layer section is etched.
The apparatus of claim 16, wherein the dielectric layer is characterized as having electrons transferred from a diamond conduction band. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based FET/HEMT
diamond FET (p-channel)
complementary FET (C-FET) integrated circuit
Materials described outside the worked examples.
diamond layer section
C
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1C is a top view of an integrated circuit more specifically showing a top view a diamond-based FET and an exemplary type of GaN-based FET, according to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 500–950 nm | — |
Temperature |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 15
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,961,837 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C is a top view of an integrated circuit more specifically showing a top view a diamond-based FET and an exemplary type of GaN-based FET, according to …
FIG. 2 is a flow chart showing an example process for monolithically integrating, during their fabrication, the FETs of
FIG. 3 is diagram illustrating formation of a structure, for example, by seeding and growing PCD particles on an example GaN-based layer while under pressure, …
FIG. 4 is cross section diagram illustrating example diamond-on-GaN architectures, according to certain exem- plary aspects of the present disclosure;
FIG. 5B is a cross-sectional view illustrating an example polycrystalline diamond grown on top of GaN, according to certain exemplary aspects of the present …
FIG. 6 is a Raman spectra graph and top view micro- graphs illustrating an example diamond-on-GaN growth method implemented at various pressures, according to …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: forming a diamond layer section; 35 a GaN-based substrate including GaN and AlGaN and including a dielectric layer; and forming an integrated circuit that includes a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, 40 a diamond-based FET (“diamond FET”) integrated with a portion of the diamond layer section, the diamond FET being electrically coupled to the GaN-based FET and situated over or against a surface region of the GaN-based substrate, and interconnects to electrically interconnect the GaN-based FET and the diamond-based FET, wherein the dielectric layer is formed on the diamond layer section and the dielectric layer is to facilitate stability during operation of the integrated circuit at tempera-tures greater than 250° C. by at least one of: having a selected thickness to mitigate dielectric layer leak-age current or breakdown of the dielectric layer; and being formed using a sufficiently-high deposition temperature of greater than 350° C.
The method of claim 1, wherein the AlGaN is charac-terized as AlxGayN (0<x<1; x+y=1), the GaN-based FET is an n-channel FET and the diamond FET is a p-channel diamond FET, and the diamond layer section is combined with the GaN-based substrate by bonding or by growing a PCD (polycrystalline diamond) over or against the surface region of the GaN-based substrate.
The method of claim 1, wherein the method further includes providing pressure-based control to form the dia-mond layer section with a targeted grain size of diamond particles which are grown through use of chemical vapor deposition (CVD).
The method of claim 1, wherein said forming an integrated circuit includes using a thermocompression-bonding method to bond respective portions of the diamond layer section and the GaN-based substrate, wherein the diamond layer section is formed without use of chemical vapor deposition (CVD).
The method of claim 1, wherein forming the dielectric layer includes using atomic-layer deposition (ALD) at a temperature in a range from 450° C. to 500° C., or using plasma-enhanced chemical vapor deposition (PECVD) at a temperature in a range not exceeding 500° C., and causing the dielectric layer to have a thickness, between the GaN-based substrate and the diamond layer section, in a range from 30 nm to 50 nm.
The method of claim 1, further including forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET, and wherein the GaN-based FET and the diamond FET are interconnected and configured to form a complementary FET.
The method of claim 1, wherein the method further includes a cooling process during growth of PCD (polycrys-talline diamond) particles to form a PCD, and further includes controlling growth parameters of the PCD particles, wherein the controlled growth parameters include controlled pressure and controlled temperature to realize a targeted grain size of the PCD particles.
The method of claim 1, wherein controlled growth pressure and plasma power are applied to set a targeted grain size of PCD (polycrystalline diamond) particles in the diamond layer section, the targeted grain size corresponding to or associated with sp2 and hydrogen content in the diamond layer section, and further including using the controlled growth pressure and plasma power for growing the PCD particles.
The method of claim 1, wherein the GaN-based FET is part of a circuit that includes a plurality of GaN-type FETs, and the method further includes using the diamond layer section to spread heat while the GaN-based FET and the diamond FET are being operated.
The method of claim 1, wherein the diamond-based FET and the GaN-based FET are interconnected by a monolithic integration process including: deposition and growth of PC diamond on the GaN-based substrate; fabri-cating the GaN-based FET on a portion of the GaN-based substrate not covered by the diamond layer section; and forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET.
The method of claim 1, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is formed, the method further including using interconnecting contact pads of the diamond FET with contact pads of the GaN-based FET through use of a thermocompression process.
The method of claim 1, further including hydrogen-terminating the diamond FET and then forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET, and wherein the dielectric layer has a thickness in a range from 30 nm to 60 nm.
The method of claim 1, wherein the diamond layer section is polycrystalline in nature, and is grown from PCD (polycrystalline diamond) particles that are characterized as having a targeted grain size provided by controlling growth of the PCD particles, wherein the targeted grain size is within a range from 650 nanometers to 2.5 microns.
The method of claim 1, wherein the dielectric layer is formed using atomic-layer deposition with the sufficiently-high deposition temperature being in a range from 450° C. to 500° C.
An apparatus comprising: a GaN-based substrate including GaN and AlGaN and including a dielectric layer; a diamond layer section that is single- or poly-crystalline in nature; and an integrated circuit that includes a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, and a diamond FET integrated with a portion of the dia-mond layer section, the diamond FET being electri-cally coupled to the GaN-based FET by intercon-nects and situated over or against a surface region of the GaN-based substrate, the dielectric layer being formed on the diamond layer section and the dielec-tric layer to facilitate stability during operation of the integrated circuit at temperatures greater than 250° C. by at least one of: having a selected thickness to mitigate dielectric layer leakage current or break-down of the dielectric layer; and being formed using a sufficiently-high deposition temperature of greater than 350° C.
The apparatus of claim 16, wherein the GaN-based FET is part of a circuit that includes a plurality of GaN-type FETs, and wherein the diamond layer section is to spread heat while the GaN-based FET and the diamond FET are being operated, and wherein the dielectric layer has a thickness in a range from 30 nm to 60 nm.
The apparatus of claim 16, wherein the diamond FET and the GaN-based FET are monolithically integrated and B₂ have respective sets of contact pads interconnected, and wherein the diamond layer section is polycrystalline in nature.
The apparatus of claim 16, wherein the diamond FET is a p-channel diamond FET and the GaN-based FET is an n-channel GaN-based HEMT (high-electron-mobility tran-sistor).
The apparatus of claim 16, wherein the GaN-based FET and the diamond FET are cooperatively configured to provide a complementary FET (C-FET) in which the GaN-based FET is an n-channel HEMT (high-electron-mobility transistor) and the diamond FET is a p-channel FET.
The apparatus of claim 16, wherein the integrated circuit includes at least one diamond FET and at least one of a MESFET (metal—semiconductor field-effect transistor) and a HEMT (high-electron-mobility transistor).
The apparatus of claim 16, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is situated, and the first portion and the second portion are of a commonly-formed wafer die.
The apparatus of claim 16, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is situated, and the first portion and the second portion correspond to separately-formed wafer dice.
The apparatus of claim 16, wherein a portion of the diamond layer section is etched.
The apparatus of claim 16, wherein the dielectric layer is characterized as having electrons transferred from a diamond conduction band. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based FET/HEMT
diamond FET (p-channel)
complementary FET (C-FET) integrated circuit
Materials described outside the worked examples.
diamond layer section
C
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1C is a top view of an integrated circuit more specifically showing a top view a diamond-based FET and an exemplary type of GaN-based FET, according to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 500–950 nm | — |
Temperature |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 15
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,961,837 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C is a top view of an integrated circuit more specifically showing a top view a diamond-based FET and an exemplary type of GaN-based FET, according to …
FIG. 2 is a flow chart showing an example process for monolithically integrating, during their fabrication, the FETs of
FIG. 3 is diagram illustrating formation of a structure, for example, by seeding and growing PCD particles on an example GaN-based layer while under pressure, …
FIG. 4 is cross section diagram illustrating example diamond-on-GaN architectures, according to certain exem- plary aspects of the present disclosure;
FIG. 5B is a cross-sectional view illustrating an example polycrystalline diamond grown on top of GaN, according to certain exemplary aspects of the present …
FIG. 6 is a Raman spectra graph and top view micro- graphs illustrating an example diamond-on-GaN growth method implemented at various pressures, according to …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: forming a diamond layer section; 35 a GaN-based substrate including GaN and AlGaN and including a dielectric layer; and forming an integrated circuit that includes a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, 40 a diamond-based FET (“diamond FET”) integrated with a portion of the diamond layer section, the diamond FET being electrically coupled to the GaN-based FET and situated over or against a surface region of the GaN-based substrate, and interconnects to electrically interconnect the GaN-based FET and the diamond-based FET, wherein the dielectric layer is formed on the diamond layer section and the dielectric layer is to facilitate stability during operation of the integrated circuit at tempera-tures greater than 250° C. by at least one of: having a selected thickness to mitigate dielectric layer leak-age current or breakdown of the dielectric layer; and being formed using a sufficiently-high deposition temperature of greater than 350° C.
The method of claim 1, wherein the AlGaN is charac-terized as AlxGayN (0<x<1; x+y=1), the GaN-based FET is an n-channel FET and the diamond FET is a p-channel diamond FET, and the diamond layer section is combined with the GaN-based substrate by bonding or by growing a PCD (polycrystalline diamond) over or against the surface region of the GaN-based substrate.
The method of claim 1, wherein the method further includes providing pressure-based control to form the dia-mond layer section with a targeted grain size of diamond particles which are grown through use of chemical vapor deposition (CVD).
The method of claim 1, wherein said forming an integrated circuit includes using a thermocompression-bonding method to bond respective portions of the diamond layer section and the GaN-based substrate, wherein the diamond layer section is formed without use of chemical vapor deposition (CVD).
The method of claim 1, wherein forming the dielectric layer includes using atomic-layer deposition (ALD) at a temperature in a range from 450° C. to 500° C., or using plasma-enhanced chemical vapor deposition (PECVD) at a temperature in a range not exceeding 500° C., and causing the dielectric layer to have a thickness, between the GaN-based substrate and the diamond layer section, in a range from 30 nm to 50 nm.
The method of claim 1, further including forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET, and wherein the GaN-based FET and the diamond FET are interconnected and configured to form a complementary FET.
The method of claim 1, wherein the method further includes a cooling process during growth of PCD (polycrys-talline diamond) particles to form a PCD, and further includes controlling growth parameters of the PCD particles, wherein the controlled growth parameters include controlled pressure and controlled temperature to realize a targeted grain size of the PCD particles.
The method of claim 1, wherein controlled growth pressure and plasma power are applied to set a targeted grain size of PCD (polycrystalline diamond) particles in the diamond layer section, the targeted grain size corresponding to or associated with sp2 and hydrogen content in the diamond layer section, and further including using the controlled growth pressure and plasma power for growing the PCD particles.
The method of claim 1, wherein the GaN-based FET is part of a circuit that includes a plurality of GaN-type FETs, and the method further includes using the diamond layer section to spread heat while the GaN-based FET and the diamond FET are being operated.
The method of claim 1, wherein the diamond-based FET and the GaN-based FET are interconnected by a monolithic integration process including: deposition and growth of PC diamond on the GaN-based substrate; fabri-cating the GaN-based FET on a portion of the GaN-based substrate not covered by the diamond layer section; and forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET.
The method of claim 1, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is formed, the method further including using interconnecting contact pads of the diamond FET with contact pads of the GaN-based FET through use of a thermocompression process.
The method of claim 1, further including hydrogen-terminating the diamond FET and then forming and interconnecting respective sets of contact pads for each of the GaN-based FET and the diamond FET, and wherein the dielectric layer has a thickness in a range from 30 nm to 60 nm.
The method of claim 1, wherein the diamond layer section is polycrystalline in nature, and is grown from PCD (polycrystalline diamond) particles that are characterized as having a targeted grain size provided by controlling growth of the PCD particles, wherein the targeted grain size is within a range from 650 nanometers to 2.5 microns.
The method of claim 1, wherein the dielectric layer is formed using atomic-layer deposition with the sufficiently-high deposition temperature being in a range from 450° C. to 500° C.
An apparatus comprising: a GaN-based substrate including GaN and AlGaN and including a dielectric layer; a diamond layer section that is single- or poly-crystalline in nature; and an integrated circuit that includes a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, and a diamond FET integrated with a portion of the dia-mond layer section, the diamond FET being electri-cally coupled to the GaN-based FET by intercon-nects and situated over or against a surface region of the GaN-based substrate, the dielectric layer being formed on the diamond layer section and the dielec-tric layer to facilitate stability during operation of the integrated circuit at temperatures greater than 250° C. by at least one of: having a selected thickness to mitigate dielectric layer leakage current or break-down of the dielectric layer; and being formed using a sufficiently-high deposition temperature of greater than 350° C.
The apparatus of claim 16, wherein the GaN-based FET is part of a circuit that includes a plurality of GaN-type FETs, and wherein the diamond layer section is to spread heat while the GaN-based FET and the diamond FET are being operated, and wherein the dielectric layer has a thickness in a range from 30 nm to 60 nm.
The apparatus of claim 16, wherein the diamond FET and the GaN-based FET are monolithically integrated and B₂ have respective sets of contact pads interconnected, and wherein the diamond layer section is polycrystalline in nature.
The apparatus of claim 16, wherein the diamond FET is a p-channel diamond FET and the GaN-based FET is an n-channel GaN-based HEMT (high-electron-mobility tran-sistor).
The apparatus of claim 16, wherein the GaN-based FET and the diamond FET are cooperatively configured to provide a complementary FET (C-FET) in which the GaN-based FET is an n-channel HEMT (high-electron-mobility transistor) and the diamond FET is a p-channel FET.
The apparatus of claim 16, wherein the integrated circuit includes at least one diamond FET and at least one of a MESFET (metal—semiconductor field-effect transistor) and a HEMT (high-electron-mobility transistor).
The apparatus of claim 16, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is situated, and the first portion and the second portion are of a commonly-formed wafer die.
The apparatus of claim 16, wherein the GaN-based substrate has a first portion corresponding to the GaN-based substrate portion in which the GaN-based FET is contained or integrated and has a second portion corresponding to the surface region of the GaN-based substrate over or against which the diamond layer section is situated, and the first portion and the second portion correspond to separately-formed wafer dice.
The apparatus of claim 16, wherein a portion of the diamond layer section is etched.
The apparatus of claim 16, wherein the dielectric layer is characterized as having electrons transferred from a diamond conduction band. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based FET/HEMT
diamond FET (p-channel)
complementary FET (C-FET) integrated circuit
Materials described outside the worked examples.
diamond layer section
C
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1C is a top view of an integrated circuit more specifically showing a top view a diamond-based FET and an exemplary type of GaN-based FET, according to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 500–950 nm | — |
Temperature |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 15
Related documents with shared materials, methods, properties, or citations.
AlGaN
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FIG. 6 is a Raman spectra graph and top view micro- graphs illustrating an example diamond-on-GaN growth method implemented at various pressures, according to …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
| 25–250 °C |
| — |
Duration | 2–3 hours | — |
Temperature | 25–300 °C | — |
Voltage | 3–7 V | — |
Pressure | 40–60 torr | — |
Thickness | 130–180 nm | — |
Thickness | 180–350 nm | — |
Pressure | 30–70 torr | — |
Temperature | 700–750 °C | — |
Thickness | 1–3 µm | — |
Temperature | 125–200 °C | — |
Duration | 0.75–1.5 hours | — |
Thickness | ≤ 4 µm | — |
Thickness | ≤ 800 nm | — |
Thickness | ≤ 500 µm | — |
Thickness | ≤ 200 µm | — |
Thickness | ≤ 200 nm | — |
Thickness | ≥ 1 µm | — |
— | ≥ 20 W | — |
Temperature | ≥ 150 °C | — |
Temperature | 450–500 °C | — |
Thickness | 30–50 nm | — |
Thickness | 30–60 nm | — |
Thickness | 650–2500 nm | — |
Temperature | ≥ 250 °C | — |
Temperature | ≥ 350 °C | — |
Temperature | ≥ 500 °C | — |
Cited non-patent literature · 4
AlGaN
AlxGa(1-x)N
dielectric layer
FIG. 2 is a flow chart showing an example process for monolithically integrating, during their fabrication, the FETs of
FIG. 6 is a Raman spectra graph and top view micro- graphs illustrating an example diamond-on-GaN growth method implemented at various pressures, according to …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
| 25–250 °C |
| — |
Duration | 2–3 hours | — |
Temperature | 25–300 °C | — |
Voltage | 3–7 V | — |
Pressure | 40–60 torr | — |
Thickness | 130–180 nm | — |
Thickness | 180–350 nm | — |
Pressure | 30–70 torr | — |
Temperature | 700–750 °C | — |
Thickness | 1–3 µm | — |
Temperature | 125–200 °C | — |
Duration | 0.75–1.5 hours | — |
Thickness | ≤ 4 µm | — |
Thickness | ≤ 800 nm | — |
Thickness | ≤ 500 µm | — |
Thickness | ≤ 200 µm | — |
Thickness | ≤ 200 nm | — |
Thickness | ≥ 1 µm | — |
— | ≥ 20 W | — |
Temperature | ≥ 150 °C | — |
Temperature | 450–500 °C | — |
Thickness | 30–50 nm | — |
Thickness | 30–60 nm | — |
Thickness | 650–2500 nm | — |
Temperature | ≥ 250 °C | — |
Temperature | ≥ 350 °C | — |
Temperature | ≥ 500 °C | — |
Cited non-patent literature · 4
AlGaN
AlxGa(1-x)N
dielectric layer
FIG. 2 is a flow chart showing an example process for monolithically integrating, during their fabrication, the FETs of
FIG. 6 is a Raman spectra graph and top view micro- graphs illustrating an example diamond-on-GaN growth method implemented at various pressures, according to …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
| 25–250 °C |
| — |
Duration | 2–3 hours | — |
Temperature | 25–300 °C | — |
Voltage | 3–7 V | — |
Pressure | 40–60 torr | — |
Thickness | 130–180 nm | — |
Thickness | 180–350 nm | — |
Pressure | 30–70 torr | — |
Temperature | 700–750 °C | — |
Thickness | 1–3 µm | — |
Temperature | 125–200 °C | — |
Duration | 0.75–1.5 hours | — |
Thickness | ≤ 4 µm | — |
Thickness | ≤ 800 nm | — |
Thickness | ≤ 500 µm | — |
Thickness | ≤ 200 µm | — |
Thickness | ≤ 200 nm | — |
Thickness | ≥ 1 µm | — |
— | ≥ 20 W | — |
Temperature | ≥ 150 °C | — |
Temperature | 450–500 °C | — |
Thickness | 30–50 nm | — |
Thickness | 30–60 nm | — |
Thickness | 650–2500 nm | — |
Temperature | ≥ 250 °C | — |
Temperature | ≥ 350 °C | — |
Temperature | ≥ 500 °C | — |
Cited non-patent literature · 4
AlGaN
AlxGa(1-x)N
dielectric layer
FIG. 2 is a flow chart showing an example process for monolithically integrating, during their fabrication, the FETs of
FIG. 6 is a Raman spectra graph and top view micro- graphs illustrating an example diamond-on-GaN growth method implemented at various pressures, according to …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 7B is a graph illustrating the voltage transfer char- acteristics of an example complementary transistor based inverter according to certain exemplary …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
FIG. 8D is a graph illustrating ID versus VDS character- istics and the breakdown field of an example diamond MESFET according to certain exemplary aspects of …
| 25–250 °C |
| — |
Duration | 2–3 hours | — |
Temperature | 25–300 °C | — |
Voltage | 3–7 V | — |
Pressure | 40–60 torr | — |
Thickness | 130–180 nm | — |
Thickness | 180–350 nm | — |
Pressure | 30–70 torr | — |
Temperature | 700–750 °C | — |
Thickness | 1–3 µm | — |
Temperature | 125–200 °C | — |
Duration | 0.75–1.5 hours | — |
Thickness | ≤ 4 µm | — |
Thickness | ≤ 800 nm | — |
Thickness | ≤ 500 µm | — |
Thickness | ≤ 200 µm | — |
Thickness | ≤ 200 nm | — |
Thickness | ≥ 1 µm | — |
— | ≥ 20 W | — |
Temperature | ≥ 150 °C | — |
Temperature | 450–500 °C | — |
Thickness | 30–50 nm | — |
Thickness | 30–60 nm | — |
Thickness | 650–2500 nm | — |
Temperature | ≥ 250 °C | — |
Temperature | ≥ 350 °C | — |
Temperature | ≥ 500 °C | — |
Cited non-patent literature · 4
