Patent
US 10,573,647CMOS CIRCUITS USING N-CHANNEL AND P-CHANNEL GALLIUM NITRIDE TRANSISTORS
Han Wui Then
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,573,647Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic of a gallium nitride circuit, as known in the art.
FIG. 2 is a schematic of a gallium nitride circuit, according to an embodiment of the present description. FIGs. 3-9 are side cross-section views of the …
FIG. 3. As shown in
FIG. 4, the layered structure 210 formed with a polarization layer 204 deposited on a first gallium nitride layer 202 and a second gallium nitride layer 206 …
FIG. 5) has removed and a third hardmask 244 10 is patterned over the n-channel gallium nitride transistor 230. The p-channel gallium nitride transistor 250 …
FIG. 6, the second gallium nitride layer 206 in the unmasked portion 224 designated for the subsequent formation of an n-channel gallium 25 nitride circuit …
FIG. 7, an n-channel gallium nitride transistor 230 may be formed in the portion 224 af t er a second hardmask 228 is patterned on the portion 220 designated …
FIG. 8) may be removed and at least one interlayer dielectric layer 272 may be deposited over the n-channel gallium nitride transistor 230 and the p-channel …
FIG. 9, conductive traces 286 may be formed to appropriately connect components of the n-channel gallium nitride transistor 230 and the p-channel gallium …
FIG. 10 is a side cross-section view of a gallium nitride circuit structure, according to another embodiment of the present description. FIGs. 11 and 12 are …
FIG. 11, the p-channel 30 gallium nitride transistor 250 may be stacked on top of the n-channel gallium nitride transistor 230, so that a common gate 302 could …
FIG. 12, which is a cross-sectional view along line 12-12 of
FIG. 13 is a side cross-section view of a gallium nitride circuit structure, according to a further embodiment of the present description.
FIG. 14 is a side cross-section view of a gallium nitride circuit structure, according to another embodiment of the present description. 15
FIG. 15 is a flow chart of a process of fabricating a gallium nitride circuit structure, according to an embodiment of the present description.
FIG. 16 illustrates a computing device in accordance with one implementation of the present description.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A CMOS circuit structure comprising: a layered structure including a first gallium nitride layer and a second gallium nitride layer separated by a polarization layer, wherein the layered structure includes an polarization layer intermediate surface and wherein a thickness between the polarization layer intermediate surface and an interface between the first gallium nitride layer and the polarization layer is less than about 20 nm; a first transistor formed proximate the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and a second the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The CMOS circuit structure of claim 1, wherein the p-channel transistor is an enhancement mode transistor. Original
The CMOS circuit structure of claim 1, wherein the n-channel transistor is an enhancement mode transistor. Previously presented
The CMOS circuit structure of claim 1, wherein the polarization layer is selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, indium gallium nitride, aluminum nitride, and aluminum indium gallium nitride. Original
The CMOS circuit structure of claim 1, further including a strain material layer, wherein the first gallium nitride layer abuts the strain material layer. Original
The CMOS circuit structure of claim 1, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The CMOS circuit structure of claim 1, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the p-channel transistor is formed proximate the polarization layer intermediate surface and the n-channel transistor is formed proximate the first gallium nitride layer. Original
A method of fabricating a CMOS circuit structure comprising: forming a layered structure comprising depositing a polarization layer on a first gallium nitride layer and depositing a second gallium nitride layer on the polarization layer; removing a portion of one of the first gallium nitride layer and the second gallium nitride layer and a portion of the polarization layer to form a polarization layer intermediate surface and wherein a thickness between the polarization layer intermediate surface and an interface between the first gallium nitride layer and the polarization layer is less than about 20 nm; forming a first transistor on the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and forming a second the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The method of claim 11, wherein forming the p-channel transistor comprises forming a p-channel enhancement mode transistor. Original
The method of claim 11, wherein forming the n-channel transistor comprises forming an n-channel enhancement mode transistor. Previously presented
The method of claim 11, wherein depositing the polarization layer comprises depositing a material selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, indium gallium nitride, aluminum nitride, and aluminum indium gallium nitride. Original
The method of claim 11, further comprising depositing the first gallium nitride layer on a strain material layer. Original
The method of claim 11, wherein forming the layered structure includes forming a 2D electron gas within the first gallium nitride layer proximate the polarization layer and forming a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The method of claim I1, wherein forming the layered structure includes forming a 2D electron gas within the first gallium nitride layer proximate the polarization layer and forming a 2D hole gas within the second gallium nitride laye r; and wherein the p-channel transistor is for m ed proximate the polarization layer intermediate surface and the n-channel transistor is for m ed proximate the first gallium nitride layer. Original
(Or ig inal) The method of claim 19, further including forming a recess in the first gallium nitride layer to disrupt a portion of the 2D electron gas. Original
An electronic system, comprising: a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one CMOS circuit structure comprising: a layered structure including a first gallium nitride layer and a second gallium nitride layer separated by a polarization layer, wherein the layered structure includes an polarization layer intermediate surface and wherein a thickness between the polarization layer inter m ediate su r face and an interface between the fi r st gallium nitride layer and the polarization layer is less than about 20 nm; a first transistor formed proximate the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and a second transistor formed on the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The electronic system of claim 21, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The electronic system of claim 21, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the second gallium nitride layer; and wherein the polarization layer intermediate surface and the gallium nitride layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN CMOS circuit structure
n-channel gallium nitride transistor
Materials described outside the worked examples.
first gallium nitride layer
GaN
aluminum gallium nitride
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5) has removed and a third hardmask 244 10 is patterned over the n-channel gallium nitride transistor 230. The p-channel gallium nitride transistor 250 …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN bandgap | 3.4 eV | GaN |
GaN electron mobility |
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Patent
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US 10,573,647Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic of a gallium nitride circuit, as known in the art.
FIG. 2 is a schematic of a gallium nitride circuit, according to an embodiment of the present description. FIGs. 3-9 are side cross-section views of the …
FIG. 3. As shown in
FIG. 4, the layered structure 210 formed with a polarization layer 204 deposited on a first gallium nitride layer 202 and a second gallium nitride layer 206 …
FIG. 5) has removed and a third hardmask 244 10 is patterned over the n-channel gallium nitride transistor 230. The p-channel gallium nitride transistor 250 …
FIG. 6, the second gallium nitride layer 206 in the unmasked portion 224 designated for the subsequent formation of an n-channel gallium 25 nitride circuit …
FIG. 7, an n-channel gallium nitride transistor 230 may be formed in the portion 224 af t er a second hardmask 228 is patterned on the portion 220 designated …
FIG. 8) may be removed and at least one interlayer dielectric layer 272 may be deposited over the n-channel gallium nitride transistor 230 and the p-channel …
FIG. 9, conductive traces 286 may be formed to appropriately connect components of the n-channel gallium nitride transistor 230 and the p-channel gallium …
FIG. 10 is a side cross-section view of a gallium nitride circuit structure, according to another embodiment of the present description. FIGs. 11 and 12 are …
FIG. 11, the p-channel 30 gallium nitride transistor 250 may be stacked on top of the n-channel gallium nitride transistor 230, so that a common gate 302 could …
FIG. 12, which is a cross-sectional view along line 12-12 of
FIG. 13 is a side cross-section view of a gallium nitride circuit structure, according to a further embodiment of the present description.
FIG. 14 is a side cross-section view of a gallium nitride circuit structure, according to another embodiment of the present description. 15
FIG. 15 is a flow chart of a process of fabricating a gallium nitride circuit structure, according to an embodiment of the present description.
FIG. 16 illustrates a computing device in accordance with one implementation of the present description.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A CMOS circuit structure comprising: a layered structure including a first gallium nitride layer and a second gallium nitride layer separated by a polarization layer, wherein the layered structure includes an polarization layer intermediate surface and wherein a thickness between the polarization layer intermediate surface and an interface between the first gallium nitride layer and the polarization layer is less than about 20 nm; a first transistor formed proximate the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and a second the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The CMOS circuit structure of claim 1, wherein the p-channel transistor is an enhancement mode transistor. Original
The CMOS circuit structure of claim 1, wherein the n-channel transistor is an enhancement mode transistor. Previously presented
The CMOS circuit structure of claim 1, wherein the polarization layer is selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, indium gallium nitride, aluminum nitride, and aluminum indium gallium nitride. Original
The CMOS circuit structure of claim 1, further including a strain material layer, wherein the first gallium nitride layer abuts the strain material layer. Original
The CMOS circuit structure of claim 1, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The CMOS circuit structure of claim 1, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the p-channel transistor is formed proximate the polarization layer intermediate surface and the n-channel transistor is formed proximate the first gallium nitride layer. Original
A method of fabricating a CMOS circuit structure comprising: forming a layered structure comprising depositing a polarization layer on a first gallium nitride layer and depositing a second gallium nitride layer on the polarization layer; removing a portion of one of the first gallium nitride layer and the second gallium nitride layer and a portion of the polarization layer to form a polarization layer intermediate surface and wherein a thickness between the polarization layer intermediate surface and an interface between the first gallium nitride layer and the polarization layer is less than about 20 nm; forming a first transistor on the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and forming a second the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The method of claim 11, wherein forming the p-channel transistor comprises forming a p-channel enhancement mode transistor. Original
The method of claim 11, wherein forming the n-channel transistor comprises forming an n-channel enhancement mode transistor. Previously presented
The method of claim 11, wherein depositing the polarization layer comprises depositing a material selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, indium gallium nitride, aluminum nitride, and aluminum indium gallium nitride. Original
The method of claim 11, further comprising depositing the first gallium nitride layer on a strain material layer. Original
The method of claim 11, wherein forming the layered structure includes forming a 2D electron gas within the first gallium nitride layer proximate the polarization layer and forming a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The method of claim I1, wherein forming the layered structure includes forming a 2D electron gas within the first gallium nitride layer proximate the polarization layer and forming a 2D hole gas within the second gallium nitride laye r; and wherein the p-channel transistor is for m ed proximate the polarization layer intermediate surface and the n-channel transistor is for m ed proximate the first gallium nitride layer. Original
(Or ig inal) The method of claim 19, further including forming a recess in the first gallium nitride layer to disrupt a portion of the 2D electron gas. Original
An electronic system, comprising: a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one CMOS circuit structure comprising: a layered structure including a first gallium nitride layer and a second gallium nitride layer separated by a polarization layer, wherein the layered structure includes an polarization layer intermediate surface and wherein a thickness between the polarization layer inter m ediate su r face and an interface between the fi r st gallium nitride layer and the polarization layer is less than about 20 nm; a first transistor formed proximate the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and a second transistor formed on the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The electronic system of claim 21, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The electronic system of claim 21, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the second gallium nitride layer; and wherein the polarization layer intermediate surface and the gallium nitride layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN CMOS circuit structure
n-channel gallium nitride transistor
Materials described outside the worked examples.
first gallium nitride layer
GaN
aluminum gallium nitride
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5) has removed and a third hardmask 244 10 is patterned over the n-channel gallium nitride transistor 230. The p-channel gallium nitride transistor 250 …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN bandgap | 3.4 eV | GaN |
GaN electron mobility |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,573,647Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic of a gallium nitride circuit, as known in the art.
FIG. 2 is a schematic of a gallium nitride circuit, according to an embodiment of the present description. FIGs. 3-9 are side cross-section views of the …
FIG. 3. As shown in
FIG. 4, the layered structure 210 formed with a polarization layer 204 deposited on a first gallium nitride layer 202 and a second gallium nitride layer 206 …
FIG. 5) has removed and a third hardmask 244 10 is patterned over the n-channel gallium nitride transistor 230. The p-channel gallium nitride transistor 250 …
FIG. 6, the second gallium nitride layer 206 in the unmasked portion 224 designated for the subsequent formation of an n-channel gallium 25 nitride circuit …
FIG. 7, an n-channel gallium nitride transistor 230 may be formed in the portion 224 af t er a second hardmask 228 is patterned on the portion 220 designated …
FIG. 8) may be removed and at least one interlayer dielectric layer 272 may be deposited over the n-channel gallium nitride transistor 230 and the p-channel …
FIG. 9, conductive traces 286 may be formed to appropriately connect components of the n-channel gallium nitride transistor 230 and the p-channel gallium …
FIG. 10 is a side cross-section view of a gallium nitride circuit structure, according to another embodiment of the present description. FIGs. 11 and 12 are …
FIG. 11, the p-channel 30 gallium nitride transistor 250 may be stacked on top of the n-channel gallium nitride transistor 230, so that a common gate 302 could …
FIG. 12, which is a cross-sectional view along line 12-12 of
FIG. 13 is a side cross-section view of a gallium nitride circuit structure, according to a further embodiment of the present description.
FIG. 14 is a side cross-section view of a gallium nitride circuit structure, according to another embodiment of the present description. 15
FIG. 15 is a flow chart of a process of fabricating a gallium nitride circuit structure, according to an embodiment of the present description.
FIG. 16 illustrates a computing device in accordance with one implementation of the present description.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A CMOS circuit structure comprising: a layered structure including a first gallium nitride layer and a second gallium nitride layer separated by a polarization layer, wherein the layered structure includes an polarization layer intermediate surface and wherein a thickness between the polarization layer intermediate surface and an interface between the first gallium nitride layer and the polarization layer is less than about 20 nm; a first transistor formed proximate the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and a second the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The CMOS circuit structure of claim 1, wherein the p-channel transistor is an enhancement mode transistor. Original
The CMOS circuit structure of claim 1, wherein the n-channel transistor is an enhancement mode transistor. Previously presented
The CMOS circuit structure of claim 1, wherein the polarization layer is selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, indium gallium nitride, aluminum nitride, and aluminum indium gallium nitride. Original
The CMOS circuit structure of claim 1, further including a strain material layer, wherein the first gallium nitride layer abuts the strain material layer. Original
The CMOS circuit structure of claim 1, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The CMOS circuit structure of claim 1, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the p-channel transistor is formed proximate the polarization layer intermediate surface and the n-channel transistor is formed proximate the first gallium nitride layer. Original
A method of fabricating a CMOS circuit structure comprising: forming a layered structure comprising depositing a polarization layer on a first gallium nitride layer and depositing a second gallium nitride layer on the polarization layer; removing a portion of one of the first gallium nitride layer and the second gallium nitride layer and a portion of the polarization layer to form a polarization layer intermediate surface and wherein a thickness between the polarization layer intermediate surface and an interface between the first gallium nitride layer and the polarization layer is less than about 20 nm; forming a first transistor on the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and forming a second the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The method of claim 11, wherein forming the p-channel transistor comprises forming a p-channel enhancement mode transistor. Original
The method of claim 11, wherein forming the n-channel transistor comprises forming an n-channel enhancement mode transistor. Previously presented
The method of claim 11, wherein depositing the polarization layer comprises depositing a material selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, indium gallium nitride, aluminum nitride, and aluminum indium gallium nitride. Original
The method of claim 11, further comprising depositing the first gallium nitride layer on a strain material layer. Original
The method of claim 11, wherein forming the layered structure includes forming a 2D electron gas within the first gallium nitride layer proximate the polarization layer and forming a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The method of claim I1, wherein forming the layered structure includes forming a 2D electron gas within the first gallium nitride layer proximate the polarization layer and forming a 2D hole gas within the second gallium nitride laye r; and wherein the p-channel transistor is for m ed proximate the polarization layer intermediate surface and the n-channel transistor is for m ed proximate the first gallium nitride layer. Original
(Or ig inal) The method of claim 19, further including forming a recess in the first gallium nitride layer to disrupt a portion of the 2D electron gas. Original
An electronic system, comprising: a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one CMOS circuit structure comprising: a layered structure including a first gallium nitride layer and a second gallium nitride layer separated by a polarization layer, wherein the layered structure includes an polarization layer intermediate surface and wherein a thickness between the polarization layer inter m ediate su r face and an interface between the fi r st gallium nitride layer and the polarization layer is less than about 20 nm; a first transistor formed proximate the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and a second transistor formed on the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The electronic system of claim 21, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The electronic system of claim 21, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the second gallium nitride layer; and wherein the polarization layer intermediate surface and the gallium nitride layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN CMOS circuit structure
n-channel gallium nitride transistor
Materials described outside the worked examples.
first gallium nitride layer
GaN
aluminum gallium nitride
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5) has removed and a third hardmask 244 10 is patterned over the n-channel gallium nitride transistor 230. The p-channel gallium nitride transistor 250 …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN bandgap | 3.4 eV | GaN |
GaN electron mobility |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,573,647Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic of a gallium nitride circuit, as known in the art.
FIG. 2 is a schematic of a gallium nitride circuit, according to an embodiment of the present description. FIGs. 3-9 are side cross-section views of the …
FIG. 3. As shown in
FIG. 4, the layered structure 210 formed with a polarization layer 204 deposited on a first gallium nitride layer 202 and a second gallium nitride layer 206 …
FIG. 5) has removed and a third hardmask 244 10 is patterned over the n-channel gallium nitride transistor 230. The p-channel gallium nitride transistor 250 …
FIG. 6, the second gallium nitride layer 206 in the unmasked portion 224 designated for the subsequent formation of an n-channel gallium 25 nitride circuit …
FIG. 7, an n-channel gallium nitride transistor 230 may be formed in the portion 224 af t er a second hardmask 228 is patterned on the portion 220 designated …
FIG. 8) may be removed and at least one interlayer dielectric layer 272 may be deposited over the n-channel gallium nitride transistor 230 and the p-channel …
FIG. 9, conductive traces 286 may be formed to appropriately connect components of the n-channel gallium nitride transistor 230 and the p-channel gallium …
FIG. 10 is a side cross-section view of a gallium nitride circuit structure, according to another embodiment of the present description. FIGs. 11 and 12 are …
FIG. 11, the p-channel 30 gallium nitride transistor 250 may be stacked on top of the n-channel gallium nitride transistor 230, so that a common gate 302 could …
FIG. 12, which is a cross-sectional view along line 12-12 of
FIG. 13 is a side cross-section view of a gallium nitride circuit structure, according to a further embodiment of the present description.
FIG. 14 is a side cross-section view of a gallium nitride circuit structure, according to another embodiment of the present description. 15
FIG. 15 is a flow chart of a process of fabricating a gallium nitride circuit structure, according to an embodiment of the present description.
FIG. 16 illustrates a computing device in accordance with one implementation of the present description.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A CMOS circuit structure comprising: a layered structure including a first gallium nitride layer and a second gallium nitride layer separated by a polarization layer, wherein the layered structure includes an polarization layer intermediate surface and wherein a thickness between the polarization layer intermediate surface and an interface between the first gallium nitride layer and the polarization layer is less than about 20 nm; a first transistor formed proximate the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and a second the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The CMOS circuit structure of claim 1, wherein the p-channel transistor is an enhancement mode transistor. Original
The CMOS circuit structure of claim 1, wherein the n-channel transistor is an enhancement mode transistor. Previously presented
The CMOS circuit structure of claim 1, wherein the polarization layer is selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, indium gallium nitride, aluminum nitride, and aluminum indium gallium nitride. Original
The CMOS circuit structure of claim 1, further including a strain material layer, wherein the first gallium nitride layer abuts the strain material layer. Original
The CMOS circuit structure of claim 1, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The CMOS circuit structure of claim 1, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the p-channel transistor is formed proximate the polarization layer intermediate surface and the n-channel transistor is formed proximate the first gallium nitride layer. Original
A method of fabricating a CMOS circuit structure comprising: forming a layered structure comprising depositing a polarization layer on a first gallium nitride layer and depositing a second gallium nitride layer on the polarization layer; removing a portion of one of the first gallium nitride layer and the second gallium nitride layer and a portion of the polarization layer to form a polarization layer intermediate surface and wherein a thickness between the polarization layer intermediate surface and an interface between the first gallium nitride layer and the polarization layer is less than about 20 nm; forming a first transistor on the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and forming a second the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The method of claim 11, wherein forming the p-channel transistor comprises forming a p-channel enhancement mode transistor. Original
The method of claim 11, wherein forming the n-channel transistor comprises forming an n-channel enhancement mode transistor. Previously presented
The method of claim 11, wherein depositing the polarization layer comprises depositing a material selected from the group consisting of aluminum gallium nitride, aluminum indium nitride, indium gallium nitride, aluminum nitride, and aluminum indium gallium nitride. Original
The method of claim 11, further comprising depositing the first gallium nitride layer on a strain material layer. Original
The method of claim 11, wherein forming the layered structure includes forming a 2D electron gas within the first gallium nitride layer proximate the polarization layer and forming a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The method of claim I1, wherein forming the layered structure includes forming a 2D electron gas within the first gallium nitride layer proximate the polarization layer and forming a 2D hole gas within the second gallium nitride laye r; and wherein the p-channel transistor is for m ed proximate the polarization layer intermediate surface and the n-channel transistor is for m ed proximate the first gallium nitride layer. Original
(Or ig inal) The method of claim 19, further including forming a recess in the first gallium nitride layer to disrupt a portion of the 2D electron gas. Original
An electronic system, comprising: a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one CMOS circuit structure comprising: a layered structure including a first gallium nitride layer and a second gallium nitride layer separated by a polarization layer, wherein the layered structure includes an polarization layer intermediate surface and wherein a thickness between the polarization layer inter m ediate su r face and an interface between the fi r st gallium nitride layer and the polarization layer is less than about 20 nm; a first transistor formed proximate the polarization layer intermediate surface, wherein the first transistor includes at least one source/drain structure extending through a portion of the polarization layer and into the first gallium nitride layer, and wherein the first transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the first gallium nitride layer and the polarization layer, and wherein the first transistor is one of a p-channel transistor and a n-channel transistor; and a second transistor formed on the second gallium nitride layer, wherein the first transistor includes at least one source/drain structure extending into the second gallium nitride layer, wherein the second transistor includes a gate dielectric and a gate electrode, wherein the gate dielectric contacts the second gallium nitride, and wherein the second transistor is one of a p-channel transistor and a n-channel transistor differing from the first transistor. Currently amended
The electronic system of claim 21, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the polarization layer and a 2D hole gas within the second gallium nitride layer; and wherein the n-channel transistor is formed proximate the polarization layer intermediate surface and the p-channel transistor is formed proximate the second gallium nitride layer. Original
The electronic system of claim 21, wherein the layered structure includes a 2D electron gas within the first gallium nitride layer proximate the second gallium nitride layer; and wherein the polarization layer intermediate surface and the gallium nitride layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaN CMOS circuit structure
n-channel gallium nitride transistor
Materials described outside the worked examples.
first gallium nitride layer
GaN
aluminum gallium nitride
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5) has removed and a third hardmask 244 10 is patterned over the n-channel gallium nitride transistor 230. The p-channel gallium nitride transistor 250 …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN bandgap | 3.4 eV | GaN |
GaN electron mobility |
Related documents with shared materials, methods, properties, or citations.
p-channel gallium nitride transistor
aluminum indium nitride
AlInN
indium gallium nitride
InGaN
aluminum nitride
AlN
aluminum indium gallium nitride
AlInGaN
strain material layer
FIG. 7, an n-channel gallium nitride transistor 230 may be formed in the portion 224 af t er a second hardmask 228 is patterned on the portion 220 designated …
FIG. 8) may be removed and at least one interlayer dielectric layer 272 may be deposited over the n-channel gallium nitride transistor 230 and the p-channel …
FIG. 9, conductive traces 286 may be formed to appropriately connect components of the n-channel gallium nitride transistor 230 and the p-channel gallium …
FIG. 11, the p-channel 30 gallium nitride transistor 250 may be stacked on top of the n-channel gallium nitride transistor 230, so that a common gate 302 could …
GaN |
GaN hole mobility (zero strain) | 100 cm2/Vs | GaN |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 20 nm | — |
p-channel gallium nitride transistor
aluminum indium nitride
AlInN
indium gallium nitride
InGaN
aluminum nitride
AlN
aluminum indium gallium nitride
AlInGaN
strain material layer
FIG. 7, an n-channel gallium nitride transistor 230 may be formed in the portion 224 af t er a second hardmask 228 is patterned on the portion 220 designated …
FIG. 8) may be removed and at least one interlayer dielectric layer 272 may be deposited over the n-channel gallium nitride transistor 230 and the p-channel …
FIG. 9, conductive traces 286 may be formed to appropriately connect components of the n-channel gallium nitride transistor 230 and the p-channel gallium …
FIG. 11, the p-channel 30 gallium nitride transistor 250 may be stacked on top of the n-channel gallium nitride transistor 230, so that a common gate 302 could …
GaN |
GaN hole mobility (zero strain) | 100 cm2/Vs | GaN |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 20 nm | — |
p-channel gallium nitride transistor
aluminum indium nitride
AlInN
indium gallium nitride
InGaN
aluminum nitride
AlN
aluminum indium gallium nitride
AlInGaN
strain material layer
FIG. 7, an n-channel gallium nitride transistor 230 may be formed in the portion 224 af t er a second hardmask 228 is patterned on the portion 220 designated …
FIG. 8) may be removed and at least one interlayer dielectric layer 272 may be deposited over the n-channel gallium nitride transistor 230 and the p-channel …
FIG. 9, conductive traces 286 may be formed to appropriately connect components of the n-channel gallium nitride transistor 230 and the p-channel gallium …
FIG. 11, the p-channel 30 gallium nitride transistor 250 may be stacked on top of the n-channel gallium nitride transistor 230, so that a common gate 302 could …
GaN |
GaN hole mobility (zero strain) | 100 cm2/Vs | GaN |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 20 nm | — |
p-channel gallium nitride transistor
aluminum indium nitride
AlInN
indium gallium nitride
InGaN
aluminum nitride
AlN
aluminum indium gallium nitride
AlInGaN
strain material layer
FIG. 7, an n-channel gallium nitride transistor 230 may be formed in the portion 224 af t er a second hardmask 228 is patterned on the portion 220 designated …
FIG. 8) may be removed and at least one interlayer dielectric layer 272 may be deposited over the n-channel gallium nitride transistor 230 and the p-channel …
FIG. 9, conductive traces 286 may be formed to appropriately connect components of the n-channel gallium nitride transistor 230 and the p-channel gallium …
FIG. 11, the p-channel 30 gallium nitride transistor 250 may be stacked on top of the n-channel gallium nitride transistor 230, so that a common gate 302 could …
GaN |
GaN hole mobility (zero strain) | 100 cm2/Vs | GaN |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 20 nm | — |