RESISTOR AND RESISTOR-TRANSISTOR-LOGIC CIRCUIT WITH GaN STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Kuo-Hsing Lee; Sheng-Yuan Hsueh; Chien-Liang Wu; Te-Wei Yeh; Yi-Chun Chen

Patent

Atlas literature

Patent

US 12,132,043 B2

RESISTOR AND RESISTOR-TRANSISTOR-LOGIC CIRCUIT WITH GaN STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Te-Wei Yeh et al.

UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)·Oct. 29, 2024·US

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 is a schematic plan view of a 2DEG resistor in 5 accordance with the preferred embodiment of present inven- tion;

FIG. 2

FIG. 2 is a cross-section along the section line A-A' in

FIG. 3

FIG. 3 is a schematic plan view of low-voltage logic FETs 10 in accordance with the preferred embodiment of present invention;

FIG. 4

FIG. 4 is a cross-section along the section line B-B' in

FIG. 5

FIG. 5 is a schematic plan view of high-voltage HEMTs in accordance with the preferred embodiment of present invention;

FIG. 6

FIG. 6 is a cross-section along the section line C-C' in

FIG. 7

FIG. 7 is a schematic plan view and a circuit diagram of a resistor-transistor-logic inverter (INV) circuit structure in accordance with the preferred …

FIG. 8

FIG. 8 is a schematic plan view and a circuit diagram of 25 a resistor-transistor-logic NAND circuit structure in accor- dance with the preferred embodiment of …

FIG. 9

FIG. 9 is a schematic plan view and a circuit diagram of a resistor-transistor-logic NOR circuit structure in accor- dance with the preferred embodiment of …

FIG. 10

FIG. 10 is a schematic plan view of three different kinds of resistors, including a 2DEG resistor, an undoped poly- silicon resistor and a doped polysilicon …

FIG. 11

FIG. 11 is cross-sections along the section lines A-A', 35 D-D' and E-E' in

FIG. 12

FIG. 12 is a schematic plan view of high-voltage HEMTs with ﬁeld plate structures in accordance with another embodiment of present invention;

FIG. 13

FIG. 13 is a cross-section along the section line C-C' in 40

FIG. 14

FIG. 14 is a cross-section of high-voltage HEMTs with upper metal interconnect resistors in accordance with another embodiment of present invention. It should …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

3 independent · 8 dependent

1
IndependentGaNAlGaNGaN:p2DEG resistorlogic FET (inverter)
A resistor-transistor-logic inverter circuit with GaN structures, comprising: a 2DEG resistor, wherein a drain of said 2DEG resistor is connected with an operating voltage, and said 2DEG resistor further comprises: a GaN layer; an AlGaN barrier layer on said GaN layer; and multiple p-type doped GaN capping layers, wherein parts of said multiple p-type doped GaN capping layers are arranged in a staggered arrangement on said AlGaN barrier layer and not directly connected with any interconnects or not applied with voltages, so that said GaN layer not covered by said parts of said p-type doped GaN capping layers forms a winding pattern and is converted into said 2DEG resistor; and a logic FET, wherein a gate of said logic FET is connected to an input voltage, a source of said logic FET is grounded, and a drain of said logic FET and a source of said 2DEG resistor are connected with each other and are connected collectively to an output voltage.
1. 2
  Dependent← claim 12DEG resistorlogic FET (inverter)
  The resistor-transistor-logic inverter circuit with GaN structures of claim 1, wherein in an operation, when said input voltage equals said operating voltage, said logic FET is turned ON and said output voltage is approximately equal to a ground voltage, when said input voltage equals 0V, said logic FET is in cut-off state and said output voltage is approximately equal to said operating voltage.
2. 3
  Dependent← claim 1GaNAlGaNGaN:plogic FET (inverter)
  The resistor-transistor-logic inverter circuit with GaN structures of claim 1, wherein said logic FET comprises: said GaN layer; said AlGaN barrier layer on said GaN layer; one of said multiple p-type doped GaN capping layers on said AlGaN barrier layer, wherein said one of said multiple p-type doped GaN capping layers converts said GaN layer under said one of said multiple p-type doped GaN capping layers into gate depletion regions; said gate formed on said one of said multiple p-type doped GaN capping layer; and said source and said drain formed on said GaN layer at two sides of said gate respectively, wherein said gate, said source and said drain constitute said logic FET.
4
IndependentGaNAlGaNGaN:p2DEG resistorlogic FET pair (NAND, series)
A resistor-transistor-logic NAND circuit with GaN structures, comprising: a 2DEG resistor, wherein a drain of said 2DEG resistor is connected with an operating voltage, and said 2DEG resistor further comprises: a GaN layer; an AlGaN barrier layer on said GaN layer; and multiple p-type doped GaN capping layers, wherein parts of said multiple p-type doped GaN capping layers are arranged in a staggered arrangement on said AlGaN barrier layer and not directly connected with any interconnects or not applied with voltages, so that said GaN layer not covered by said parts of said multiple p-type doped GaN capping layers forms a winding pattern and is converted into said 2DEG resistor; a ﬁrst logic FET, wherein a gate of said ﬁrst logic FET is connected to a ﬁrst input voltage, and a source of said ﬁrst logic FET is grounded; and a second logic FET, wherein a gate of said second logic FET is connected to a second input voltage, a drain of said second logic FET and a source of said 2DEG resistor are connected with each other and are con-nected collectively to an output voltage, a source of said second logic FET is connected with a drain of said ﬁrst logic FET, and said ﬁrst logic FET and said second logic FET are in serious connection.
1. 5
  Dependent← claim 4logic FET pair (NAND, series)
  The resistor-transistor-logic NAND circuit with GaN structures of claim 4, wherein in an operation, when said ﬁrst input voltage and said second input voltage equal said operating voltage, said ﬁrst logic FET and said second logic FET are turned ON and said output voltage is approximately equal to a ground voltage, when said ﬁrst input voltage and said second input voltage equal 0V, said ﬁrst logic FET and said second logic FET are in cut-off state and said output voltage is approximately equal to said operating voltage.
2. 6
  Dependent← claim 4GaNAlGaNGaN:plogic FET pair (NAND, series)
  The resistor-transistor-logic NAND circuit with GaN structures of claim 4, wherein said ﬁrst logic FET and said 25 second logic FET comprise: a said GaN layer; said AlGaN barrier layer on said GaN layer; two of said multiple p-type doped GaN capping layers on said AlGaN barrier layer, wherein said two of said multiple p-type doped GaN capping layers convert said GaN layer under said two of said multiple p-type doped GaN capping layers into gate depletion regions; two gates formed respectively on said two of said multiple p-type doped GaN capping layers; said source and said drain of said ﬁrst logic FET formed on said GaN layer at two sides of said gate of said ﬁrst logic FET; and said source and said drain of said second logic FET formed on said GaN layer at two sides of said gate of 40 second logic FET.
8
IndependentGaNAlGaNGaN:p2DEG resistorlogic FET pair (NOR, parallel)
A resistor-transistor-logic NOR circuit with GaN struc-tures, comprising: a 2DEG resistor, wherein a drain of said 2DEG resistor is connected with an operating voltage, and said 2DEG resistor further comprises: a GaN layer; an AlGaN barrier layer on said GaN layer; and B₂ multiple p-type doped GaN capping layers, wherein parts of said multiple p-type doped GaN capping layers are arranged in a staggered arrangement on said AlGaN barrier layer and not directly connected with any interconnects or not applied with voltages, so that said GaN layer not covered by said parts of said multiple p-type doped GaN capping layers forms a winding pattern and is converted into said 2DEG resistor; a ﬁrst logic FET, wherein a gate of said ﬁrst logic FET is connected to a ﬁrst input voltage, and a source of said ﬁrst logic FET is grounded; and a second logic FET, wherein a gate of said second logic FET is connected to a second input voltage, a source of said second logic FET is grounded, a drain of said second logic FET and a drain of said ﬁrst logic FET are connected to a common output voltage and are con-nected collectively to a source of said 2DEG resistor, and said ﬁrst logic FET and said second logic FET are in parallel connection.
1. 9
  Dependent← claim 8logic FET pair (NOR, parallel)
  The resistor-transistor-logic NOR circuit with GaN structures of claim 8, wherein in an operation, only when said ﬁrst input voltage and said second input voltage both equal 0V, said output voltage is approximately equal to said operating voltage, and when said ﬁrst input voltage and said second input voltage are both in said operating voltage or one of them is in said operating voltage, at least one of said ﬁrst logic FET and said second logic FET is turn ON to make said output voltage approximately equal to a ground voltage.
2. 10
  Dependent← claim 8GaNAlGaNGaN:plogic FET pair (NOR, parallel)
  The resistor-transistor-logic NOR circuit with GaN structures of claim 8, wherein said ﬁrst logic FET and said second logic FET comprise: said GaN layer; said AlGaN barrier layer on said GaN layer; two of said multiple p-type doped GaN capping layers on said AlGaN barrier layer, wherein said two of said multiple p-type doped GaN capping layers convert said GaN layer under said two of said multiple p-type doped GaN capping layers into gate depletion regions; two gates formed respectively on said two of said multiple p-type doped GaN capping layers; said source and said drain of said ﬁrst logic FET formed on said GaN layer at two sides of said gate of said ﬁrst logic FET; and said source and said drain of said second logic FET formed on said GaN layer at two sides of said gate of second logic FET.

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

2DEG resistor

GaN:ppatterned capping

AlGaNbarrier

GaNchannel

logic FET (inverter)

GaN:pgate capping

AlGaNbarrier

GaN

Materials

Materials described outside the worked examples.

GaN

Channel Layer

AlGaN

Barrier Layer

Characterization

Measurements and analyses referenced in the patent, with their drawing references.

fet electrical

Fet Electrical

FIG. 3 is a schematic plan view of low-voltage logic FETs 10 in accordance with the preferred embodiment of present invention;

Figure references

FIG. 3

fet electrical

Cited prior art

Patents and literature cited by this patent (applicant and examiner references).

Cited patents · 18

US 9,660,064 B29,660,064 B2 5/2017 Dasgupta
US 9,761,675 B19,761,675 B1 9/2017 Marinella
US 10,720,913 B110,720,913 B1 7/2020 Leong
US 2006/0088973 A12006/0088973 A1 4/2006 Chun
US 2007/0176295 A12007/0176295 A1 8/2007 Chinthakindi
US 2011/0057196 A12011/0057196 A1 3/2011 Chang
US 2015/0061076 A12015/0061076 A1 3/2015 Cheng

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RESISTOR AND RESISTOR-TRANSISTOR-LOGIC CIRCUIT WITH GaN STRUCTURE AND METHOD OF MANUFACTURING THE SAME | Matter42 Literature