Patent
US 8,947,154METHOD AND SYSTEM FOR OPERATING GALLIUM NITRIDE ELECTRONICS
Hemal N. Shah
US
Copyright © 2026 Matter42. All rights reserved.
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US 8,947,154Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, an IGBT gate driver 126 is used to drive a three-terminal GaN transistor circuit 120, including a GaN JFET driver 122, and a GaN JFET 124 (which may …
FIG. 2, an example optional current/Vd s mo nit or ing ci r cuit 240 is illustrated. The current monitoring circuit 240 may monitor the current through main …
FIG. 3. The graph at 502 shows the input pulse voltage of voltage source V₃ 300. As can be seen, the input voltage V₃ 300 is pulsed between +15 V and -15 V. …
FIG. 4 is a simplified flowchart illustrating a method of operating an IGBT gate 10 driver in conjunction with a GaN transistor according to an embodiment of the …
FIG. 5 illustrates the behavior of the exemplary schematic diagram of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. An electronic circuit comprising: 2 a driver comprising: 3 a bias voltage generator configured to receive a voltage input and 4 generate a biased voltage output based on the voltage input; 5 a supplementary transistor having a gate, a drain, and a source, 6 wherein: 7 the gate of the supplementary transistor is coupled to the 8 biased voltage output of the bias voltage generator; and 9 the source of the supplementary transistor provides a 10 current to the bias voltage generator; and 11 an output driver configured to: 12 receive the biased voltage output from the bias voltage 13 generator and the voltage input; 14 receive the voltage input; and output a drive voltage; and 16 a main transistor having a gate, a drain, and a source, wherein: 17 the gate of the main transistor is coupled to the drive voltage; and 18 the drain of the main transistor is coupled to the drain of the 19 supplementary transistor.
1 2. The electronic circuit of claim 1, wherein the supplementary 2 transistor is a GaN transistor, such that: 3 the drain of the supplementary transistor comprises a GaN substrate and a 4 drain contact; 5 the source of the supplementary transistor is separated from the GaN 6 substrate by a drift region and comprises a source contact; 7 the drift region of the supplementary transistor comprises a first GaN 8 epitaxial layer coupled to the GaN substrate; and 17 9 the gate of the supplementary transistor comprises a second GaN epitaxial 10 layer coupled to the first GaN epitaxial layer and a gate contact coupled to the biased 11 voltage output of the bias voltage generator.
1 3. The electronic circuit of claim 1, the driver further comprising a 2 current monitor configured to detect a current from the drain to the source of the 3 supplementary transistor and output a regulated current, wherein the output driver further 4 is configured to receive the regulated current from the current monitor.
1 4. The electronic circuit of claim 1 wherein the current monitor 2 regulates the current from the drain of the supplementary transistor to the source of the 3 supplementary transistor.
1 5. The electronic circuit of claim 1 wherein the supplementary 2 transistor and the main transistor are junction gate field-effect transistors (JF E T).
1 6. The electronic circuit of claim 1 wherein the output driver is a 2 voltage converter.
1 8. The electronic circuit of claim 1 wherein the driver and the main 2 transistor are co-packaged in a same package.
1 11. A method of operating a GaN JF E T, the method comprising: 2 receiving, at a GaN JF E T driver, an input voltage; 3 generating a biased voltage output based on the input voltage; 18 4 monitoring a current of a supplementary transistor to provide a current 5 value; 6 receiving, at an output driver, the biased voltage output, the current value, 7 and the input voltage; 8 generating an output drive voltage based on the biased voltage output, the 9 current value, and the input voltage; and 10 providing, to the GaN JFET, the output drive voltage.
1 12. The method of claim 11 wherein the input voltage comprises a 2 pulsed input voltage.
1 13. The method of claim 11 wherein the current value is based on the 2 current from the drain to the source of the supplementary transistor.
1 14. The method of claim 11 wherein the output drive voltage is 2 characterized by a lower amplitude than the input voltage.
1 15. The method of claim 11 wherein the supplementary transistor 2 comprises a GaN FET.
1 16. The method of claim 11 wherein the output drive voltage is 2 generated by a voltage converter.
1 18. The method of claim 11 further comprising packaging the driver 2 and the main transistor in a same package.
Layer stacks claimed or described, ordered top of device to substrate.
electronic circuit with GaN JFET driver and main transistor
No layer stack recorded.
GaN supplementary transistor with GaN substrate, drift region, and epitaxial gate
junction gate field-effect transistor (JFET)
No layer stack recorded.
GaN JFET main transistor
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, an IGBT gate driver 126 is used to drive a three-terminal GaN transistor circuit 120, including a GaN JFET driver 122, and a GaN JFET 124 (which may …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–400 V | — |
Voltage | 20–40 V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,947,154Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, an IGBT gate driver 126 is used to drive a three-terminal GaN transistor circuit 120, including a GaN JFET driver 122, and a GaN JFET 124 (which may …
FIG. 2, an example optional current/Vd s mo nit or ing ci r cuit 240 is illustrated. The current monitoring circuit 240 may monitor the current through main …
FIG. 3. The graph at 502 shows the input pulse voltage of voltage source V₃ 300. As can be seen, the input voltage V₃ 300 is pulsed between +15 V and -15 V. …
FIG. 4 is a simplified flowchart illustrating a method of operating an IGBT gate 10 driver in conjunction with a GaN transistor according to an embodiment of the …
FIG. 5 illustrates the behavior of the exemplary schematic diagram of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. An electronic circuit comprising: 2 a driver comprising: 3 a bias voltage generator configured to receive a voltage input and 4 generate a biased voltage output based on the voltage input; 5 a supplementary transistor having a gate, a drain, and a source, 6 wherein: 7 the gate of the supplementary transistor is coupled to the 8 biased voltage output of the bias voltage generator; and 9 the source of the supplementary transistor provides a 10 current to the bias voltage generator; and 11 an output driver configured to: 12 receive the biased voltage output from the bias voltage 13 generator and the voltage input; 14 receive the voltage input; and output a drive voltage; and 16 a main transistor having a gate, a drain, and a source, wherein: 17 the gate of the main transistor is coupled to the drive voltage; and 18 the drain of the main transistor is coupled to the drain of the 19 supplementary transistor.
1 2. The electronic circuit of claim 1, wherein the supplementary 2 transistor is a GaN transistor, such that: 3 the drain of the supplementary transistor comprises a GaN substrate and a 4 drain contact; 5 the source of the supplementary transistor is separated from the GaN 6 substrate by a drift region and comprises a source contact; 7 the drift region of the supplementary transistor comprises a first GaN 8 epitaxial layer coupled to the GaN substrate; and 17 9 the gate of the supplementary transistor comprises a second GaN epitaxial 10 layer coupled to the first GaN epitaxial layer and a gate contact coupled to the biased 11 voltage output of the bias voltage generator.
1 3. The electronic circuit of claim 1, the driver further comprising a 2 current monitor configured to detect a current from the drain to the source of the 3 supplementary transistor and output a regulated current, wherein the output driver further 4 is configured to receive the regulated current from the current monitor.
1 4. The electronic circuit of claim 1 wherein the current monitor 2 regulates the current from the drain of the supplementary transistor to the source of the 3 supplementary transistor.
1 5. The electronic circuit of claim 1 wherein the supplementary 2 transistor and the main transistor are junction gate field-effect transistors (JF E T).
1 6. The electronic circuit of claim 1 wherein the output driver is a 2 voltage converter.
1 8. The electronic circuit of claim 1 wherein the driver and the main 2 transistor are co-packaged in a same package.
1 11. A method of operating a GaN JF E T, the method comprising: 2 receiving, at a GaN JF E T driver, an input voltage; 3 generating a biased voltage output based on the input voltage; 18 4 monitoring a current of a supplementary transistor to provide a current 5 value; 6 receiving, at an output driver, the biased voltage output, the current value, 7 and the input voltage; 8 generating an output drive voltage based on the biased voltage output, the 9 current value, and the input voltage; and 10 providing, to the GaN JFET, the output drive voltage.
1 12. The method of claim 11 wherein the input voltage comprises a 2 pulsed input voltage.
1 13. The method of claim 11 wherein the current value is based on the 2 current from the drain to the source of the supplementary transistor.
1 14. The method of claim 11 wherein the output drive voltage is 2 characterized by a lower amplitude than the input voltage.
1 15. The method of claim 11 wherein the supplementary transistor 2 comprises a GaN FET.
1 16. The method of claim 11 wherein the output drive voltage is 2 generated by a voltage converter.
1 18. The method of claim 11 further comprising packaging the driver 2 and the main transistor in a same package.
Layer stacks claimed or described, ordered top of device to substrate.
electronic circuit with GaN JFET driver and main transistor
No layer stack recorded.
GaN supplementary transistor with GaN substrate, drift region, and epitaxial gate
junction gate field-effect transistor (JFET)
No layer stack recorded.
GaN JFET main transistor
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, an IGBT gate driver 126 is used to drive a three-terminal GaN transistor circuit 120, including a GaN JFET driver 122, and a GaN JFET 124 (which may …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–400 V | — |
Voltage | 20–40 V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,947,154Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, an IGBT gate driver 126 is used to drive a three-terminal GaN transistor circuit 120, including a GaN JFET driver 122, and a GaN JFET 124 (which may …
FIG. 2, an example optional current/Vd s mo nit or ing ci r cuit 240 is illustrated. The current monitoring circuit 240 may monitor the current through main …
FIG. 3. The graph at 502 shows the input pulse voltage of voltage source V₃ 300. As can be seen, the input voltage V₃ 300 is pulsed between +15 V and -15 V. …
FIG. 4 is a simplified flowchart illustrating a method of operating an IGBT gate 10 driver in conjunction with a GaN transistor according to an embodiment of the …
FIG. 5 illustrates the behavior of the exemplary schematic diagram of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. An electronic circuit comprising: 2 a driver comprising: 3 a bias voltage generator configured to receive a voltage input and 4 generate a biased voltage output based on the voltage input; 5 a supplementary transistor having a gate, a drain, and a source, 6 wherein: 7 the gate of the supplementary transistor is coupled to the 8 biased voltage output of the bias voltage generator; and 9 the source of the supplementary transistor provides a 10 current to the bias voltage generator; and 11 an output driver configured to: 12 receive the biased voltage output from the bias voltage 13 generator and the voltage input; 14 receive the voltage input; and output a drive voltage; and 16 a main transistor having a gate, a drain, and a source, wherein: 17 the gate of the main transistor is coupled to the drive voltage; and 18 the drain of the main transistor is coupled to the drain of the 19 supplementary transistor.
1 2. The electronic circuit of claim 1, wherein the supplementary 2 transistor is a GaN transistor, such that: 3 the drain of the supplementary transistor comprises a GaN substrate and a 4 drain contact; 5 the source of the supplementary transistor is separated from the GaN 6 substrate by a drift region and comprises a source contact; 7 the drift region of the supplementary transistor comprises a first GaN 8 epitaxial layer coupled to the GaN substrate; and 17 9 the gate of the supplementary transistor comprises a second GaN epitaxial 10 layer coupled to the first GaN epitaxial layer and a gate contact coupled to the biased 11 voltage output of the bias voltage generator.
1 3. The electronic circuit of claim 1, the driver further comprising a 2 current monitor configured to detect a current from the drain to the source of the 3 supplementary transistor and output a regulated current, wherein the output driver further 4 is configured to receive the regulated current from the current monitor.
1 4. The electronic circuit of claim 1 wherein the current monitor 2 regulates the current from the drain of the supplementary transistor to the source of the 3 supplementary transistor.
1 5. The electronic circuit of claim 1 wherein the supplementary 2 transistor and the main transistor are junction gate field-effect transistors (JF E T).
1 6. The electronic circuit of claim 1 wherein the output driver is a 2 voltage converter.
1 8. The electronic circuit of claim 1 wherein the driver and the main 2 transistor are co-packaged in a same package.
1 11. A method of operating a GaN JF E T, the method comprising: 2 receiving, at a GaN JF E T driver, an input voltage; 3 generating a biased voltage output based on the input voltage; 18 4 monitoring a current of a supplementary transistor to provide a current 5 value; 6 receiving, at an output driver, the biased voltage output, the current value, 7 and the input voltage; 8 generating an output drive voltage based on the biased voltage output, the 9 current value, and the input voltage; and 10 providing, to the GaN JFET, the output drive voltage.
1 12. The method of claim 11 wherein the input voltage comprises a 2 pulsed input voltage.
1 13. The method of claim 11 wherein the current value is based on the 2 current from the drain to the source of the supplementary transistor.
1 14. The method of claim 11 wherein the output drive voltage is 2 characterized by a lower amplitude than the input voltage.
1 15. The method of claim 11 wherein the supplementary transistor 2 comprises a GaN FET.
1 16. The method of claim 11 wherein the output drive voltage is 2 generated by a voltage converter.
1 18. The method of claim 11 further comprising packaging the driver 2 and the main transistor in a same package.
Layer stacks claimed or described, ordered top of device to substrate.
electronic circuit with GaN JFET driver and main transistor
No layer stack recorded.
GaN supplementary transistor with GaN substrate, drift region, and epitaxial gate
junction gate field-effect transistor (JFET)
No layer stack recorded.
GaN JFET main transistor
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, an IGBT gate driver 126 is used to drive a three-terminal GaN transistor circuit 120, including a GaN JFET driver 122, and a GaN JFET 124 (which may …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–400 V | — |
Voltage | 20–40 V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,947,154Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, an IGBT gate driver 126 is used to drive a three-terminal GaN transistor circuit 120, including a GaN JFET driver 122, and a GaN JFET 124 (which may …
FIG. 2, an example optional current/Vd s mo nit or ing ci r cuit 240 is illustrated. The current monitoring circuit 240 may monitor the current through main …
FIG. 3. The graph at 502 shows the input pulse voltage of voltage source V₃ 300. As can be seen, the input voltage V₃ 300 is pulsed between +15 V and -15 V. …
FIG. 4 is a simplified flowchart illustrating a method of operating an IGBT gate 10 driver in conjunction with a GaN transistor according to an embodiment of the …
FIG. 5 illustrates the behavior of the exemplary schematic diagram of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. An electronic circuit comprising: 2 a driver comprising: 3 a bias voltage generator configured to receive a voltage input and 4 generate a biased voltage output based on the voltage input; 5 a supplementary transistor having a gate, a drain, and a source, 6 wherein: 7 the gate of the supplementary transistor is coupled to the 8 biased voltage output of the bias voltage generator; and 9 the source of the supplementary transistor provides a 10 current to the bias voltage generator; and 11 an output driver configured to: 12 receive the biased voltage output from the bias voltage 13 generator and the voltage input; 14 receive the voltage input; and output a drive voltage; and 16 a main transistor having a gate, a drain, and a source, wherein: 17 the gate of the main transistor is coupled to the drive voltage; and 18 the drain of the main transistor is coupled to the drain of the 19 supplementary transistor.
1 2. The electronic circuit of claim 1, wherein the supplementary 2 transistor is a GaN transistor, such that: 3 the drain of the supplementary transistor comprises a GaN substrate and a 4 drain contact; 5 the source of the supplementary transistor is separated from the GaN 6 substrate by a drift region and comprises a source contact; 7 the drift region of the supplementary transistor comprises a first GaN 8 epitaxial layer coupled to the GaN substrate; and 17 9 the gate of the supplementary transistor comprises a second GaN epitaxial 10 layer coupled to the first GaN epitaxial layer and a gate contact coupled to the biased 11 voltage output of the bias voltage generator.
1 3. The electronic circuit of claim 1, the driver further comprising a 2 current monitor configured to detect a current from the drain to the source of the 3 supplementary transistor and output a regulated current, wherein the output driver further 4 is configured to receive the regulated current from the current monitor.
1 4. The electronic circuit of claim 1 wherein the current monitor 2 regulates the current from the drain of the supplementary transistor to the source of the 3 supplementary transistor.
1 5. The electronic circuit of claim 1 wherein the supplementary 2 transistor and the main transistor are junction gate field-effect transistors (JF E T).
1 6. The electronic circuit of claim 1 wherein the output driver is a 2 voltage converter.
1 8. The electronic circuit of claim 1 wherein the driver and the main 2 transistor are co-packaged in a same package.
1 11. A method of operating a GaN JF E T, the method comprising: 2 receiving, at a GaN JF E T driver, an input voltage; 3 generating a biased voltage output based on the input voltage; 18 4 monitoring a current of a supplementary transistor to provide a current 5 value; 6 receiving, at an output driver, the biased voltage output, the current value, 7 and the input voltage; 8 generating an output drive voltage based on the biased voltage output, the 9 current value, and the input voltage; and 10 providing, to the GaN JFET, the output drive voltage.
1 12. The method of claim 11 wherein the input voltage comprises a 2 pulsed input voltage.
1 13. The method of claim 11 wherein the current value is based on the 2 current from the drain to the source of the supplementary transistor.
1 14. The method of claim 11 wherein the output drive voltage is 2 characterized by a lower amplitude than the input voltage.
1 15. The method of claim 11 wherein the supplementary transistor 2 comprises a GaN FET.
1 16. The method of claim 11 wherein the output drive voltage is 2 generated by a voltage converter.
1 18. The method of claim 11 further comprising packaging the driver 2 and the main transistor in a same package.
Layer stacks claimed or described, ordered top of device to substrate.
electronic circuit with GaN JFET driver and main transistor
No layer stack recorded.
GaN supplementary transistor with GaN substrate, drift region, and epitaxial gate
junction gate field-effect transistor (JFET)
No layer stack recorded.
GaN JFET main transistor
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, an IGBT gate driver 126 is used to drive a three-terminal GaN transistor circuit 120, including a GaN JFET driver 122, and a GaN JFET 124 (which may …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–400 V | — |
Voltage | 20–40 V |
Related documents with shared materials, methods, properties, or citations.
FIG. 2, an example optional current/Vd s mo nit or ing ci r cuit 240 is illustrated. The current monitoring circuit 240 may monitor the current through main …
FIG. 3. The graph at 502 shows the input pulse voltage of voltage source V₃ 300. As can be seen, the input voltage V₃ 300 is pulsed between +15 V and -15 V. …
FIG. 4 is a simplified flowchart illustrating a method of operating an IGBT gate 10 driver in conjunction with a GaN transistor according to an embodiment of the …
| — |
Voltage | ≥ 1 V | — |
FIG. 2, an example optional current/Vd s mo nit or ing ci r cuit 240 is illustrated. The current monitoring circuit 240 may monitor the current through main …
FIG. 3. The graph at 502 shows the input pulse voltage of voltage source V₃ 300. As can be seen, the input voltage V₃ 300 is pulsed between +15 V and -15 V. …
FIG. 4 is a simplified flowchart illustrating a method of operating an IGBT gate 10 driver in conjunction with a GaN transistor according to an embodiment of the …
| — |
Voltage | ≥ 1 V | — |
FIG. 2, an example optional current/Vd s mo nit or ing ci r cuit 240 is illustrated. The current monitoring circuit 240 may monitor the current through main …
FIG. 3. The graph at 502 shows the input pulse voltage of voltage source V₃ 300. As can be seen, the input voltage V₃ 300 is pulsed between +15 V and -15 V. …
FIG. 4 is a simplified flowchart illustrating a method of operating an IGBT gate 10 driver in conjunction with a GaN transistor according to an embodiment of the …
| — |
Voltage | ≥ 1 V | — |
FIG. 2, an example optional current/Vd s mo nit or ing ci r cuit 240 is illustrated. The current monitoring circuit 240 may monitor the current through main …
FIG. 3. The graph at 502 shows the input pulse voltage of voltage source V₃ 300. As can be seen, the input voltage V₃ 300 is pulsed between +15 V and -15 V. …
FIG. 4 is a simplified flowchart illustrating a method of operating an IGBT gate 10 driver in conjunction with a GaN transistor according to an embodiment of the …
| — |
Voltage | ≥ 1 V | — |