Patent
US 9,819,316APPARATUS AND METHOD FOR SELF BIAS IN GALLIUM NITRIDE (GaN) AMPLIFIERS
David R. Helms
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,819,316Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a conventional bias circuit for a FET including a source resistor connected to the source electrode of the FET. [0016]
FIG. 2 shows a conventional bias circuit, which uses Schottky diodes to produce a bias voltage. [0017]
FIG. 3 illustrates a bias circuit according to an embodiment of the disclosure using two voltage sources. [0018]
FIG. 4 further illustrating radio frequency (RF) input/output (I/O) connections according to an embodiment of the disclosure. [0020]
FIG. 5 shows the bias circuit of
FIG. 6 shows a bias circuit for providing bias voltage to a GaN FET, the circuit including temperature compensation and an enable circuit according to an …
FIG. 7 is a schematic for a biasing circuit for providing bias voltage to a GaN FET according to an embodiment of the disclosure. {0018 6293;v 1 } 8 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic circuit for providing a bias voltage to an output Gallium Nitride (GaN) field effect transistor (FET) comprising: a first reference GaN FET having a gate, a source and a drain electrode; a positive voltage supply connected to the drain electrode of said first reference GaN FET; a first resistor device having a first terminal end coupled to the drain electrode of the first reference GaN FET, and a second terminal end coupled to the positive voltage supply; a negative voltage supply coupled to said source electrode of said first reference GaN FET via a second reference GaN FET; and an output node terminal coupled to the first terminal end of the first resistor and the drain electrode of said first reference GaN FET for providing the bias voltage to said output GaN FET, wherein said gate electrode of said first reference GaN FET is coupled to said negative voltage supply via a third resistor, and said source electrode of said first reference GaN FET is coupled to said negative voltage supply via said second reference GaN FET, thereby producinq a voltage level at said gate electrode that is less than a voltage level at said source electrode. {00210669;v1} 3 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed
The circuit of claim 1, wherein said second reference GaN FET exhibits a resistance to produce a target bias voltage at said output node terminal.
canceled
A reference bias circuit for providing a desired gate bias voltage to an output wide band gap field effect transistor (FET) comprising: a first reference FET having a gate electrode, a drain electrode coupled to a positive voltage supply, and a source electrode coupled to [[said]] a negative voltage supply; a first resistor coupled between said drain electrode of said first reference FET and said positive voltage supply; a second reference FET coupled between said source electrode of said first reference FET and [[a]]said negative voltage supply; an electrical node connecting said first resistor and said drain electrode of said first reference FET, and coupled to a gate electrode of said output wide band gap FET to provide a reference bias voltage thereto; and {00210669;v1} 4 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed a plurality of diode-connected FETs connected in series between said positive voltage supply and said gate electrode of said first reference FET, said plurality of diode-connected FETs configured to produce a temperature dependent bias voltage at said gate electrode of said first reference FET, to thereby modulate a current between said drain electrode and said source electrode of said first reference FET based on temperature.
The reference bias circuit of claim 6 further comprising: a level shifting resistor coupled between said electrical node (616) and said negative voltage supply, wherein a conductive path is defined from said positive voltage supply through said first resistor, said electrical node and said level shifting resistor to said negative voltage supply.
The reference bias circuit of claim 6, further comprising: an enable circuit comprising: an enable FET having a gate electrode coupled to said negative voltage supplyand supply and to said gate electrode of said output wide band gap FET, a {00210669;v1} 5 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed drain electrode coupled to said source electrode of said first reference FET, and a source electrode coupled to an enable pin; and a pair of series connected resistors connected between said gate electrode of said enable FET and said enable pin, wherein said source electrode of said enable FET is coupled to said enable pinat pin at a node between a first resistor and a second resistor of said pair of series connected resistors.
The reference bias circuit of claim 6, further comprising: a capacitor coupled between said gate electrode of said output wide band gap FET and a reference potential, wherein said capacitor is configured to filter out radio frequency (R F) signals applied at said gate of said output wide band gap FET and prevent said RF signals from reaching said electrical node coupled to said first reference FET.
The reference bias circuit of claim 6, wherein said output wide band gap FET comprises Gallium Nitride (GaN).
The reference bias circuit of claim 6, wherein said first reference FET comprises Gallium Nitride (GaN). {00210669;v1} 6 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed 15. The reference bias circuit of claim 6, wherein said second reference FET comprises Gallium Nitride (GaN).
canceled
The reference bias circuit of claim [[7]]6, wherein each of said plurality of diode-connected FETs comprises Gallium Nitride (GaN).
A circuit for providing bias to an output Gallium Nitride (GaN) field effect transistor (FET) comprising: a radio frequency (R F) input signal applied to a gate electrode of the output GaN FET; a positive voltage source connected to a drain electrode of the output GaN FET; a reference voltage connected to a source electrode of the output GaN FET; [[and]] a reference FET between the source electrode of the output GaN FET and the reference voltage, the reference FET having a drain electrode connected to the source electrode of the output GaN FET, a gate electrode connected to the source electrode of the output GaN FET via a resistor, and a source electrode connected to the reference voltage; and a negative voltage source connected to the gate electrode of the output GaN FET via a filtering resistor and a filtering inductor.
The circuit of claim 16, further comprising: an RF output generated between the positive voltage source and the drain electrode of the output GaN FET. {00210669;v1} 7 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN bias circuit with first and second reference GaN FETs
reference bias circuit for wide band gap output FET with diode-connected FET stack
Materials described outside the worked examples.
Gallium Nitride
GaN
wide band gap semiconductor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a conventional bias circuit for a FET including a source resistor connected to the source electrode of the FET. [0016]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | ≥ 10 k | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,819,316Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a conventional bias circuit for a FET including a source resistor connected to the source electrode of the FET. [0016]
FIG. 2 shows a conventional bias circuit, which uses Schottky diodes to produce a bias voltage. [0017]
FIG. 3 illustrates a bias circuit according to an embodiment of the disclosure using two voltage sources. [0018]
FIG. 4 further illustrating radio frequency (RF) input/output (I/O) connections according to an embodiment of the disclosure. [0020]
FIG. 5 shows the bias circuit of
FIG. 6 shows a bias circuit for providing bias voltage to a GaN FET, the circuit including temperature compensation and an enable circuit according to an …
FIG. 7 is a schematic for a biasing circuit for providing bias voltage to a GaN FET according to an embodiment of the disclosure. {0018 6293;v 1 } 8 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic circuit for providing a bias voltage to an output Gallium Nitride (GaN) field effect transistor (FET) comprising: a first reference GaN FET having a gate, a source and a drain electrode; a positive voltage supply connected to the drain electrode of said first reference GaN FET; a first resistor device having a first terminal end coupled to the drain electrode of the first reference GaN FET, and a second terminal end coupled to the positive voltage supply; a negative voltage supply coupled to said source electrode of said first reference GaN FET via a second reference GaN FET; and an output node terminal coupled to the first terminal end of the first resistor and the drain electrode of said first reference GaN FET for providing the bias voltage to said output GaN FET, wherein said gate electrode of said first reference GaN FET is coupled to said negative voltage supply via a third resistor, and said source electrode of said first reference GaN FET is coupled to said negative voltage supply via said second reference GaN FET, thereby producinq a voltage level at said gate electrode that is less than a voltage level at said source electrode. {00210669;v1} 3 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed
The circuit of claim 1, wherein said second reference GaN FET exhibits a resistance to produce a target bias voltage at said output node terminal.
canceled
A reference bias circuit for providing a desired gate bias voltage to an output wide band gap field effect transistor (FET) comprising: a first reference FET having a gate electrode, a drain electrode coupled to a positive voltage supply, and a source electrode coupled to [[said]] a negative voltage supply; a first resistor coupled between said drain electrode of said first reference FET and said positive voltage supply; a second reference FET coupled between said source electrode of said first reference FET and [[a]]said negative voltage supply; an electrical node connecting said first resistor and said drain electrode of said first reference FET, and coupled to a gate electrode of said output wide band gap FET to provide a reference bias voltage thereto; and {00210669;v1} 4 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed a plurality of diode-connected FETs connected in series between said positive voltage supply and said gate electrode of said first reference FET, said plurality of diode-connected FETs configured to produce a temperature dependent bias voltage at said gate electrode of said first reference FET, to thereby modulate a current between said drain electrode and said source electrode of said first reference FET based on temperature.
The reference bias circuit of claim 6 further comprising: a level shifting resistor coupled between said electrical node (616) and said negative voltage supply, wherein a conductive path is defined from said positive voltage supply through said first resistor, said electrical node and said level shifting resistor to said negative voltage supply.
The reference bias circuit of claim 6, further comprising: an enable circuit comprising: an enable FET having a gate electrode coupled to said negative voltage supplyand supply and to said gate electrode of said output wide band gap FET, a {00210669;v1} 5 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed drain electrode coupled to said source electrode of said first reference FET, and a source electrode coupled to an enable pin; and a pair of series connected resistors connected between said gate electrode of said enable FET and said enable pin, wherein said source electrode of said enable FET is coupled to said enable pinat pin at a node between a first resistor and a second resistor of said pair of series connected resistors.
The reference bias circuit of claim 6, further comprising: a capacitor coupled between said gate electrode of said output wide band gap FET and a reference potential, wherein said capacitor is configured to filter out radio frequency (R F) signals applied at said gate of said output wide band gap FET and prevent said RF signals from reaching said electrical node coupled to said first reference FET.
The reference bias circuit of claim 6, wherein said output wide band gap FET comprises Gallium Nitride (GaN).
The reference bias circuit of claim 6, wherein said first reference FET comprises Gallium Nitride (GaN). {00210669;v1} 6 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed 15. The reference bias circuit of claim 6, wherein said second reference FET comprises Gallium Nitride (GaN).
canceled
The reference bias circuit of claim [[7]]6, wherein each of said plurality of diode-connected FETs comprises Gallium Nitride (GaN).
A circuit for providing bias to an output Gallium Nitride (GaN) field effect transistor (FET) comprising: a radio frequency (R F) input signal applied to a gate electrode of the output GaN FET; a positive voltage source connected to a drain electrode of the output GaN FET; a reference voltage connected to a source electrode of the output GaN FET; [[and]] a reference FET between the source electrode of the output GaN FET and the reference voltage, the reference FET having a drain electrode connected to the source electrode of the output GaN FET, a gate electrode connected to the source electrode of the output GaN FET via a resistor, and a source electrode connected to the reference voltage; and a negative voltage source connected to the gate electrode of the output GaN FET via a filtering resistor and a filtering inductor.
The circuit of claim 16, further comprising: an RF output generated between the positive voltage source and the drain electrode of the output GaN FET. {00210669;v1} 7 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN bias circuit with first and second reference GaN FETs
reference bias circuit for wide band gap output FET with diode-connected FET stack
Materials described outside the worked examples.
Gallium Nitride
GaN
wide band gap semiconductor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a conventional bias circuit for a FET including a source resistor connected to the source electrode of the FET. [0016]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | ≥ 10 k | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,819,316Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a conventional bias circuit for a FET including a source resistor connected to the source electrode of the FET. [0016]
FIG. 2 shows a conventional bias circuit, which uses Schottky diodes to produce a bias voltage. [0017]
FIG. 3 illustrates a bias circuit according to an embodiment of the disclosure using two voltage sources. [0018]
FIG. 4 further illustrating radio frequency (RF) input/output (I/O) connections according to an embodiment of the disclosure. [0020]
FIG. 5 shows the bias circuit of
FIG. 6 shows a bias circuit for providing bias voltage to a GaN FET, the circuit including temperature compensation and an enable circuit according to an …
FIG. 7 is a schematic for a biasing circuit for providing bias voltage to a GaN FET according to an embodiment of the disclosure. {0018 6293;v 1 } 8 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic circuit for providing a bias voltage to an output Gallium Nitride (GaN) field effect transistor (FET) comprising: a first reference GaN FET having a gate, a source and a drain electrode; a positive voltage supply connected to the drain electrode of said first reference GaN FET; a first resistor device having a first terminal end coupled to the drain electrode of the first reference GaN FET, and a second terminal end coupled to the positive voltage supply; a negative voltage supply coupled to said source electrode of said first reference GaN FET via a second reference GaN FET; and an output node terminal coupled to the first terminal end of the first resistor and the drain electrode of said first reference GaN FET for providing the bias voltage to said output GaN FET, wherein said gate electrode of said first reference GaN FET is coupled to said negative voltage supply via a third resistor, and said source electrode of said first reference GaN FET is coupled to said negative voltage supply via said second reference GaN FET, thereby producinq a voltage level at said gate electrode that is less than a voltage level at said source electrode. {00210669;v1} 3 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed
The circuit of claim 1, wherein said second reference GaN FET exhibits a resistance to produce a target bias voltage at said output node terminal.
canceled
A reference bias circuit for providing a desired gate bias voltage to an output wide band gap field effect transistor (FET) comprising: a first reference FET having a gate electrode, a drain electrode coupled to a positive voltage supply, and a source electrode coupled to [[said]] a negative voltage supply; a first resistor coupled between said drain electrode of said first reference FET and said positive voltage supply; a second reference FET coupled between said source electrode of said first reference FET and [[a]]said negative voltage supply; an electrical node connecting said first resistor and said drain electrode of said first reference FET, and coupled to a gate electrode of said output wide band gap FET to provide a reference bias voltage thereto; and {00210669;v1} 4 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed a plurality of diode-connected FETs connected in series between said positive voltage supply and said gate electrode of said first reference FET, said plurality of diode-connected FETs configured to produce a temperature dependent bias voltage at said gate electrode of said first reference FET, to thereby modulate a current between said drain electrode and said source electrode of said first reference FET based on temperature.
The reference bias circuit of claim 6 further comprising: a level shifting resistor coupled between said electrical node (616) and said negative voltage supply, wherein a conductive path is defined from said positive voltage supply through said first resistor, said electrical node and said level shifting resistor to said negative voltage supply.
The reference bias circuit of claim 6, further comprising: an enable circuit comprising: an enable FET having a gate electrode coupled to said negative voltage supplyand supply and to said gate electrode of said output wide band gap FET, a {00210669;v1} 5 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed drain electrode coupled to said source electrode of said first reference FET, and a source electrode coupled to an enable pin; and a pair of series connected resistors connected between said gate electrode of said enable FET and said enable pin, wherein said source electrode of said enable FET is coupled to said enable pinat pin at a node between a first resistor and a second resistor of said pair of series connected resistors.
The reference bias circuit of claim 6, further comprising: a capacitor coupled between said gate electrode of said output wide band gap FET and a reference potential, wherein said capacitor is configured to filter out radio frequency (R F) signals applied at said gate of said output wide band gap FET and prevent said RF signals from reaching said electrical node coupled to said first reference FET.
The reference bias circuit of claim 6, wherein said output wide band gap FET comprises Gallium Nitride (GaN).
The reference bias circuit of claim 6, wherein said first reference FET comprises Gallium Nitride (GaN). {00210669;v1} 6 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed 15. The reference bias circuit of claim 6, wherein said second reference FET comprises Gallium Nitride (GaN).
canceled
The reference bias circuit of claim [[7]]6, wherein each of said plurality of diode-connected FETs comprises Gallium Nitride (GaN).
A circuit for providing bias to an output Gallium Nitride (GaN) field effect transistor (FET) comprising: a radio frequency (R F) input signal applied to a gate electrode of the output GaN FET; a positive voltage source connected to a drain electrode of the output GaN FET; a reference voltage connected to a source electrode of the output GaN FET; [[and]] a reference FET between the source electrode of the output GaN FET and the reference voltage, the reference FET having a drain electrode connected to the source electrode of the output GaN FET, a gate electrode connected to the source electrode of the output GaN FET via a resistor, and a source electrode connected to the reference voltage; and a negative voltage source connected to the gate electrode of the output GaN FET via a filtering resistor and a filtering inductor.
The circuit of claim 16, further comprising: an RF output generated between the positive voltage source and the drain electrode of the output GaN FET. {00210669;v1} 7 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN bias circuit with first and second reference GaN FETs
reference bias circuit for wide band gap output FET with diode-connected FET stack
Materials described outside the worked examples.
Gallium Nitride
GaN
wide band gap semiconductor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a conventional bias circuit for a FET including a source resistor connected to the source electrode of the FET. [0016]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | ≥ 10 k | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,819,316Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a conventional bias circuit for a FET including a source resistor connected to the source electrode of the FET. [0016]
FIG. 2 shows a conventional bias circuit, which uses Schottky diodes to produce a bias voltage. [0017]
FIG. 3 illustrates a bias circuit according to an embodiment of the disclosure using two voltage sources. [0018]
FIG. 4 further illustrating radio frequency (RF) input/output (I/O) connections according to an embodiment of the disclosure. [0020]
FIG. 5 shows the bias circuit of
FIG. 6 shows a bias circuit for providing bias voltage to a GaN FET, the circuit including temperature compensation and an enable circuit according to an …
FIG. 7 is a schematic for a biasing circuit for providing bias voltage to a GaN FET according to an embodiment of the disclosure. {0018 6293;v 1 } 8 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic circuit for providing a bias voltage to an output Gallium Nitride (GaN) field effect transistor (FET) comprising: a first reference GaN FET having a gate, a source and a drain electrode; a positive voltage supply connected to the drain electrode of said first reference GaN FET; a first resistor device having a first terminal end coupled to the drain electrode of the first reference GaN FET, and a second terminal end coupled to the positive voltage supply; a negative voltage supply coupled to said source electrode of said first reference GaN FET via a second reference GaN FET; and an output node terminal coupled to the first terminal end of the first resistor and the drain electrode of said first reference GaN FET for providing the bias voltage to said output GaN FET, wherein said gate electrode of said first reference GaN FET is coupled to said negative voltage supply via a third resistor, and said source electrode of said first reference GaN FET is coupled to said negative voltage supply via said second reference GaN FET, thereby producinq a voltage level at said gate electrode that is less than a voltage level at said source electrode. {00210669;v1} 3 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed
The circuit of claim 1, wherein said second reference GaN FET exhibits a resistance to produce a target bias voltage at said output node terminal.
canceled
A reference bias circuit for providing a desired gate bias voltage to an output wide band gap field effect transistor (FET) comprising: a first reference FET having a gate electrode, a drain electrode coupled to a positive voltage supply, and a source electrode coupled to [[said]] a negative voltage supply; a first resistor coupled between said drain electrode of said first reference FET and said positive voltage supply; a second reference FET coupled between said source electrode of said first reference FET and [[a]]said negative voltage supply; an electrical node connecting said first resistor and said drain electrode of said first reference FET, and coupled to a gate electrode of said output wide band gap FET to provide a reference bias voltage thereto; and {00210669;v1} 4 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed a plurality of diode-connected FETs connected in series between said positive voltage supply and said gate electrode of said first reference FET, said plurality of diode-connected FETs configured to produce a temperature dependent bias voltage at said gate electrode of said first reference FET, to thereby modulate a current between said drain electrode and said source electrode of said first reference FET based on temperature.
The reference bias circuit of claim 6 further comprising: a level shifting resistor coupled between said electrical node (616) and said negative voltage supply, wherein a conductive path is defined from said positive voltage supply through said first resistor, said electrical node and said level shifting resistor to said negative voltage supply.
The reference bias circuit of claim 6, further comprising: an enable circuit comprising: an enable FET having a gate electrode coupled to said negative voltage supplyand supply and to said gate electrode of said output wide band gap FET, a {00210669;v1} 5 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed drain electrode coupled to said source electrode of said first reference FET, and a source electrode coupled to an enable pin; and a pair of series connected resistors connected between said gate electrode of said enable FET and said enable pin, wherein said source electrode of said enable FET is coupled to said enable pinat pin at a node between a first resistor and a second resistor of said pair of series connected resistors.
The reference bias circuit of claim 6, further comprising: a capacitor coupled between said gate electrode of said output wide band gap FET and a reference potential, wherein said capacitor is configured to filter out radio frequency (R F) signals applied at said gate of said output wide band gap FET and prevent said RF signals from reaching said electrical node coupled to said first reference FET.
The reference bias circuit of claim 6, wherein said output wide band gap FET comprises Gallium Nitride (GaN).
The reference bias circuit of claim 6, wherein said first reference FET comprises Gallium Nitride (GaN). {00210669;v1} 6 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed 15. The reference bias circuit of claim 6, wherein said second reference FET comprises Gallium Nitride (GaN).
canceled
The reference bias circuit of claim [[7]]6, wherein each of said plurality of diode-connected FETs comprises Gallium Nitride (GaN).
A circuit for providing bias to an output Gallium Nitride (GaN) field effect transistor (FET) comprising: a radio frequency (R F) input signal applied to a gate electrode of the output GaN FET; a positive voltage source connected to a drain electrode of the output GaN FET; a reference voltage connected to a source electrode of the output GaN FET; [[and]] a reference FET between the source electrode of the output GaN FET and the reference voltage, the reference FET having a drain electrode connected to the source electrode of the output GaN FET, a gate electrode connected to the source electrode of the output GaN FET via a resistor, and a source electrode connected to the reference voltage; and a negative voltage source connected to the gate electrode of the output GaN FET via a filtering resistor and a filtering inductor.
The circuit of claim 16, further comprising: an RF output generated between the positive voltage source and the drain electrode of the output GaN FET. {00210669;v1} 7 Docket No: GE-08047-US(RS) Serial No. 15/133,689 Response to Office Action mailed
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN bias circuit with first and second reference GaN FETs
reference bias circuit for wide band gap output FET with diode-connected FET stack
Materials described outside the worked examples.
Gallium Nitride
GaN
wide band gap semiconductor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows a conventional bias circuit for a FET including a source resistor connected to the source electrode of the FET. [0016]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | ≥ 10 k | — |
Related documents with shared materials, methods, properties, or citations.
GaN FET RF amplifier bias circuit with source reference FET
FIG. 3 illustrates a bias circuit according to an embodiment of the disclosure using two voltage sources. [0018]
FIG. 6 shows a bias circuit for providing bias voltage to a GaN FET, the circuit including temperature compensation and an enable circuit according to an …
FIG. 7 is a schematic for a biasing circuit for providing bias voltage to a GaN FET according to an embodiment of the disclosure. {0018 6293;v 1 } 8 …
GaN FET RF amplifier bias circuit with source reference FET
FIG. 3 illustrates a bias circuit according to an embodiment of the disclosure using two voltage sources. [0018]
FIG. 6 shows a bias circuit for providing bias voltage to a GaN FET, the circuit including temperature compensation and an enable circuit according to an …
FIG. 7 is a schematic for a biasing circuit for providing bias voltage to a GaN FET according to an embodiment of the disclosure. {0018 6293;v 1 } 8 …
GaN FET RF amplifier bias circuit with source reference FET
FIG. 3 illustrates a bias circuit according to an embodiment of the disclosure using two voltage sources. [0018]
FIG. 6 shows a bias circuit for providing bias voltage to a GaN FET, the circuit including temperature compensation and an enable circuit according to an …
FIG. 7 is a schematic for a biasing circuit for providing bias voltage to a GaN FET according to an embodiment of the disclosure. {0018 6293;v 1 } 8 …
GaN FET RF amplifier bias circuit with source reference FET
FIG. 3 illustrates a bias circuit according to an embodiment of the disclosure using two voltage sources. [0018]
FIG. 6 shows a bias circuit for providing bias voltage to a GaN FET, the circuit including temperature compensation and an enable circuit according to an …
FIG. 7 is a schematic for a biasing circuit for providing bias voltage to a GaN FET according to an embodiment of the disclosure. {0018 6293;v 1 } 8 …