Patent
US 11,973,134 B2SUPER JUNCTION GATED ALGAN GAN HEMT
Koon Hoo Teo, Nadim Chowdhury
Mitsubishi Electric Research Laboratories, Inc., Cambridge, MA (US)·Apr. 30, 2024·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,973,134 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structures and thicknesses of the transistor device, according to some …
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET), comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the FET; a gate, such that the gate is at a second horizontal plane of the FET, wherein the second horizontal plane is higher than the first horizontal plane; a first region under the first horizontal plane, such that the first region includes a first three Nitride (III-N) layer and a second III-N layer over the first III-N layer, wherein the first horizontal plane is arranged above a top surface of the second III-N layer; and a second region under the gate, such that the second region includes the first III-N layer, the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction per-pendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein the third III-N layer is doped P-type, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The field effect transistor of claim 1, wherein the first region includes a first portion of a base layer, 25 a first portion of a buffer layer over the first portion of the base layer, wherein the first three Nitride (III-N) layer is over the first portion of the buffer layer, and wherein the second region under the gate includes a second portion of the base layer, 30 a second portion of the buffer layer over the second portion of the base layer, wherein the first three Nitride (III-N) layer is over the second portion of the buffer layer.
The field effect transistor of claim 1, wherein the second III-N layer is an AlxInyGa₁-x-yN, such that a value of x and y is between 0 and 1 (0≤x≤1), (0≤y≤1), wherein the first III-N layer and the third III-N layer are Gallium Nitride (GaN).
The field effect transistor of claim 1, wherein the second III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the first III-N layer.
The field effect transistor of claim 1, wherein a vertical thickness of the first III-N layer is greater than a vertical thickness of the second III-N layer.
The field effect transistor of claim 1, wherein a vertical thickness of the first III-N layer is 10× times thicker than a vertical thickness of the second III-N layer, or the vertical thickness of the first III-N layer is 1000% percent thicker than the vertical thickness of the second III-N layer.
The field effect transistor of claim 1, wherein a gap distance between the source and the gate, and a gap distance between the gate and the drain, is one of symmetrical or non-symmetrical.
The field effect transistor of claim 1, wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the field effect transistor.
The field effect transistor of claim 1, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.
The field effect transistor of claim 1, wherein at an interface of the first and second III-N layers there is an accumulation of two-dimensional electron gas (2-DEG).
The field effect transistor of claim 1, wherein the first III-N layer has a first band gap and the second III-N layer has a second band gap, such that the second bandgap of the second III-N layer is larger than the first bandgap of the first III-N layer.
A transistor, comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the transistor; a gate, wherein the gate is at a second horizontal plane of the transistor, wherein the second horizontal plane is higher than the first horizontal plane; a first region under the first horizontal plane, such that the first region includes a first portion of a base substrate layer, a first portion of a buffer layer over the first portion of the base substrate layer, a first three Nitride (III-N) layer over the first portion of the buffer layer and a second III-N layer over the first III-N layer, wherein the second III-N layer has a first spontaneous polarization charge higher than a second spontaneous polarization charge of the first III-N layer, and wherein the first horizontal plane is arranged above a top surface of the second III-N layer; a second region under the gate, such that the second region includes a second portion of the base substrate layer, a second portion of the buffer layer over the second portion of the base substrate layer, the first III-N layer over the second portion of the buffer layer, and the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend ver-tically through the second III-N layer and into one or more portions of the first III-N layer along a direction perpendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selec-tive locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein the third III-N layer is doped P-type, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The transistor of claim 16, wherein the first III-N layer, second III-N layer and third III-N layer are grown using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD).
The transistor of claim 16, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.
A transistor, comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the transistor; a gate, such that the gate is at a second horizontal plane of the transistor, wherein the second horizontal plane is higher than the first horizontal plane, and wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the transistor; a first region under the first horizontal plane, such that the first region includes a first three Nitride (III-N) layer and a second III-N layer over the first III-N layer, wherein the first horizontal plane is arranged above a top surface of the second III-N layer; a second region under the gate, such that the second region includes the first III-N layer, the second III-N layer over the first III-N layer, and a third III-N layer B₂ directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction per-pendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The transistor of claim 19, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
Super Junction Gated AlGaN/GaN HEMT (FET, claim 1)
Super Junction Gated AlGaN/GaN Transistor (claim 16)
Materials described outside the worked examples.
first III-N layer (GaN channel layer)
GaN
second III-N layer (AlxInyGa₁-x-yN barrier layer)
AlxInyGa₁-x-yN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structures and thicknesses of the transistor device, according to some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage range for Trigate (FinFET) from experimentation | 0.2–1.5 V | — |
Threshold voltage target for super junction gated trigate device (>3 V) | ≥ 3 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,973,134 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structures and thicknesses of the transistor device, according to some …
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET), comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the FET; a gate, such that the gate is at a second horizontal plane of the FET, wherein the second horizontal plane is higher than the first horizontal plane; a first region under the first horizontal plane, such that the first region includes a first three Nitride (III-N) layer and a second III-N layer over the first III-N layer, wherein the first horizontal plane is arranged above a top surface of the second III-N layer; and a second region under the gate, such that the second region includes the first III-N layer, the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction per-pendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein the third III-N layer is doped P-type, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The field effect transistor of claim 1, wherein the first region includes a first portion of a base layer, 25 a first portion of a buffer layer over the first portion of the base layer, wherein the first three Nitride (III-N) layer is over the first portion of the buffer layer, and wherein the second region under the gate includes a second portion of the base layer, 30 a second portion of the buffer layer over the second portion of the base layer, wherein the first three Nitride (III-N) layer is over the second portion of the buffer layer.
The field effect transistor of claim 1, wherein the second III-N layer is an AlxInyGa₁-x-yN, such that a value of x and y is between 0 and 1 (0≤x≤1), (0≤y≤1), wherein the first III-N layer and the third III-N layer are Gallium Nitride (GaN).
The field effect transistor of claim 1, wherein the second III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the first III-N layer.
The field effect transistor of claim 1, wherein a vertical thickness of the first III-N layer is greater than a vertical thickness of the second III-N layer.
The field effect transistor of claim 1, wherein a vertical thickness of the first III-N layer is 10× times thicker than a vertical thickness of the second III-N layer, or the vertical thickness of the first III-N layer is 1000% percent thicker than the vertical thickness of the second III-N layer.
The field effect transistor of claim 1, wherein a gap distance between the source and the gate, and a gap distance between the gate and the drain, is one of symmetrical or non-symmetrical.
The field effect transistor of claim 1, wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the field effect transistor.
The field effect transistor of claim 1, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.
The field effect transistor of claim 1, wherein at an interface of the first and second III-N layers there is an accumulation of two-dimensional electron gas (2-DEG).
The field effect transistor of claim 1, wherein the first III-N layer has a first band gap and the second III-N layer has a second band gap, such that the second bandgap of the second III-N layer is larger than the first bandgap of the first III-N layer.
A transistor, comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the transistor; a gate, wherein the gate is at a second horizontal plane of the transistor, wherein the second horizontal plane is higher than the first horizontal plane; a first region under the first horizontal plane, such that the first region includes a first portion of a base substrate layer, a first portion of a buffer layer over the first portion of the base substrate layer, a first three Nitride (III-N) layer over the first portion of the buffer layer and a second III-N layer over the first III-N layer, wherein the second III-N layer has a first spontaneous polarization charge higher than a second spontaneous polarization charge of the first III-N layer, and wherein the first horizontal plane is arranged above a top surface of the second III-N layer; a second region under the gate, such that the second region includes a second portion of the base substrate layer, a second portion of the buffer layer over the second portion of the base substrate layer, the first III-N layer over the second portion of the buffer layer, and the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend ver-tically through the second III-N layer and into one or more portions of the first III-N layer along a direction perpendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selec-tive locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein the third III-N layer is doped P-type, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The transistor of claim 16, wherein the first III-N layer, second III-N layer and third III-N layer are grown using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD).
The transistor of claim 16, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.
A transistor, comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the transistor; a gate, such that the gate is at a second horizontal plane of the transistor, wherein the second horizontal plane is higher than the first horizontal plane, and wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the transistor; a first region under the first horizontal plane, such that the first region includes a first three Nitride (III-N) layer and a second III-N layer over the first III-N layer, wherein the first horizontal plane is arranged above a top surface of the second III-N layer; a second region under the gate, such that the second region includes the first III-N layer, the second III-N layer over the first III-N layer, and a third III-N layer B₂ directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction per-pendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The transistor of claim 19, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
Super Junction Gated AlGaN/GaN HEMT (FET, claim 1)
Super Junction Gated AlGaN/GaN Transistor (claim 16)
Materials described outside the worked examples.
first III-N layer (GaN channel layer)
GaN
second III-N layer (AlxInyGa₁-x-yN barrier layer)
AlxInyGa₁-x-yN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structures and thicknesses of the transistor device, according to some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage range for Trigate (FinFET) from experimentation | 0.2–1.5 V | — |
Threshold voltage target for super junction gated trigate device (>3 V) | ≥ 3 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,973,134 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structures and thicknesses of the transistor device, according to some …
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET), comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the FET; a gate, such that the gate is at a second horizontal plane of the FET, wherein the second horizontal plane is higher than the first horizontal plane; a first region under the first horizontal plane, such that the first region includes a first three Nitride (III-N) layer and a second III-N layer over the first III-N layer, wherein the first horizontal plane is arranged above a top surface of the second III-N layer; and a second region under the gate, such that the second region includes the first III-N layer, the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction per-pendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein the third III-N layer is doped P-type, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The field effect transistor of claim 1, wherein the first region includes a first portion of a base layer, 25 a first portion of a buffer layer over the first portion of the base layer, wherein the first three Nitride (III-N) layer is over the first portion of the buffer layer, and wherein the second region under the gate includes a second portion of the base layer, 30 a second portion of the buffer layer over the second portion of the base layer, wherein the first three Nitride (III-N) layer is over the second portion of the buffer layer.
The field effect transistor of claim 1, wherein the second III-N layer is an AlxInyGa₁-x-yN, such that a value of x and y is between 0 and 1 (0≤x≤1), (0≤y≤1), wherein the first III-N layer and the third III-N layer are Gallium Nitride (GaN).
The field effect transistor of claim 1, wherein the second III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the first III-N layer.
The field effect transistor of claim 1, wherein a vertical thickness of the first III-N layer is greater than a vertical thickness of the second III-N layer.
The field effect transistor of claim 1, wherein a vertical thickness of the first III-N layer is 10× times thicker than a vertical thickness of the second III-N layer, or the vertical thickness of the first III-N layer is 1000% percent thicker than the vertical thickness of the second III-N layer.
The field effect transistor of claim 1, wherein a gap distance between the source and the gate, and a gap distance between the gate and the drain, is one of symmetrical or non-symmetrical.
The field effect transistor of claim 1, wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the field effect transistor.
The field effect transistor of claim 1, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.
The field effect transistor of claim 1, wherein at an interface of the first and second III-N layers there is an accumulation of two-dimensional electron gas (2-DEG).
The field effect transistor of claim 1, wherein the first III-N layer has a first band gap and the second III-N layer has a second band gap, such that the second bandgap of the second III-N layer is larger than the first bandgap of the first III-N layer.
A transistor, comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the transistor; a gate, wherein the gate is at a second horizontal plane of the transistor, wherein the second horizontal plane is higher than the first horizontal plane; a first region under the first horizontal plane, such that the first region includes a first portion of a base substrate layer, a first portion of a buffer layer over the first portion of the base substrate layer, a first three Nitride (III-N) layer over the first portion of the buffer layer and a second III-N layer over the first III-N layer, wherein the second III-N layer has a first spontaneous polarization charge higher than a second spontaneous polarization charge of the first III-N layer, and wherein the first horizontal plane is arranged above a top surface of the second III-N layer; a second region under the gate, such that the second region includes a second portion of the base substrate layer, a second portion of the buffer layer over the second portion of the base substrate layer, the first III-N layer over the second portion of the buffer layer, and the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend ver-tically through the second III-N layer and into one or more portions of the first III-N layer along a direction perpendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selec-tive locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein the third III-N layer is doped P-type, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The transistor of claim 16, wherein the first III-N layer, second III-N layer and third III-N layer are grown using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD).
The transistor of claim 16, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.
A transistor, comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the transistor; a gate, such that the gate is at a second horizontal plane of the transistor, wherein the second horizontal plane is higher than the first horizontal plane, and wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the transistor; a first region under the first horizontal plane, such that the first region includes a first three Nitride (III-N) layer and a second III-N layer over the first III-N layer, wherein the first horizontal plane is arranged above a top surface of the second III-N layer; a second region under the gate, such that the second region includes the first III-N layer, the second III-N layer over the first III-N layer, and a third III-N layer B₂ directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction per-pendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The transistor of claim 19, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
Super Junction Gated AlGaN/GaN HEMT (FET, claim 1)
Super Junction Gated AlGaN/GaN Transistor (claim 16)
Materials described outside the worked examples.
first III-N layer (GaN channel layer)
GaN
second III-N layer (AlxInyGa₁-x-yN barrier layer)
AlxInyGa₁-x-yN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structures and thicknesses of the transistor device, according to some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage range for Trigate (FinFET) from experimentation | 0.2–1.5 V | — |
Threshold voltage target for super junction gated trigate device (>3 V) | ≥ 3 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,973,134 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structures and thicknesses of the transistor device, according to some …
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET), comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the FET; a gate, such that the gate is at a second horizontal plane of the FET, wherein the second horizontal plane is higher than the first horizontal plane; a first region under the first horizontal plane, such that the first region includes a first three Nitride (III-N) layer and a second III-N layer over the first III-N layer, wherein the first horizontal plane is arranged above a top surface of the second III-N layer; and a second region under the gate, such that the second region includes the first III-N layer, the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction per-pendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein the third III-N layer is doped P-type, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The field effect transistor of claim 1, wherein the first region includes a first portion of a base layer, 25 a first portion of a buffer layer over the first portion of the base layer, wherein the first three Nitride (III-N) layer is over the first portion of the buffer layer, and wherein the second region under the gate includes a second portion of the base layer, 30 a second portion of the buffer layer over the second portion of the base layer, wherein the first three Nitride (III-N) layer is over the second portion of the buffer layer.
The field effect transistor of claim 1, wherein the second III-N layer is an AlxInyGa₁-x-yN, such that a value of x and y is between 0 and 1 (0≤x≤1), (0≤y≤1), wherein the first III-N layer and the third III-N layer are Gallium Nitride (GaN).
The field effect transistor of claim 1, wherein the second III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the first III-N layer.
The field effect transistor of claim 1, wherein a vertical thickness of the first III-N layer is greater than a vertical thickness of the second III-N layer.
The field effect transistor of claim 1, wherein a vertical thickness of the first III-N layer is 10× times thicker than a vertical thickness of the second III-N layer, or the vertical thickness of the first III-N layer is 1000% percent thicker than the vertical thickness of the second III-N layer.
The field effect transistor of claim 1, wherein a gap distance between the source and the gate, and a gap distance between the gate and the drain, is one of symmetrical or non-symmetrical.
The field effect transistor of claim 1, wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the field effect transistor.
The field effect transistor of claim 1, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.
The field effect transistor of claim 1, wherein at an interface of the first and second III-N layers there is an accumulation of two-dimensional electron gas (2-DEG).
The field effect transistor of claim 1, wherein the first III-N layer has a first band gap and the second III-N layer has a second band gap, such that the second bandgap of the second III-N layer is larger than the first bandgap of the first III-N layer.
A transistor, comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the transistor; a gate, wherein the gate is at a second horizontal plane of the transistor, wherein the second horizontal plane is higher than the first horizontal plane; a first region under the first horizontal plane, such that the first region includes a first portion of a base substrate layer, a first portion of a buffer layer over the first portion of the base substrate layer, a first three Nitride (III-N) layer over the first portion of the buffer layer and a second III-N layer over the first III-N layer, wherein the second III-N layer has a first spontaneous polarization charge higher than a second spontaneous polarization charge of the first III-N layer, and wherein the first horizontal plane is arranged above a top surface of the second III-N layer; a second region under the gate, such that the second region includes a second portion of the base substrate layer, a second portion of the buffer layer over the second portion of the base substrate layer, the first III-N layer over the second portion of the buffer layer, and the second III-N layer over the first III-N layer, and a third III-N layer directly on the second III-N layer, wherein selective locations of the third III-N layer extend ver-tically through the second III-N layer and into one or more portions of the first III-N layer along a direction perpendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selec-tive locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein the third III-N layer is doped P-type, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The transistor of claim 16, wherein the first III-N layer, second III-N layer and third III-N layer are grown using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD).
The transistor of claim 16, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length.
A transistor, comprising: a source and a drain, such that a bottom surface of the source and a bottom surface of the drain are at a first horizontal plane of the transistor; a gate, such that the gate is at a second horizontal plane of the transistor, wherein the second horizontal plane is higher than the first horizontal plane, and wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the transistor; a first region under the first horizontal plane, such that the first region includes a first three Nitride (III-N) layer and a second III-N layer over the first III-N layer, wherein the first horizontal plane is arranged above a top surface of the second III-N layer; a second region under the gate, such that the second region includes the first III-N layer, the second III-N layer over the first III-N layer, and a third III-N layer B₂ directly on the second III-N layer, wherein selective locations of the third III-N layer extend vertically through the second III-N layer and into one or more portions of the first III-N layer along a direction per-pendicular to the first horizontal plane and the second horizontal plane, wherein portions of the selective locations of the third III-N layer that extend into the one or more portions of the first III-N layer are implanted with Magnesium, wherein a top surface of the third III-N layer extends above a top surface of the source and a top surface of the drain, and wherein the third III-N layer extends continuously and horizontally under the gate in a third horizontal plane parallel to the first horizontal plane and the second horizontal plane without intersecting the source and the drain.
The transistor of claim 19, wherein the third III-N layer extending through the second III-N layer into the one or more portions of the first III-N layer at the selective locations defines a plurality of profiles such that each of the plurality of profiles has a vertical profile length and a profile width, and wherein the plurality of profiles include one or a combination of a variable profile width or a variable vertical profile length. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
Super Junction Gated AlGaN/GaN HEMT (FET, claim 1)
Super Junction Gated AlGaN/GaN Transistor (claim 16)
Materials described outside the worked examples.
first III-N layer (GaN channel layer)
GaN
second III-N layer (AlxInyGa₁-x-yN barrier layer)
AlxInyGa₁-x-yN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structures and thicknesses of the transistor device, according to some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage range for Trigate (FinFET) from experimentation | 0.2–1.5 V | — |
Threshold voltage target for super junction gated trigate device (>3 V) | ≥ 3 V |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Super Junction Gated AlGaN/GaN Transistor (claim 19)
Magnesium dopant
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base substrate layer
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FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
| — |
Thickness | 5–30 nm | — |
Cited non-patent literature · 2
Super Junction Gated AlGaN/GaN Transistor (claim 19)
Magnesium dopant
Mg
base substrate layer
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FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
| — |
Thickness | 5–30 nm | — |
Cited non-patent literature · 2
Super Junction Gated AlGaN/GaN Transistor (claim 19)
Magnesium dopant
Mg
base substrate layer
buffer layer
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
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Thickness | 5–30 nm | — |
Cited non-patent literature · 2
Super Junction Gated AlGaN/GaN Transistor (claim 19)
Magnesium dopant
Mg
base substrate layer
buffer layer
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
| — |
Thickness | 5–30 nm | — |
Cited non-patent literature · 2