Patent
US 10,038,060GRAPHENE NMOS TRANSISTOR USING NITROGEN DIOXIDE CHEMICAL ADSORPTION
Yong Ju LEE
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
Patent
US 10,038,060Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an exemplary graphene structure, according to various aspects. [0013]
FIG. 2 B -2C illustrate performance measurements associated with the top-gated field- effect transistor shown in
FIG. 3 illustrates an exemplary transistor structure that employs p-type doping in an attempt to capture electrons in a graphene channel, according to various …
FIG. 4 illustrates an exemplary graphene n-type metal-oxide-semiconductor (NMOS) transistor formed using nitrogen dioxide (N O 2) chemical adsorption in a …
FIG. 5 through
FIG. 6, the photoresist 108 is not formed over the graphene layer 106 in the channel region such that NO 2 can be selectively adsorbed on the graphene layer …
FIG. 7. At that point, as shown in
FIG. 8, the high-k dielectric 122 and the gate metal 124 may be deposited over the photoresist 120 in the source region and the channel region and over the NO₂ …
FIG. 9, a gate stack can then be formed, wherein the gate stack may comprise a high-k dielectric 122 (e.g., hafnium silicate, zirconium silicate, hafnium …
FIG. 11, a silicon nitride (SiN) layer 130 may then be deposited on the entire surface and an etching process may then QC₁₅₃₁ 17 Qualcomm Ref. No. 153117 10 be …
FIG. 12. For example, in various embodiments, a dry-etching (or plasma-etching) process can be used, whereby a source gas rich in chlorine or fluorine (e.g. …
FIG. 13, a photoresist 140 may be developed in the channel region to cover the SiN spacers 132 and the gate metal 124 used in the gate stack, thereby exposing …
FIG. 15, a silicon dioxide (SiO₂) layer 150 may then be deposited over the interface metal 142 in the source region and the drain region and the gate metal 124 …
FIG. 16 illustrate an exemplary process flow to form a graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0017]
FIG. 17 and FI G. 18 illustrate exemplary effects from using N O 2 chemical adsorption to form the graphene NMOS transistor, according to various aspects. [0018]
FIG. 19 illustrates an exemplary method to form the graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0019]
FIG. 20 illustrates an exemplary processor-based system that may comprise one or more integrated circuits that implement the graphene NMOS transistor described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An n-type metal-oxide-semiconductor (NMOS) transistor, comprising: a substrate having a graphene layer formed on a topmost surface; a source terminal fo rm ed on the graphene layer in a source region; a drain terminal formed on the graphene layer in a drain region; a gate stack fo rm ed on the graphene layer within a channel region disposed between the source te rm inal and the drain terminal, wherein the channel region comprises a spacer region and the gate stack comprises: a high-k dielectric layer; an adsorbed nitrogen dioxide (N O 2) layer formed on an adsorbent surface of the graphene layer in the channel region, the absorbed N O 2 layer in contact with the source terminal and the drain terminal and fo rm ing an adsorbate film between the high-k dielectric layer and the adsorbent surface of the graphene layer; and 2 a gate metal formed over the high-k dielectric layer. Currently amended
The NMOS transistor recited in claim 1, wherein the adsorbed N O 2 layer is further disposed between the spacer region and the graphene layer. Original
The NMOS transistor recited in claim 1, wherein the adsorbed N O 2 layer is configured to attract electrons from the graphene layer within the channel region to make the graphene layer electron-deficient in the channel region. Original
The NMOS transistor recited in claim 1, further comprising: a first spacer formed in the spacer region adjacent to a first sidewall of the gate stack; and a second spacer formed in the spacer region adjacent to a second sidewall of the gate stack, wherein the adsorbed N O 2 layer is disposed under the first spacer and the second spacer to reduce potential short-channel effects related to drain-induced barrier lowering (DIBL). Original
The NMOS transistor recited in claim 1, wherein the topmost surface of the substrate is formed from silicon carbide (Si C). Original
The NMOS transistor recited in claim 1, further comprising: interlayer dielectrics formed over the channel region, the source terminal in the source region, and the drain terminal in the drain region; and interconnects formed through the interlayer dielectrics to connect the source terminal to a source electrode, the gate metal to a gate electrode, and the drain terminal to a drain electrode. Original
A method for forming an n-type metal-oxide-semiconductor (NMOS) transistor, comprising: forming a graphene layer on a substrate surface; forming an adsorbed nitrogen dioxide layer on a portion of the graphene layer disposed in a channel region; forming a gate stack on a portion of the adsorbed nitrogen dioxide layer; forming spacer structures on the adsorbed nitrogen dioxide layer in spacer regions disposed within the channel region and adjacent to the gate stack; and forming a source stack and a drain stack on lateral portions of the graphene layer disposed adjacent to the adsorbed nitrogen dioxide layer. Withdrawn
The method recited in claim 11, wherein the substrate surface comprises a silicon (Si)- terminated face having the graphene layer epitaxially formed thereon. Withdrawn
The method recited in claim 11, wherein forming the adsorbed nitrogen dioxide layer comprises: developing a photoresist on the lateral portions of the graphene layer and leaving the portion of the graphene layer disposed in the channel region exposed; chemically adsorbing the nitrogen dioxide on the exposed portion of the graphene layer disposed in the channel region; and removing the photoresist developed on the lateral portions of the graphene layer. Withdrawn
The method recited in claim 11, wherein forming the gate stack comprises: developing a photoresist on the lateral portions of the graphene layer and the spacer regions disposed within the channel region and leaving a portion of the adsorbed nitrogen dioxide layer exposed; depositing a high-k dielectric on the photoresist and the exposed portion of the adsorbed nitrogen dioxide layer; depositing a gate metal on the high-k dielectric deposited on the photoresist and the exposed portion of the adsorbed nitrogen dioxide layer; and performing a lift-off process to remove the photoresist and the high-k dielectric and the gate metal deposited thereon. Withdrawn
The method recited in claim 11, wherein forming the spacer structures comp ri ses: depositing a spacer material on the lateral portions of the graphene layer, a portion of the adsorbed nitrogen dioxide layer disposed in the spacer regions, and the gate stack fo rm ed on the portion of the adsorbed nitrogen dioxide layer; and performing an etching process to remove the spacer material except the spacer material deposited on the portion of the adsorbed nitrogen dioxide layer disposed in the spacer regions. Withdrawn
A field-effect transistor, comprising: a source terminal, a drain terminal, and a gate; a graphene channel having an adsorbent surface with a nitrogen dioxide adsorbate film formed thereon, the nitrogen dioxide adsorbate film in contact with the source terminal and the drain terminal and forming an adsorbate film disposed under the gate between a high-k dielectric layer and the adsorbent surface of the graphene channel; and means for flowing electrons through the graphene channel, wherein: the nitrogen dioxide adsorbate film is configured to attract the electrons flowed through the graphene channel such that the field-effect transistor turns off at a gate voltage (V g) equal to zero, and the graphene channel has a doping concentration (N D) equal to zero such that the electrons flowed through the graphene channel have a maximum possible mobility (p). Currently amended
The field-effect transistor recited in claim 17, further comprising: a first spacer structure located in a first spacer region above the nitrogen dioxide adsorbate film and between the source terminal and the gate; and a second spacer structure located in a second spacer region above the nitrogen dioxide adsorbate film and between the drain terminal and the gate. Currently amended
A method for operating a field-effect transistor comprising a source, a drain, a gate, and a graphene channel having an adsorbent surface with a nitrogen dioxide adsorbate film under the gate and on the adsorbent surface, the method comprising: flowing electrons from the source to the drain and through the graphene channel, the graphene channel having a doping concentration (N D) equal to zero such that the flowed electrons have a maximum possible mobility (p); and applying a gate voltage (V g) to the field-effect transistor, wherein the nitrogen dioxide adsorbate film located under the gate attracts the electrons flowed through the graphene channel such that the field-effect transistor turns off at V g equals zero. Withdrawn
The method recited in claim 19, wherein the field-effect transistor further comprises a first spacer structure located in a first spacer region above the nitrogen dioxide adsorbate film and between the source and the gate and a second spacer structure located in a second spacer region above the nitrogen dioxide adsorbate film and between the drain and the gate. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
NMOS transistor with graphene channel and NO₂ adsorbate
field-effect transistor with graphene channel and NO₂ adsorbate film
Materials described outside the worked examples.
graphene
C
nitrogen dioxide adsorbate
NO₂
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 B -2C illustrate performance measurements associated with the top-gated field- effect transistor shown in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 15000 cm2/Vs | C |
Fet Mobility | 1330 cm2/Vs |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,038,060Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an exemplary graphene structure, according to various aspects. [0013]
FIG. 2 B -2C illustrate performance measurements associated with the top-gated field- effect transistor shown in
FIG. 3 illustrates an exemplary transistor structure that employs p-type doping in an attempt to capture electrons in a graphene channel, according to various …
FIG. 4 illustrates an exemplary graphene n-type metal-oxide-semiconductor (NMOS) transistor formed using nitrogen dioxide (N O 2) chemical adsorption in a …
FIG. 5 through
FIG. 6, the photoresist 108 is not formed over the graphene layer 106 in the channel region such that NO 2 can be selectively adsorbed on the graphene layer …
FIG. 7. At that point, as shown in
FIG. 8, the high-k dielectric 122 and the gate metal 124 may be deposited over the photoresist 120 in the source region and the channel region and over the NO₂ …
FIG. 9, a gate stack can then be formed, wherein the gate stack may comprise a high-k dielectric 122 (e.g., hafnium silicate, zirconium silicate, hafnium …
FIG. 11, a silicon nitride (SiN) layer 130 may then be deposited on the entire surface and an etching process may then QC₁₅₃₁ 17 Qualcomm Ref. No. 153117 10 be …
FIG. 12. For example, in various embodiments, a dry-etching (or plasma-etching) process can be used, whereby a source gas rich in chlorine or fluorine (e.g. …
FIG. 13, a photoresist 140 may be developed in the channel region to cover the SiN spacers 132 and the gate metal 124 used in the gate stack, thereby exposing …
FIG. 15, a silicon dioxide (SiO₂) layer 150 may then be deposited over the interface metal 142 in the source region and the drain region and the gate metal 124 …
FIG. 16 illustrate an exemplary process flow to form a graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0017]
FIG. 17 and FI G. 18 illustrate exemplary effects from using N O 2 chemical adsorption to form the graphene NMOS transistor, according to various aspects. [0018]
FIG. 19 illustrates an exemplary method to form the graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0019]
FIG. 20 illustrates an exemplary processor-based system that may comprise one or more integrated circuits that implement the graphene NMOS transistor described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An n-type metal-oxide-semiconductor (NMOS) transistor, comprising: a substrate having a graphene layer formed on a topmost surface; a source terminal fo rm ed on the graphene layer in a source region; a drain terminal formed on the graphene layer in a drain region; a gate stack fo rm ed on the graphene layer within a channel region disposed between the source te rm inal and the drain terminal, wherein the channel region comprises a spacer region and the gate stack comprises: a high-k dielectric layer; an adsorbed nitrogen dioxide (N O 2) layer formed on an adsorbent surface of the graphene layer in the channel region, the absorbed N O 2 layer in contact with the source terminal and the drain terminal and fo rm ing an adsorbate film between the high-k dielectric layer and the adsorbent surface of the graphene layer; and 2 a gate metal formed over the high-k dielectric layer. Currently amended
The NMOS transistor recited in claim 1, wherein the adsorbed N O 2 layer is further disposed between the spacer region and the graphene layer. Original
The NMOS transistor recited in claim 1, wherein the adsorbed N O 2 layer is configured to attract electrons from the graphene layer within the channel region to make the graphene layer electron-deficient in the channel region. Original
The NMOS transistor recited in claim 1, further comprising: a first spacer formed in the spacer region adjacent to a first sidewall of the gate stack; and a second spacer formed in the spacer region adjacent to a second sidewall of the gate stack, wherein the adsorbed N O 2 layer is disposed under the first spacer and the second spacer to reduce potential short-channel effects related to drain-induced barrier lowering (DIBL). Original
The NMOS transistor recited in claim 1, wherein the topmost surface of the substrate is formed from silicon carbide (Si C). Original
The NMOS transistor recited in claim 1, further comprising: interlayer dielectrics formed over the channel region, the source terminal in the source region, and the drain terminal in the drain region; and interconnects formed through the interlayer dielectrics to connect the source terminal to a source electrode, the gate metal to a gate electrode, and the drain terminal to a drain electrode. Original
A method for forming an n-type metal-oxide-semiconductor (NMOS) transistor, comprising: forming a graphene layer on a substrate surface; forming an adsorbed nitrogen dioxide layer on a portion of the graphene layer disposed in a channel region; forming a gate stack on a portion of the adsorbed nitrogen dioxide layer; forming spacer structures on the adsorbed nitrogen dioxide layer in spacer regions disposed within the channel region and adjacent to the gate stack; and forming a source stack and a drain stack on lateral portions of the graphene layer disposed adjacent to the adsorbed nitrogen dioxide layer. Withdrawn
The method recited in claim 11, wherein the substrate surface comprises a silicon (Si)- terminated face having the graphene layer epitaxially formed thereon. Withdrawn
The method recited in claim 11, wherein forming the adsorbed nitrogen dioxide layer comprises: developing a photoresist on the lateral portions of the graphene layer and leaving the portion of the graphene layer disposed in the channel region exposed; chemically adsorbing the nitrogen dioxide on the exposed portion of the graphene layer disposed in the channel region; and removing the photoresist developed on the lateral portions of the graphene layer. Withdrawn
The method recited in claim 11, wherein forming the gate stack comprises: developing a photoresist on the lateral portions of the graphene layer and the spacer regions disposed within the channel region and leaving a portion of the adsorbed nitrogen dioxide layer exposed; depositing a high-k dielectric on the photoresist and the exposed portion of the adsorbed nitrogen dioxide layer; depositing a gate metal on the high-k dielectric deposited on the photoresist and the exposed portion of the adsorbed nitrogen dioxide layer; and performing a lift-off process to remove the photoresist and the high-k dielectric and the gate metal deposited thereon. Withdrawn
The method recited in claim 11, wherein forming the spacer structures comp ri ses: depositing a spacer material on the lateral portions of the graphene layer, a portion of the adsorbed nitrogen dioxide layer disposed in the spacer regions, and the gate stack fo rm ed on the portion of the adsorbed nitrogen dioxide layer; and performing an etching process to remove the spacer material except the spacer material deposited on the portion of the adsorbed nitrogen dioxide layer disposed in the spacer regions. Withdrawn
A field-effect transistor, comprising: a source terminal, a drain terminal, and a gate; a graphene channel having an adsorbent surface with a nitrogen dioxide adsorbate film formed thereon, the nitrogen dioxide adsorbate film in contact with the source terminal and the drain terminal and forming an adsorbate film disposed under the gate between a high-k dielectric layer and the adsorbent surface of the graphene channel; and means for flowing electrons through the graphene channel, wherein: the nitrogen dioxide adsorbate film is configured to attract the electrons flowed through the graphene channel such that the field-effect transistor turns off at a gate voltage (V g) equal to zero, and the graphene channel has a doping concentration (N D) equal to zero such that the electrons flowed through the graphene channel have a maximum possible mobility (p). Currently amended
The field-effect transistor recited in claim 17, further comprising: a first spacer structure located in a first spacer region above the nitrogen dioxide adsorbate film and between the source terminal and the gate; and a second spacer structure located in a second spacer region above the nitrogen dioxide adsorbate film and between the drain terminal and the gate. Currently amended
A method for operating a field-effect transistor comprising a source, a drain, a gate, and a graphene channel having an adsorbent surface with a nitrogen dioxide adsorbate film under the gate and on the adsorbent surface, the method comprising: flowing electrons from the source to the drain and through the graphene channel, the graphene channel having a doping concentration (N D) equal to zero such that the flowed electrons have a maximum possible mobility (p); and applying a gate voltage (V g) to the field-effect transistor, wherein the nitrogen dioxide adsorbate film located under the gate attracts the electrons flowed through the graphene channel such that the field-effect transistor turns off at V g equals zero. Withdrawn
The method recited in claim 19, wherein the field-effect transistor further comprises a first spacer structure located in a first spacer region above the nitrogen dioxide adsorbate film and between the source and the gate and a second spacer structure located in a second spacer region above the nitrogen dioxide adsorbate film and between the drain and the gate. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
NMOS transistor with graphene channel and NO₂ adsorbate
field-effect transistor with graphene channel and NO₂ adsorbate film
Materials described outside the worked examples.
graphene
C
nitrogen dioxide adsorbate
NO₂
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 B -2C illustrate performance measurements associated with the top-gated field- effect transistor shown in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 15000 cm2/Vs | C |
Fet Mobility | 1330 cm2/Vs |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,038,060Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an exemplary graphene structure, according to various aspects. [0013]
FIG. 2 B -2C illustrate performance measurements associated with the top-gated field- effect transistor shown in
FIG. 3 illustrates an exemplary transistor structure that employs p-type doping in an attempt to capture electrons in a graphene channel, according to various …
FIG. 4 illustrates an exemplary graphene n-type metal-oxide-semiconductor (NMOS) transistor formed using nitrogen dioxide (N O 2) chemical adsorption in a …
FIG. 5 through
FIG. 6, the photoresist 108 is not formed over the graphene layer 106 in the channel region such that NO 2 can be selectively adsorbed on the graphene layer …
FIG. 7. At that point, as shown in
FIG. 8, the high-k dielectric 122 and the gate metal 124 may be deposited over the photoresist 120 in the source region and the channel region and over the NO₂ …
FIG. 9, a gate stack can then be formed, wherein the gate stack may comprise a high-k dielectric 122 (e.g., hafnium silicate, zirconium silicate, hafnium …
FIG. 11, a silicon nitride (SiN) layer 130 may then be deposited on the entire surface and an etching process may then QC₁₅₃₁ 17 Qualcomm Ref. No. 153117 10 be …
FIG. 12. For example, in various embodiments, a dry-etching (or plasma-etching) process can be used, whereby a source gas rich in chlorine or fluorine (e.g. …
FIG. 13, a photoresist 140 may be developed in the channel region to cover the SiN spacers 132 and the gate metal 124 used in the gate stack, thereby exposing …
FIG. 15, a silicon dioxide (SiO₂) layer 150 may then be deposited over the interface metal 142 in the source region and the drain region and the gate metal 124 …
FIG. 16 illustrate an exemplary process flow to form a graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0017]
FIG. 17 and FI G. 18 illustrate exemplary effects from using N O 2 chemical adsorption to form the graphene NMOS transistor, according to various aspects. [0018]
FIG. 19 illustrates an exemplary method to form the graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0019]
FIG. 20 illustrates an exemplary processor-based system that may comprise one or more integrated circuits that implement the graphene NMOS transistor described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An n-type metal-oxide-semiconductor (NMOS) transistor, comprising: a substrate having a graphene layer formed on a topmost surface; a source terminal fo rm ed on the graphene layer in a source region; a drain terminal formed on the graphene layer in a drain region; a gate stack fo rm ed on the graphene layer within a channel region disposed between the source te rm inal and the drain terminal, wherein the channel region comprises a spacer region and the gate stack comprises: a high-k dielectric layer; an adsorbed nitrogen dioxide (N O 2) layer formed on an adsorbent surface of the graphene layer in the channel region, the absorbed N O 2 layer in contact with the source terminal and the drain terminal and fo rm ing an adsorbate film between the high-k dielectric layer and the adsorbent surface of the graphene layer; and 2 a gate metal formed over the high-k dielectric layer. Currently amended
The NMOS transistor recited in claim 1, wherein the adsorbed N O 2 layer is further disposed between the spacer region and the graphene layer. Original
The NMOS transistor recited in claim 1, wherein the adsorbed N O 2 layer is configured to attract electrons from the graphene layer within the channel region to make the graphene layer electron-deficient in the channel region. Original
The NMOS transistor recited in claim 1, further comprising: a first spacer formed in the spacer region adjacent to a first sidewall of the gate stack; and a second spacer formed in the spacer region adjacent to a second sidewall of the gate stack, wherein the adsorbed N O 2 layer is disposed under the first spacer and the second spacer to reduce potential short-channel effects related to drain-induced barrier lowering (DIBL). Original
The NMOS transistor recited in claim 1, wherein the topmost surface of the substrate is formed from silicon carbide (Si C). Original
The NMOS transistor recited in claim 1, further comprising: interlayer dielectrics formed over the channel region, the source terminal in the source region, and the drain terminal in the drain region; and interconnects formed through the interlayer dielectrics to connect the source terminal to a source electrode, the gate metal to a gate electrode, and the drain terminal to a drain electrode. Original
A method for forming an n-type metal-oxide-semiconductor (NMOS) transistor, comprising: forming a graphene layer on a substrate surface; forming an adsorbed nitrogen dioxide layer on a portion of the graphene layer disposed in a channel region; forming a gate stack on a portion of the adsorbed nitrogen dioxide layer; forming spacer structures on the adsorbed nitrogen dioxide layer in spacer regions disposed within the channel region and adjacent to the gate stack; and forming a source stack and a drain stack on lateral portions of the graphene layer disposed adjacent to the adsorbed nitrogen dioxide layer. Withdrawn
The method recited in claim 11, wherein the substrate surface comprises a silicon (Si)- terminated face having the graphene layer epitaxially formed thereon. Withdrawn
The method recited in claim 11, wherein forming the adsorbed nitrogen dioxide layer comprises: developing a photoresist on the lateral portions of the graphene layer and leaving the portion of the graphene layer disposed in the channel region exposed; chemically adsorbing the nitrogen dioxide on the exposed portion of the graphene layer disposed in the channel region; and removing the photoresist developed on the lateral portions of the graphene layer. Withdrawn
The method recited in claim 11, wherein forming the gate stack comprises: developing a photoresist on the lateral portions of the graphene layer and the spacer regions disposed within the channel region and leaving a portion of the adsorbed nitrogen dioxide layer exposed; depositing a high-k dielectric on the photoresist and the exposed portion of the adsorbed nitrogen dioxide layer; depositing a gate metal on the high-k dielectric deposited on the photoresist and the exposed portion of the adsorbed nitrogen dioxide layer; and performing a lift-off process to remove the photoresist and the high-k dielectric and the gate metal deposited thereon. Withdrawn
The method recited in claim 11, wherein forming the spacer structures comp ri ses: depositing a spacer material on the lateral portions of the graphene layer, a portion of the adsorbed nitrogen dioxide layer disposed in the spacer regions, and the gate stack fo rm ed on the portion of the adsorbed nitrogen dioxide layer; and performing an etching process to remove the spacer material except the spacer material deposited on the portion of the adsorbed nitrogen dioxide layer disposed in the spacer regions. Withdrawn
A field-effect transistor, comprising: a source terminal, a drain terminal, and a gate; a graphene channel having an adsorbent surface with a nitrogen dioxide adsorbate film formed thereon, the nitrogen dioxide adsorbate film in contact with the source terminal and the drain terminal and forming an adsorbate film disposed under the gate between a high-k dielectric layer and the adsorbent surface of the graphene channel; and means for flowing electrons through the graphene channel, wherein: the nitrogen dioxide adsorbate film is configured to attract the electrons flowed through the graphene channel such that the field-effect transistor turns off at a gate voltage (V g) equal to zero, and the graphene channel has a doping concentration (N D) equal to zero such that the electrons flowed through the graphene channel have a maximum possible mobility (p). Currently amended
The field-effect transistor recited in claim 17, further comprising: a first spacer structure located in a first spacer region above the nitrogen dioxide adsorbate film and between the source terminal and the gate; and a second spacer structure located in a second spacer region above the nitrogen dioxide adsorbate film and between the drain terminal and the gate. Currently amended
A method for operating a field-effect transistor comprising a source, a drain, a gate, and a graphene channel having an adsorbent surface with a nitrogen dioxide adsorbate film under the gate and on the adsorbent surface, the method comprising: flowing electrons from the source to the drain and through the graphene channel, the graphene channel having a doping concentration (N D) equal to zero such that the flowed electrons have a maximum possible mobility (p); and applying a gate voltage (V g) to the field-effect transistor, wherein the nitrogen dioxide adsorbate film located under the gate attracts the electrons flowed through the graphene channel such that the field-effect transistor turns off at V g equals zero. Withdrawn
The method recited in claim 19, wherein the field-effect transistor further comprises a first spacer structure located in a first spacer region above the nitrogen dioxide adsorbate film and between the source and the gate and a second spacer structure located in a second spacer region above the nitrogen dioxide adsorbate film and between the drain and the gate. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
NMOS transistor with graphene channel and NO₂ adsorbate
field-effect transistor with graphene channel and NO₂ adsorbate film
Materials described outside the worked examples.
graphene
C
nitrogen dioxide adsorbate
NO₂
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 B -2C illustrate performance measurements associated with the top-gated field- effect transistor shown in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 15000 cm2/Vs | C |
Fet Mobility | 1330 cm2/Vs |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,038,060Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an exemplary graphene structure, according to various aspects. [0013]
FIG. 2 B -2C illustrate performance measurements associated with the top-gated field- effect transistor shown in
FIG. 3 illustrates an exemplary transistor structure that employs p-type doping in an attempt to capture electrons in a graphene channel, according to various …
FIG. 4 illustrates an exemplary graphene n-type metal-oxide-semiconductor (NMOS) transistor formed using nitrogen dioxide (N O 2) chemical adsorption in a …
FIG. 5 through
FIG. 6, the photoresist 108 is not formed over the graphene layer 106 in the channel region such that NO 2 can be selectively adsorbed on the graphene layer …
FIG. 7. At that point, as shown in
FIG. 8, the high-k dielectric 122 and the gate metal 124 may be deposited over the photoresist 120 in the source region and the channel region and over the NO₂ …
FIG. 9, a gate stack can then be formed, wherein the gate stack may comprise a high-k dielectric 122 (e.g., hafnium silicate, zirconium silicate, hafnium …
FIG. 11, a silicon nitride (SiN) layer 130 may then be deposited on the entire surface and an etching process may then QC₁₅₃₁ 17 Qualcomm Ref. No. 153117 10 be …
FIG. 12. For example, in various embodiments, a dry-etching (or plasma-etching) process can be used, whereby a source gas rich in chlorine or fluorine (e.g. …
FIG. 13, a photoresist 140 may be developed in the channel region to cover the SiN spacers 132 and the gate metal 124 used in the gate stack, thereby exposing …
FIG. 15, a silicon dioxide (SiO₂) layer 150 may then be deposited over the interface metal 142 in the source region and the drain region and the gate metal 124 …
FIG. 16 illustrate an exemplary process flow to form a graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0017]
FIG. 17 and FI G. 18 illustrate exemplary effects from using N O 2 chemical adsorption to form the graphene NMOS transistor, according to various aspects. [0018]
FIG. 19 illustrates an exemplary method to form the graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0019]
FIG. 20 illustrates an exemplary processor-based system that may comprise one or more integrated circuits that implement the graphene NMOS transistor described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An n-type metal-oxide-semiconductor (NMOS) transistor, comprising: a substrate having a graphene layer formed on a topmost surface; a source terminal fo rm ed on the graphene layer in a source region; a drain terminal formed on the graphene layer in a drain region; a gate stack fo rm ed on the graphene layer within a channel region disposed between the source te rm inal and the drain terminal, wherein the channel region comprises a spacer region and the gate stack comprises: a high-k dielectric layer; an adsorbed nitrogen dioxide (N O 2) layer formed on an adsorbent surface of the graphene layer in the channel region, the absorbed N O 2 layer in contact with the source terminal and the drain terminal and fo rm ing an adsorbate film between the high-k dielectric layer and the adsorbent surface of the graphene layer; and 2 a gate metal formed over the high-k dielectric layer. Currently amended
The NMOS transistor recited in claim 1, wherein the adsorbed N O 2 layer is further disposed between the spacer region and the graphene layer. Original
The NMOS transistor recited in claim 1, wherein the adsorbed N O 2 layer is configured to attract electrons from the graphene layer within the channel region to make the graphene layer electron-deficient in the channel region. Original
The NMOS transistor recited in claim 1, further comprising: a first spacer formed in the spacer region adjacent to a first sidewall of the gate stack; and a second spacer formed in the spacer region adjacent to a second sidewall of the gate stack, wherein the adsorbed N O 2 layer is disposed under the first spacer and the second spacer to reduce potential short-channel effects related to drain-induced barrier lowering (DIBL). Original
The NMOS transistor recited in claim 1, wherein the topmost surface of the substrate is formed from silicon carbide (Si C). Original
The NMOS transistor recited in claim 1, further comprising: interlayer dielectrics formed over the channel region, the source terminal in the source region, and the drain terminal in the drain region; and interconnects formed through the interlayer dielectrics to connect the source terminal to a source electrode, the gate metal to a gate electrode, and the drain terminal to a drain electrode. Original
A method for forming an n-type metal-oxide-semiconductor (NMOS) transistor, comprising: forming a graphene layer on a substrate surface; forming an adsorbed nitrogen dioxide layer on a portion of the graphene layer disposed in a channel region; forming a gate stack on a portion of the adsorbed nitrogen dioxide layer; forming spacer structures on the adsorbed nitrogen dioxide layer in spacer regions disposed within the channel region and adjacent to the gate stack; and forming a source stack and a drain stack on lateral portions of the graphene layer disposed adjacent to the adsorbed nitrogen dioxide layer. Withdrawn
The method recited in claim 11, wherein the substrate surface comprises a silicon (Si)- terminated face having the graphene layer epitaxially formed thereon. Withdrawn
The method recited in claim 11, wherein forming the adsorbed nitrogen dioxide layer comprises: developing a photoresist on the lateral portions of the graphene layer and leaving the portion of the graphene layer disposed in the channel region exposed; chemically adsorbing the nitrogen dioxide on the exposed portion of the graphene layer disposed in the channel region; and removing the photoresist developed on the lateral portions of the graphene layer. Withdrawn
The method recited in claim 11, wherein forming the gate stack comprises: developing a photoresist on the lateral portions of the graphene layer and the spacer regions disposed within the channel region and leaving a portion of the adsorbed nitrogen dioxide layer exposed; depositing a high-k dielectric on the photoresist and the exposed portion of the adsorbed nitrogen dioxide layer; depositing a gate metal on the high-k dielectric deposited on the photoresist and the exposed portion of the adsorbed nitrogen dioxide layer; and performing a lift-off process to remove the photoresist and the high-k dielectric and the gate metal deposited thereon. Withdrawn
The method recited in claim 11, wherein forming the spacer structures comp ri ses: depositing a spacer material on the lateral portions of the graphene layer, a portion of the adsorbed nitrogen dioxide layer disposed in the spacer regions, and the gate stack fo rm ed on the portion of the adsorbed nitrogen dioxide layer; and performing an etching process to remove the spacer material except the spacer material deposited on the portion of the adsorbed nitrogen dioxide layer disposed in the spacer regions. Withdrawn
A field-effect transistor, comprising: a source terminal, a drain terminal, and a gate; a graphene channel having an adsorbent surface with a nitrogen dioxide adsorbate film formed thereon, the nitrogen dioxide adsorbate film in contact with the source terminal and the drain terminal and forming an adsorbate film disposed under the gate between a high-k dielectric layer and the adsorbent surface of the graphene channel; and means for flowing electrons through the graphene channel, wherein: the nitrogen dioxide adsorbate film is configured to attract the electrons flowed through the graphene channel such that the field-effect transistor turns off at a gate voltage (V g) equal to zero, and the graphene channel has a doping concentration (N D) equal to zero such that the electrons flowed through the graphene channel have a maximum possible mobility (p). Currently amended
The field-effect transistor recited in claim 17, further comprising: a first spacer structure located in a first spacer region above the nitrogen dioxide adsorbate film and between the source terminal and the gate; and a second spacer structure located in a second spacer region above the nitrogen dioxide adsorbate film and between the drain terminal and the gate. Currently amended
A method for operating a field-effect transistor comprising a source, a drain, a gate, and a graphene channel having an adsorbent surface with a nitrogen dioxide adsorbate film under the gate and on the adsorbent surface, the method comprising: flowing electrons from the source to the drain and through the graphene channel, the graphene channel having a doping concentration (N D) equal to zero such that the flowed electrons have a maximum possible mobility (p); and applying a gate voltage (V g) to the field-effect transistor, wherein the nitrogen dioxide adsorbate film located under the gate attracts the electrons flowed through the graphene channel such that the field-effect transistor turns off at V g equals zero. Withdrawn
The method recited in claim 19, wherein the field-effect transistor further comprises a first spacer structure located in a first spacer region above the nitrogen dioxide adsorbate film and between the source and the gate and a second spacer structure located in a second spacer region above the nitrogen dioxide adsorbate film and between the drain and the gate. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
NMOS transistor with graphene channel and NO₂ adsorbate
field-effect transistor with graphene channel and NO₂ adsorbate film
Materials described outside the worked examples.
graphene
C
nitrogen dioxide adsorbate
NO₂
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 B -2C illustrate performance measurements associated with the top-gated field- effect transistor shown in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 15000 cm2/Vs | C |
Fet Mobility | 1330 cm2/Vs |
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FIG. 3 illustrates an exemplary transistor structure that employs p-type doping in an attempt to capture electrons in a graphene channel, according to various …
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FIG. 16 illustrate an exemplary process flow to form a graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0017]
FIG. 17 and FI G. 18 illustrate exemplary effects from using N O 2 chemical adsorption to form the graphene NMOS transistor, according to various aspects. [0018]
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FIG. 3 illustrates an exemplary transistor structure that employs p-type doping in an attempt to capture electrons in a graphene channel, according to various …
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FIG. 17 and FI G. 18 illustrate exemplary effects from using N O 2 chemical adsorption to form the graphene NMOS transistor, according to various aspects. [0018]
FIG. 19 illustrates an exemplary method to form the graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0019]
FIG. 20 illustrates an exemplary processor-based system that may comprise one or more integrated circuits that implement the graphene NMOS transistor described …
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Fet Mobility | 250 cm2/Vs | C |
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FIG. 3 illustrates an exemplary transistor structure that employs p-type doping in an attempt to capture electrons in a graphene channel, according to various …
FIG. 4 illustrates an exemplary graphene n-type metal-oxide-semiconductor (NMOS) transistor formed using nitrogen dioxide (N O 2) chemical adsorption in a …
FIG. 16 illustrate an exemplary process flow to form a graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0017]
FIG. 17 and FI G. 18 illustrate exemplary effects from using N O 2 chemical adsorption to form the graphene NMOS transistor, according to various aspects. [0018]
FIG. 19 illustrates an exemplary method to form the graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0019]
FIG. 20 illustrates an exemplary processor-based system that may comprise one or more integrated circuits that implement the graphene NMOS transistor described …
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Fet Mobility | 250 cm2/Vs | C |
high-k dielectric
silicon nitride
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silicon carbide
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FIG. 3 illustrates an exemplary transistor structure that employs p-type doping in an attempt to capture electrons in a graphene channel, according to various …
FIG. 4 illustrates an exemplary graphene n-type metal-oxide-semiconductor (NMOS) transistor formed using nitrogen dioxide (N O 2) chemical adsorption in a …
FIG. 16 illustrate an exemplary process flow to form a graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0017]
FIG. 17 and FI G. 18 illustrate exemplary effects from using N O 2 chemical adsorption to form the graphene NMOS transistor, according to various aspects. [0018]
FIG. 19 illustrates an exemplary method to form the graphene NMOS transistor using N O 2 chemical adsorption, according to various aspects. [0019]
FIG. 20 illustrates an exemplary processor-based system that may comprise one or more integrated circuits that implement the graphene NMOS transistor described …
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