Patent
US 11,869,946 B2ETCH-LESS ALGAN GAN TRIGATE TRANSISTOR
Kon Hoo Teo, Nadim Chowdhury
Mitsubishi Electric Research Laboratories, Inc., Cambridge, MA (US)·Jan. 9, 2024·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,869,946 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structure and thicknesses of the transistor device, according to some …
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
FIGS. 25 2A-2D) at selective locations 113 in the sub-region Rsub. Contemplated is that a gap distance between the source 104 and the gate 111, and a gap …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor, comprising: a source; a gate; 25 a drain; a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer; and 30 a sub-region of the semiconductor region underneath the gate doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor.
The field effect transistor of claim 1, wherein the semiconductor region includes a base layer, a buffer layer over the base layer, wherein the GaN layer is over the buffer layer.
The field effect transistor of claim 1, wherein the III-N layer is an AlxInyGal-x-yN, such that a value of x and y is between 0 and 1 (0≤x≤1), (0≤y≤1).
The field effect transistor of claim 1, wherein the III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the GaN layer.
The field effect transistor of claim 1, wherein the vertical thickness of the GaN layer is greater than a vertical thickness of the III-N layer.
The field effect transistor of claim 1, wherein the vertical thickness of the GaN layer is 10 times thicker than 55 a vertical thickness of the III-N layer, or the vertical thick-ness of the GaN layer is 1000% percent thicker than the vertical thickness of the III-N layer.
The field effect transistor of claim 1, wherein a gap distance between the source and the gate, and a gap distance between the gate and the drain, is one of symmetrical or non-symmetrical.
The field effect transistor of claim 1, wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the field effect transistor.
The field effect transistor of claim 1, wherein each profile of the selective locations has one or a combination of, B₂ a constant profile width, a variable profile width, a constant vertical profile length or a variable vertical profile length.
The field effect transistor of claim 1, wherein each profile is equally spaced along a width of the field effect transistor, or wherein each profile is not equally spaced from each other and is varied along a width of the field effect transistor.
The field effect transistor of claim 1, wherein the selective locations doped with Mg ions in the sub-region have profiles, such that the profiles are arranged at an angle within a range from 90 degrees to 80 degrees with respect to a plane of the III-N layer.
The field effect transistor of claim 1, wherein at an interface of the GaN layer and III-N layer there is an accumulation of two-dimensional gas (2-DEG), wherein the selective locations doped with Mg ions in the sub-region comprise Mg ion implantation regions such that the accu-mulation of the 2-DEG is depleted by the Mg ion implan-tation regions, resulting in an enhancement-mode (E-mode) operation for the field effect transistor.
The field effect transistor of claim 1, wherein upon completion of the doping of the Mg ions in the selective locations in the sub-region, the sub-region is then annealed in a nitrogen gas environment.
The field effect transistor of claim 1, wherein the III-N layer is an aluminum gallium nitride (AlGaN), and wherein the selective locations doped with Mg ions in the sub-region convert the AlGaN layer to p-AlGaN, and convert the GaN layer to p-GaN, which results in generating holes in the Mg ion implanted selective locations of the sub-region.
The field effect transistor of claim 1, wherein each of the selective locations doped with Mg ions in the sub-region has a depth extending from a top edge of the III-N layer across an interface of a bottom edge of the III-N layer into a top edge of the GaN layer.
A transistor, comprising: a source; a gate; a drain; a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer, wherein GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap, wherein the GaN layer and the III-N layer are undoped; and a sub-region of the semiconductor region underneath the gate is doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor.
The transistor of claim 16, wherein the GaN layer and III-N layer are grown using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD), and wherein the selective locations doped with Mg ions in the sub-region are formed by Mg ion implantation.
A transistor, comprising: a source; a gate; a drain; 19 20 a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer, wherein GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap, wherein the III-N layer has a higher spontaneous polar-ization charge than a spontaneous polarization charge of the GaN layer; and a sub-region of the semiconductor region underneath the gate is doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
etch-less AlGaN/GaN trigate field effect transistor (claim 1)
transistor with undoped GaN and III-N layers (claim 16)
Materials described outside the worked examples.
gallium nitride
GaN
III-Nitride layer
III-N
Mg-ion-implanted sub-region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structure and thicknesses of the transistor device, according to some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage range for Trigate FinFET depending on fin-width | 0.2–1.5 V | — |
Thickness | 5–30 nm |
Patents and literature cited by this patent (applicant and examiner references).
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US 11,869,946 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structure and thicknesses of the transistor device, according to some …
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
FIGS. 25 2A-2D) at selective locations 113 in the sub-region Rsub. Contemplated is that a gap distance between the source 104 and the gate 111, and a gap …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor, comprising: a source; a gate; 25 a drain; a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer; and 30 a sub-region of the semiconductor region underneath the gate doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor.
The field effect transistor of claim 1, wherein the semiconductor region includes a base layer, a buffer layer over the base layer, wherein the GaN layer is over the buffer layer.
The field effect transistor of claim 1, wherein the III-N layer is an AlxInyGal-x-yN, such that a value of x and y is between 0 and 1 (0≤x≤1), (0≤y≤1).
The field effect transistor of claim 1, wherein the III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the GaN layer.
The field effect transistor of claim 1, wherein the vertical thickness of the GaN layer is greater than a vertical thickness of the III-N layer.
The field effect transistor of claim 1, wherein the vertical thickness of the GaN layer is 10 times thicker than 55 a vertical thickness of the III-N layer, or the vertical thick-ness of the GaN layer is 1000% percent thicker than the vertical thickness of the III-N layer.
The field effect transistor of claim 1, wherein a gap distance between the source and the gate, and a gap distance between the gate and the drain, is one of symmetrical or non-symmetrical.
The field effect transistor of claim 1, wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the field effect transistor.
The field effect transistor of claim 1, wherein each profile of the selective locations has one or a combination of, B₂ a constant profile width, a variable profile width, a constant vertical profile length or a variable vertical profile length.
The field effect transistor of claim 1, wherein each profile is equally spaced along a width of the field effect transistor, or wherein each profile is not equally spaced from each other and is varied along a width of the field effect transistor.
The field effect transistor of claim 1, wherein the selective locations doped with Mg ions in the sub-region have profiles, such that the profiles are arranged at an angle within a range from 90 degrees to 80 degrees with respect to a plane of the III-N layer.
The field effect transistor of claim 1, wherein at an interface of the GaN layer and III-N layer there is an accumulation of two-dimensional gas (2-DEG), wherein the selective locations doped with Mg ions in the sub-region comprise Mg ion implantation regions such that the accu-mulation of the 2-DEG is depleted by the Mg ion implan-tation regions, resulting in an enhancement-mode (E-mode) operation for the field effect transistor.
The field effect transistor of claim 1, wherein upon completion of the doping of the Mg ions in the selective locations in the sub-region, the sub-region is then annealed in a nitrogen gas environment.
The field effect transistor of claim 1, wherein the III-N layer is an aluminum gallium nitride (AlGaN), and wherein the selective locations doped with Mg ions in the sub-region convert the AlGaN layer to p-AlGaN, and convert the GaN layer to p-GaN, which results in generating holes in the Mg ion implanted selective locations of the sub-region.
The field effect transistor of claim 1, wherein each of the selective locations doped with Mg ions in the sub-region has a depth extending from a top edge of the III-N layer across an interface of a bottom edge of the III-N layer into a top edge of the GaN layer.
A transistor, comprising: a source; a gate; a drain; a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer, wherein GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap, wherein the GaN layer and the III-N layer are undoped; and a sub-region of the semiconductor region underneath the gate is doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor.
The transistor of claim 16, wherein the GaN layer and III-N layer are grown using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD), and wherein the selective locations doped with Mg ions in the sub-region are formed by Mg ion implantation.
A transistor, comprising: a source; a gate; a drain; 19 20 a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer, wherein GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap, wherein the III-N layer has a higher spontaneous polar-ization charge than a spontaneous polarization charge of the GaN layer; and a sub-region of the semiconductor region underneath the gate is doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
etch-less AlGaN/GaN trigate field effect transistor (claim 1)
transistor with undoped GaN and III-N layers (claim 16)
Materials described outside the worked examples.
gallium nitride
GaN
III-Nitride layer
III-N
Mg-ion-implanted sub-region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structure and thicknesses of the transistor device, according to some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage range for Trigate FinFET depending on fin-width | 0.2–1.5 V | — |
Thickness | 5–30 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
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Super Junction Gated AlGaN GaN HEMT
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US 11,869,946 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structure and thicknesses of the transistor device, according to some …
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
FIGS. 25 2A-2D) at selective locations 113 in the sub-region Rsub. Contemplated is that a gap distance between the source 104 and the gate 111, and a gap …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor, comprising: a source; a gate; 25 a drain; a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer; and 30 a sub-region of the semiconductor region underneath the gate doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor.
The field effect transistor of claim 1, wherein the semiconductor region includes a base layer, a buffer layer over the base layer, wherein the GaN layer is over the buffer layer.
The field effect transistor of claim 1, wherein the III-N layer is an AlxInyGal-x-yN, such that a value of x and y is between 0 and 1 (0≤x≤1), (0≤y≤1).
The field effect transistor of claim 1, wherein the III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the GaN layer.
The field effect transistor of claim 1, wherein the vertical thickness of the GaN layer is greater than a vertical thickness of the III-N layer.
The field effect transistor of claim 1, wherein the vertical thickness of the GaN layer is 10 times thicker than 55 a vertical thickness of the III-N layer, or the vertical thick-ness of the GaN layer is 1000% percent thicker than the vertical thickness of the III-N layer.
The field effect transistor of claim 1, wherein a gap distance between the source and the gate, and a gap distance between the gate and the drain, is one of symmetrical or non-symmetrical.
The field effect transistor of claim 1, wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the field effect transistor.
The field effect transistor of claim 1, wherein each profile of the selective locations has one or a combination of, B₂ a constant profile width, a variable profile width, a constant vertical profile length or a variable vertical profile length.
The field effect transistor of claim 1, wherein each profile is equally spaced along a width of the field effect transistor, or wherein each profile is not equally spaced from each other and is varied along a width of the field effect transistor.
The field effect transistor of claim 1, wherein the selective locations doped with Mg ions in the sub-region have profiles, such that the profiles are arranged at an angle within a range from 90 degrees to 80 degrees with respect to a plane of the III-N layer.
The field effect transistor of claim 1, wherein at an interface of the GaN layer and III-N layer there is an accumulation of two-dimensional gas (2-DEG), wherein the selective locations doped with Mg ions in the sub-region comprise Mg ion implantation regions such that the accu-mulation of the 2-DEG is depleted by the Mg ion implan-tation regions, resulting in an enhancement-mode (E-mode) operation for the field effect transistor.
The field effect transistor of claim 1, wherein upon completion of the doping of the Mg ions in the selective locations in the sub-region, the sub-region is then annealed in a nitrogen gas environment.
The field effect transistor of claim 1, wherein the III-N layer is an aluminum gallium nitride (AlGaN), and wherein the selective locations doped with Mg ions in the sub-region convert the AlGaN layer to p-AlGaN, and convert the GaN layer to p-GaN, which results in generating holes in the Mg ion implanted selective locations of the sub-region.
The field effect transistor of claim 1, wherein each of the selective locations doped with Mg ions in the sub-region has a depth extending from a top edge of the III-N layer across an interface of a bottom edge of the III-N layer into a top edge of the GaN layer.
A transistor, comprising: a source; a gate; a drain; a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer, wherein GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap, wherein the GaN layer and the III-N layer are undoped; and a sub-region of the semiconductor region underneath the gate is doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor.
The transistor of claim 16, wherein the GaN layer and III-N layer are grown using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD), and wherein the selective locations doped with Mg ions in the sub-region are formed by Mg ion implantation.
A transistor, comprising: a source; a gate; a drain; 19 20 a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer, wherein GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap, wherein the III-N layer has a higher spontaneous polar-ization charge than a spontaneous polarization charge of the GaN layer; and a sub-region of the semiconductor region underneath the gate is doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
etch-less AlGaN/GaN trigate field effect transistor (claim 1)
transistor with undoped GaN and III-N layers (claim 16)
Materials described outside the worked examples.
gallium nitride
GaN
III-Nitride layer
III-N
Mg-ion-implanted sub-region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structure and thicknesses of the transistor device, according to some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage range for Trigate FinFET depending on fin-width | 0.2–1.5 V | — |
Thickness | 5–30 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR EPITAXIAL WAFER WITH AN INGAN/GAN CAP LAYER COMPRISING FIRST SUBLAYERS DOPED WITH A MAIN DOPING ELEMENT AND SECOND SUBLAYERS DOPED WITH THE FIRST DOPING ELEMENT AND AN AUXILIARY DOPING ELEMENT, AND PREPARATION METHOD THEREFOR
Super Junction Gated AlGaN GaN HEMT
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Atlas literature
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US 11,869,946 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structure and thicknesses of the transistor device, according to some …
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
FIGS. 25 2A-2D) at selective locations 113 in the sub-region Rsub. Contemplated is that a gap distance between the source 104 and the gate 111, and a gap …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor, comprising: a source; a gate; 25 a drain; a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer; and 30 a sub-region of the semiconductor region underneath the gate doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor.
The field effect transistor of claim 1, wherein the semiconductor region includes a base layer, a buffer layer over the base layer, wherein the GaN layer is over the buffer layer.
The field effect transistor of claim 1, wherein the III-N layer is an AlxInyGal-x-yN, such that a value of x and y is between 0 and 1 (0≤x≤1), (0≤y≤1).
The field effect transistor of claim 1, wherein the III-N layer has a higher spontaneous polarization charge than a spontaneous polarization charge of the GaN layer.
The field effect transistor of claim 1, wherein the vertical thickness of the GaN layer is greater than a vertical thickness of the III-N layer.
The field effect transistor of claim 1, wherein the vertical thickness of the GaN layer is 10 times thicker than 55 a vertical thickness of the III-N layer, or the vertical thick-ness of the GaN layer is 1000% percent thicker than the vertical thickness of the III-N layer.
The field effect transistor of claim 1, wherein a gap distance between the source and the gate, and a gap distance between the gate and the drain, is one of symmetrical or non-symmetrical.
The field effect transistor of claim 1, wherein a gap distance between the gate and the drain correlates to a breakdown voltage of the field effect transistor.
The field effect transistor of claim 1, wherein each profile of the selective locations has one or a combination of, B₂ a constant profile width, a variable profile width, a constant vertical profile length or a variable vertical profile length.
The field effect transistor of claim 1, wherein each profile is equally spaced along a width of the field effect transistor, or wherein each profile is not equally spaced from each other and is varied along a width of the field effect transistor.
The field effect transistor of claim 1, wherein the selective locations doped with Mg ions in the sub-region have profiles, such that the profiles are arranged at an angle within a range from 90 degrees to 80 degrees with respect to a plane of the III-N layer.
The field effect transistor of claim 1, wherein at an interface of the GaN layer and III-N layer there is an accumulation of two-dimensional gas (2-DEG), wherein the selective locations doped with Mg ions in the sub-region comprise Mg ion implantation regions such that the accu-mulation of the 2-DEG is depleted by the Mg ion implan-tation regions, resulting in an enhancement-mode (E-mode) operation for the field effect transistor.
The field effect transistor of claim 1, wherein upon completion of the doping of the Mg ions in the selective locations in the sub-region, the sub-region is then annealed in a nitrogen gas environment.
The field effect transistor of claim 1, wherein the III-N layer is an aluminum gallium nitride (AlGaN), and wherein the selective locations doped with Mg ions in the sub-region convert the AlGaN layer to p-AlGaN, and convert the GaN layer to p-GaN, which results in generating holes in the Mg ion implanted selective locations of the sub-region.
The field effect transistor of claim 1, wherein each of the selective locations doped with Mg ions in the sub-region has a depth extending from a top edge of the III-N layer across an interface of a bottom edge of the III-N layer into a top edge of the GaN layer.
A transistor, comprising: a source; a gate; a drain; a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer, wherein GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap, wherein the GaN layer and the III-N layer are undoped; and a sub-region of the semiconductor region underneath the gate is doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor.
The transistor of claim 16, wherein the GaN layer and III-N layer are grown using one or a combination of metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD), and wherein the selective locations doped with Mg ions in the sub-region are formed by Mg ion implantation.
A transistor, comprising: a source; a gate; a drain; 19 20 a semiconductor region under the source, the gate and the drain, such that the semiconductor region includes a gallium nitride (GaN) layer and a three nitride (III-N) layer, wherein GaN layer includes a band gap, and the III-N layer includes a band gap, such that the III-N layer band gap is higher than the GaN layer band gap, wherein the III-N layer has a higher spontaneous polar-ization charge than a spontaneous polarization charge of the GaN layer; and a sub-region of the semiconductor region underneath the gate is doped with Mg ions at selective locations in the sub-region, wherein each of the selective locations doped with Mg ions in the sub-region has a profile, such that the profile includes a vertical profile length and a profile width, and wherein the profiles form a pattern, such that profile widths of the profiles increase along a direction from a first width end to a second width end of the field effect transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
etch-less AlGaN/GaN trigate field effect transistor (claim 1)
transistor with undoped GaN and III-N layers (claim 16)
Materials described outside the worked examples.
gallium nitride
GaN
III-Nitride layer
III-N
Mg-ion-implanted sub-region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, showing the structure and thicknesses of the gate stack, along with other structure and thicknesses of the transistor device, according to some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage range for Trigate FinFET depending on fin-width | 0.2–1.5 V | — |
Thickness | 5–30 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR EPITAXIAL WAFER WITH AN INGAN/GAN CAP LAYER COMPRISING FIRST SUBLAYERS DOPED WITH A MAIN DOPING ELEMENT AND SECOND SUBLAYERS DOPED WITH THE FIRST DOPING ELEMENT AND AN AUXILIARY DOPING ELEMENT, AND PREPARATION METHOD THEREFOR
Super Junction Gated AlGaN GaN HEMT
transistor with higher spontaneous polarization III-N layer (claim 18)
p-type aluminum gallium nitride
p-AlGaN
p-type gallium nitride
p-GaN
aluminum gallium nitride
AlGaN
AlxInyGa(1-x-y)N
AlxInyGa₁-x-yN
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
Pressure | 10–760 Torr | — |
Cited non-patent literature · 4
transistor with higher spontaneous polarization III-N layer (claim 18)
p-type aluminum gallium nitride
p-AlGaN
p-type gallium nitride
p-GaN
aluminum gallium nitride
AlGaN
AlxInyGa(1-x-y)N
AlxInyGa₁-x-yN
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
Pressure | 10–760 Torr | — |
Cited non-patent literature · 4
transistor with higher spontaneous polarization III-N layer (claim 18)
p-type aluminum gallium nitride
p-AlGaN
p-type gallium nitride
p-GaN
aluminum gallium nitride
AlGaN
AlxInyGa(1-x-y)N
AlxInyGa₁-x-yN
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
Pressure | 10–760 Torr | — |
Cited non-patent literature · 4
transistor with higher spontaneous polarization III-N layer (claim 18)
p-type aluminum gallium nitride
p-AlGaN
p-type gallium nitride
p-GaN
aluminum gallium nitride
AlGaN
AlxInyGa(1-x-y)N
AlxInyGa₁-x-yN
FIG. 2B is a schematic illustrating another cross section of the gate of the transistor device of
FIG. 3 is a block diagram illustrating a fabrication process of the transistor device, according to some embodiments of the present disclosure. While the …
Pressure | 10–760 Torr | — |
Cited non-patent literature · 4