Patent
US 11,158,702GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR HAVING HIGH BREAKDOWN VOLTAGE AND FORMATION METHOD THEREFOR
Chen LI
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, a schematic flowchart of a formation method for a gallium nitride high electron mobility transistor having a high breakdown voltage according to a one …
FIG. 2 illustrates a schematic sectional structural diagram after a first step of a formation process of the gallium nitride high electron mobility transistor …
FIG. 3 illustrates a schematic sectional structural diagram after a second step of the formation process of the gallium nitride high electron mobility …
FIG. 4 illustrates a schematic sectional structural diagram after a third step of the formation process of the gallium nitride high electron mobility …
FIG. 5 illustrates a schematic sectional structural diagram after a fourth step of the formation process of the gallium nitride high electron mobility …
FIG. 6, the high electron mobility transistor includes: a substrate 200; a channel layer 303 disposed on the substrate 200; a first barrier layer 305 disposed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride high electron mobility transistor, comprising: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source, and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; [[and]] a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas; and a nucleation layer and a buffer layer disposed on the nucleation layer, wherein the nucleation layer and the buffer layer are disposed between the substrate and the gallium nitride channel layer, and wherein the buffer layer has a resistivity to prevent electrons in the gallium nitride channel layer from leaking to the buffer layer. Currently amended
The gallium nitride high electron mobility transistor according to claim 1, wherein the second barrier layer comprises: a first sub-layer disposed on the surface of the first barrier layer, a second sub-layer disposed on a surface of the second sub-layer and a third sub- layer disposed on a surface of the second sub-layer, the first sub-layer and the second sub-layer forming a heterojunction, and the third sub-layer being P-doped. Original
The gallium nitride high electron mobility transistor according to claim 1, wherein the buffer layer has the resistivity over 10 6 ohms cm. New
Canceled
The gallium nitride high electron mobility transistor according to claim [[3]] _, wherein an insert layer is further defined between the gallium channel layer and the first barrier layer. Currently amended
The gallium nitride high electron mobility transistor according to claim 4, wherein the first sub-layer is made of aluminum nitride, gallium nitride or aluminum gallium nitride; the second sub-layer is made of gallium nitride, aluminum nitride or aluminum gallium nitride; the third sublayer is made from P-type gallium nitride, P-type aluminum nitride or P- type aluminum gallium nitride; the nucleation layer is made of a gallium nitride, aluminum nitride or aluminum gallium nitride; the buffer layer is made of gallium nitride; the insert layer is made of aluminum nitride; and the first barrier layer is made of aluminum gallium nitride or indium aluminum nitride. Original
A formation method for a gallium nitride high electron mobility transistor, comprising: providing a substrate; forming a gallium channel layer and a first barrier layer disposed on the gallium channel layer in sequence on the substrate; forming a second barrier layer on a surface of the first barrier layer, the second barrier layer being configured to generate two-dimensional hole gas; etching the second barrier layer to expose a part of the surface of the first barrier layer; [[and]] forming a source, a drain, and a gate respectively on the surface of the first barrier layer, the gate being positioned between the source and the second barrier layer, and a side wall on one side of the gate being connected to a side wall of the second barrier layer; and forming a nucleation layer and a buffer layer disposed on a surface of the nucleation layer, wherein the nucleation layer and the buffer layer are disposed between the substrate and the gallium channel layer, and wherein the buffer layer has a resistivity to prevent electrons in the gallium channel layer from leaking to the buffer layer. Currently amended
The formation method for a gallium nitride high electron mobility transistor according to claim 6, wherein the second barrier layer comprises a first sub-layer disposed on the surface of the first barrier layer, a second sub-layer disposed on a surface of the second sub-layer and a third sublayer disposed on a surface of the second sub-layer, the first sub-layer and the second sub-layer forming a heterojunction, and the third sub-layer being P-doped. Original
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride high electron mobility transistor
Materials described outside the worked examples.
gallium nitride channel layer
GaN
first barrier layer
second barrier layer
insert layer
AlN
aluminum gallium nitride (first sub-layer option)
AlGaN
P-type gallium nitride (third sub-layer option)
p-GaN
P-type aluminum nitride (third sub-layer option)
p-AlN
P-type aluminum gallium nitride (third sub-layer option)
p-AlGaN
indium aluminum nitride (first barrier layer option)
InAlN
substrate
nucleation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, a schematic flowchart of a formation method for a gallium nitride high electron mobility transistor having a high breakdown voltage according to a one …
FIG. 2 illustrates a schematic sectional structural diagram after a first step of a formation process of the gallium nitride high electron mobility transistor …
FIG. 3 illustrates a schematic sectional structural diagram after a second step of the formation process of the gallium nitride high electron mobility …
FIG. 4 illustrates a schematic sectional structural diagram after a third step of the formation process of the gallium nitride high electron mobility …
FIG. 5 illustrates a schematic sectional structural diagram after a fourth step of the formation process of the gallium nitride high electron mobility …
FIG. 6, the high electron mobility transistor includes: a substrate 200; a channel layer 303 disposed on the substrate 200; a first barrier layer 305 disposed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
buffer_layer_resistivity | >1e6 ohms·cm | GaN |
Thickness | 1–100 nm | — |
Temperature | 1100–1150 °C | — |
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GALLIUM NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR EPITAXIAL WAFER WITH AN INGAN/GAN CAP LAYER COMPRISING FIRST SUBLAYERS DOPED WITH A MAIN DOPING ELEMENT AND SECOND SUBLAYERS DOPED WITH THE FIRST DOPING ELEMENT AND AN AUXILIARY DOPING ELEMENT, AND PREPARATION METHOD THEREFOR
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, a schematic flowchart of a formation method for a gallium nitride high electron mobility transistor having a high breakdown voltage according to a one …
FIG. 2 illustrates a schematic sectional structural diagram after a first step of a formation process of the gallium nitride high electron mobility transistor …
FIG. 3 illustrates a schematic sectional structural diagram after a second step of the formation process of the gallium nitride high electron mobility …
FIG. 4 illustrates a schematic sectional structural diagram after a third step of the formation process of the gallium nitride high electron mobility …
FIG. 5 illustrates a schematic sectional structural diagram after a fourth step of the formation process of the gallium nitride high electron mobility …
FIG. 6, the high electron mobility transistor includes: a substrate 200; a channel layer 303 disposed on the substrate 200; a first barrier layer 305 disposed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride high electron mobility transistor, comprising: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source, and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; [[and]] a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas; and a nucleation layer and a buffer layer disposed on the nucleation layer, wherein the nucleation layer and the buffer layer are disposed between the substrate and the gallium nitride channel layer, and wherein the buffer layer has a resistivity to prevent electrons in the gallium nitride channel layer from leaking to the buffer layer. Currently amended
The gallium nitride high electron mobility transistor according to claim 1, wherein the second barrier layer comprises: a first sub-layer disposed on the surface of the first barrier layer, a second sub-layer disposed on a surface of the second sub-layer and a third sub- layer disposed on a surface of the second sub-layer, the first sub-layer and the second sub-layer forming a heterojunction, and the third sub-layer being P-doped. Original
The gallium nitride high electron mobility transistor according to claim 1, wherein the buffer layer has the resistivity over 10 6 ohms cm. New
Canceled
The gallium nitride high electron mobility transistor according to claim [[3]] _, wherein an insert layer is further defined between the gallium channel layer and the first barrier layer. Currently amended
The gallium nitride high electron mobility transistor according to claim 4, wherein the first sub-layer is made of aluminum nitride, gallium nitride or aluminum gallium nitride; the second sub-layer is made of gallium nitride, aluminum nitride or aluminum gallium nitride; the third sublayer is made from P-type gallium nitride, P-type aluminum nitride or P- type aluminum gallium nitride; the nucleation layer is made of a gallium nitride, aluminum nitride or aluminum gallium nitride; the buffer layer is made of gallium nitride; the insert layer is made of aluminum nitride; and the first barrier layer is made of aluminum gallium nitride or indium aluminum nitride. Original
A formation method for a gallium nitride high electron mobility transistor, comprising: providing a substrate; forming a gallium channel layer and a first barrier layer disposed on the gallium channel layer in sequence on the substrate; forming a second barrier layer on a surface of the first barrier layer, the second barrier layer being configured to generate two-dimensional hole gas; etching the second barrier layer to expose a part of the surface of the first barrier layer; [[and]] forming a source, a drain, and a gate respectively on the surface of the first barrier layer, the gate being positioned between the source and the second barrier layer, and a side wall on one side of the gate being connected to a side wall of the second barrier layer; and forming a nucleation layer and a buffer layer disposed on a surface of the nucleation layer, wherein the nucleation layer and the buffer layer are disposed between the substrate and the gallium channel layer, and wherein the buffer layer has a resistivity to prevent electrons in the gallium channel layer from leaking to the buffer layer. Currently amended
The formation method for a gallium nitride high electron mobility transistor according to claim 6, wherein the second barrier layer comprises a first sub-layer disposed on the surface of the first barrier layer, a second sub-layer disposed on a surface of the second sub-layer and a third sublayer disposed on a surface of the second sub-layer, the first sub-layer and the second sub-layer forming a heterojunction, and the third sub-layer being P-doped. Original
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride high electron mobility transistor
Materials described outside the worked examples.
gallium nitride channel layer
GaN
first barrier layer
second barrier layer
insert layer
AlN
aluminum gallium nitride (first sub-layer option)
AlGaN
P-type gallium nitride (third sub-layer option)
p-GaN
P-type aluminum nitride (third sub-layer option)
p-AlN
P-type aluminum gallium nitride (third sub-layer option)
p-AlGaN
indium aluminum nitride (first barrier layer option)
InAlN
substrate
nucleation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, a schematic flowchart of a formation method for a gallium nitride high electron mobility transistor having a high breakdown voltage according to a one …
FIG. 2 illustrates a schematic sectional structural diagram after a first step of a formation process of the gallium nitride high electron mobility transistor …
FIG. 3 illustrates a schematic sectional structural diagram after a second step of the formation process of the gallium nitride high electron mobility …
FIG. 4 illustrates a schematic sectional structural diagram after a third step of the formation process of the gallium nitride high electron mobility …
FIG. 5 illustrates a schematic sectional structural diagram after a fourth step of the formation process of the gallium nitride high electron mobility …
FIG. 6, the high electron mobility transistor includes: a substrate 200; a channel layer 303 disposed on the substrate 200; a first barrier layer 305 disposed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
buffer_layer_resistivity | >1e6 ohms·cm | GaN |
Thickness | 1–100 nm | — |
Temperature | 1100–1150 °C | — |
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, a schematic flowchart of a formation method for a gallium nitride high electron mobility transistor having a high breakdown voltage according to a one …
FIG. 2 illustrates a schematic sectional structural diagram after a first step of a formation process of the gallium nitride high electron mobility transistor …
FIG. 3 illustrates a schematic sectional structural diagram after a second step of the formation process of the gallium nitride high electron mobility …
FIG. 4 illustrates a schematic sectional structural diagram after a third step of the formation process of the gallium nitride high electron mobility …
FIG. 5 illustrates a schematic sectional structural diagram after a fourth step of the formation process of the gallium nitride high electron mobility …
FIG. 6, the high electron mobility transistor includes: a substrate 200; a channel layer 303 disposed on the substrate 200; a first barrier layer 305 disposed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride high electron mobility transistor, comprising: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source, and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; [[and]] a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas; and a nucleation layer and a buffer layer disposed on the nucleation layer, wherein the nucleation layer and the buffer layer are disposed between the substrate and the gallium nitride channel layer, and wherein the buffer layer has a resistivity to prevent electrons in the gallium nitride channel layer from leaking to the buffer layer. Currently amended
The gallium nitride high electron mobility transistor according to claim 1, wherein the second barrier layer comprises: a first sub-layer disposed on the surface of the first barrier layer, a second sub-layer disposed on a surface of the second sub-layer and a third sub- layer disposed on a surface of the second sub-layer, the first sub-layer and the second sub-layer forming a heterojunction, and the third sub-layer being P-doped. Original
The gallium nitride high electron mobility transistor according to claim 1, wherein the buffer layer has the resistivity over 10 6 ohms cm. New
Canceled
The gallium nitride high electron mobility transistor according to claim [[3]] _, wherein an insert layer is further defined between the gallium channel layer and the first barrier layer. Currently amended
The gallium nitride high electron mobility transistor according to claim 4, wherein the first sub-layer is made of aluminum nitride, gallium nitride or aluminum gallium nitride; the second sub-layer is made of gallium nitride, aluminum nitride or aluminum gallium nitride; the third sublayer is made from P-type gallium nitride, P-type aluminum nitride or P- type aluminum gallium nitride; the nucleation layer is made of a gallium nitride, aluminum nitride or aluminum gallium nitride; the buffer layer is made of gallium nitride; the insert layer is made of aluminum nitride; and the first barrier layer is made of aluminum gallium nitride or indium aluminum nitride. Original
A formation method for a gallium nitride high electron mobility transistor, comprising: providing a substrate; forming a gallium channel layer and a first barrier layer disposed on the gallium channel layer in sequence on the substrate; forming a second barrier layer on a surface of the first barrier layer, the second barrier layer being configured to generate two-dimensional hole gas; etching the second barrier layer to expose a part of the surface of the first barrier layer; [[and]] forming a source, a drain, and a gate respectively on the surface of the first barrier layer, the gate being positioned between the source and the second barrier layer, and a side wall on one side of the gate being connected to a side wall of the second barrier layer; and forming a nucleation layer and a buffer layer disposed on a surface of the nucleation layer, wherein the nucleation layer and the buffer layer are disposed between the substrate and the gallium channel layer, and wherein the buffer layer has a resistivity to prevent electrons in the gallium channel layer from leaking to the buffer layer. Currently amended
The formation method for a gallium nitride high electron mobility transistor according to claim 6, wherein the second barrier layer comprises a first sub-layer disposed on the surface of the first barrier layer, a second sub-layer disposed on a surface of the second sub-layer and a third sublayer disposed on a surface of the second sub-layer, the first sub-layer and the second sub-layer forming a heterojunction, and the third sub-layer being P-doped. Original
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride high electron mobility transistor
Materials described outside the worked examples.
gallium nitride channel layer
GaN
first barrier layer
second barrier layer
insert layer
AlN
aluminum gallium nitride (first sub-layer option)
AlGaN
P-type gallium nitride (third sub-layer option)
p-GaN
P-type aluminum nitride (third sub-layer option)
p-AlN
P-type aluminum gallium nitride (third sub-layer option)
p-AlGaN
indium aluminum nitride (first barrier layer option)
InAlN
substrate
nucleation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, a schematic flowchart of a formation method for a gallium nitride high electron mobility transistor having a high breakdown voltage according to a one …
FIG. 2 illustrates a schematic sectional structural diagram after a first step of a formation process of the gallium nitride high electron mobility transistor …
FIG. 3 illustrates a schematic sectional structural diagram after a second step of the formation process of the gallium nitride high electron mobility …
FIG. 4 illustrates a schematic sectional structural diagram after a third step of the formation process of the gallium nitride high electron mobility …
FIG. 5 illustrates a schematic sectional structural diagram after a fourth step of the formation process of the gallium nitride high electron mobility …
FIG. 6, the high electron mobility transistor includes: a substrate 200; a channel layer 303 disposed on the substrate 200; a first barrier layer 305 disposed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
buffer_layer_resistivity | >1e6 ohms·cm | GaN |
Thickness | 1–100 nm | — |
Temperature | 1100–1150 °C | — |
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GALLIUM NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR EPITAXIAL WAFER WITH AN INGAN/GAN CAP LAYER COMPRISING FIRST SUBLAYERS DOPED WITH A MAIN DOPING ELEMENT AND SECOND SUBLAYERS DOPED WITH THE FIRST DOPING ELEMENT AND AN AUXILIARY DOPING ELEMENT, AND PREPARATION METHOD THEREFOR
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, a schematic flowchart of a formation method for a gallium nitride high electron mobility transistor having a high breakdown voltage according to a one …
FIG. 2 illustrates a schematic sectional structural diagram after a first step of a formation process of the gallium nitride high electron mobility transistor …
FIG. 3 illustrates a schematic sectional structural diagram after a second step of the formation process of the gallium nitride high electron mobility …
FIG. 4 illustrates a schematic sectional structural diagram after a third step of the formation process of the gallium nitride high electron mobility …
FIG. 5 illustrates a schematic sectional structural diagram after a fourth step of the formation process of the gallium nitride high electron mobility …
FIG. 6, the high electron mobility transistor includes: a substrate 200; a channel layer 303 disposed on the substrate 200; a first barrier layer 305 disposed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride high electron mobility transistor, comprising: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source, and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; [[and]] a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas; and a nucleation layer and a buffer layer disposed on the nucleation layer, wherein the nucleation layer and the buffer layer are disposed between the substrate and the gallium nitride channel layer, and wherein the buffer layer has a resistivity to prevent electrons in the gallium nitride channel layer from leaking to the buffer layer. Currently amended
The gallium nitride high electron mobility transistor according to claim 1, wherein the second barrier layer comprises: a first sub-layer disposed on the surface of the first barrier layer, a second sub-layer disposed on a surface of the second sub-layer and a third sub- layer disposed on a surface of the second sub-layer, the first sub-layer and the second sub-layer forming a heterojunction, and the third sub-layer being P-doped. Original
The gallium nitride high electron mobility transistor according to claim 1, wherein the buffer layer has the resistivity over 10 6 ohms cm. New
Canceled
The gallium nitride high electron mobility transistor according to claim [[3]] _, wherein an insert layer is further defined between the gallium channel layer and the first barrier layer. Currently amended
The gallium nitride high electron mobility transistor according to claim 4, wherein the first sub-layer is made of aluminum nitride, gallium nitride or aluminum gallium nitride; the second sub-layer is made of gallium nitride, aluminum nitride or aluminum gallium nitride; the third sublayer is made from P-type gallium nitride, P-type aluminum nitride or P- type aluminum gallium nitride; the nucleation layer is made of a gallium nitride, aluminum nitride or aluminum gallium nitride; the buffer layer is made of gallium nitride; the insert layer is made of aluminum nitride; and the first barrier layer is made of aluminum gallium nitride or indium aluminum nitride. Original
A formation method for a gallium nitride high electron mobility transistor, comprising: providing a substrate; forming a gallium channel layer and a first barrier layer disposed on the gallium channel layer in sequence on the substrate; forming a second barrier layer on a surface of the first barrier layer, the second barrier layer being configured to generate two-dimensional hole gas; etching the second barrier layer to expose a part of the surface of the first barrier layer; [[and]] forming a source, a drain, and a gate respectively on the surface of the first barrier layer, the gate being positioned between the source and the second barrier layer, and a side wall on one side of the gate being connected to a side wall of the second barrier layer; and forming a nucleation layer and a buffer layer disposed on a surface of the nucleation layer, wherein the nucleation layer and the buffer layer are disposed between the substrate and the gallium channel layer, and wherein the buffer layer has a resistivity to prevent electrons in the gallium channel layer from leaking to the buffer layer. Currently amended
The formation method for a gallium nitride high electron mobility transistor according to claim 6, wherein the second barrier layer comprises a first sub-layer disposed on the surface of the first barrier layer, a second sub-layer disposed on a surface of the second sub-layer and a third sublayer disposed on a surface of the second sub-layer, the first sub-layer and the second sub-layer forming a heterojunction, and the third sub-layer being P-doped. Original
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride high electron mobility transistor
Materials described outside the worked examples.
gallium nitride channel layer
GaN
first barrier layer
second barrier layer
insert layer
AlN
aluminum gallium nitride (first sub-layer option)
AlGaN
P-type gallium nitride (third sub-layer option)
p-GaN
P-type aluminum nitride (third sub-layer option)
p-AlN
P-type aluminum gallium nitride (third sub-layer option)
p-AlGaN
indium aluminum nitride (first barrier layer option)
InAlN
substrate
nucleation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, a schematic flowchart of a formation method for a gallium nitride high electron mobility transistor having a high breakdown voltage according to a one …
FIG. 2 illustrates a schematic sectional structural diagram after a first step of a formation process of the gallium nitride high electron mobility transistor …
FIG. 3 illustrates a schematic sectional structural diagram after a second step of the formation process of the gallium nitride high electron mobility …
FIG. 4 illustrates a schematic sectional structural diagram after a third step of the formation process of the gallium nitride high electron mobility …
FIG. 5 illustrates a schematic sectional structural diagram after a fourth step of the formation process of the gallium nitride high electron mobility …
FIG. 6, the high electron mobility transistor includes: a substrate 200; a channel layer 303 disposed on the substrate 200; a first barrier layer 305 disposed …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
buffer_layer_resistivity | >1e6 ohms·cm | GaN |
Thickness | 1–100 nm | — |
Temperature | 1100–1150 °C | — |
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