Patent
US 10,236,178GALLIUM NITRIDE NANOWIRE BASED ELECTRONICS
Jonas OHLSSON
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,236,178Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 0 a-c are SEM-images illustrating the result of growth conditions giving nanowires. [0022]
FIG. 2a illustrates schematically the method according to the embodiments of the invention and
FIGS. 3a-b are SEM images of nanowire structures according to the embodiments of the invention. [0015]
FIGS. 4, 12 a-d and 13 a-d illustrate schematically a method of making a device according to the embodiments of the invention. [0016]
FIGS. 5a-b illustrate schematically embodiments of a nanostructured LED device according to the embodiments of the invention. [0017]
FIG. 6 illustrates schematically a nanowire growth apparatus according to the embodiments of the invention. [0018]
FIGS. 7a-b are SEM-images illustrating the result of growth conditions not giving nanowires. [0019]
FIGS. 8a-b are SEM-images illustrating the result of growth conditions wherein nanowires are starting to form. [0020]
FIGS. 9a-b are SEM-images illustrating the result of growth conditions giving nanowires. [0021]
FIGS. 10a-lOc, wherein (a) is a top-view; (b) and (c) are 450 tilted. Although there are some crystallites larger than 100 nm, but most of the openings evolve …
FIGS. 12a-d are schematic diagrams illustrating a method of making a pyramidal volume element with an additional single crystal semiconductor epitaxial layer …
FIGS. 13a-d are schematic diagrams illustrating a method of making a transistor according to an embodiment. [0025]
FIGS. 14a-c are schematic diagrams of a) a Schottky diode, b) a p-n diode and c) a MOSFET that can be made according to the embodiments of the invention. …
FIGS. 15A-15 E illustrate an embodiment of a nanowire enabled power wafer according to an embodiment. [0029]
FIGS. 16A-16B illustrate a prior art planar high electron mobility transistor (HEMT). [0030]
FIGS. 17A-17B illustrate a HEMT according to an embodiment. [0031]
FIGS. 18A-18F illustrate alternative HEMT embodiments. [0032]
FIG. 19C illustrates an embodiment with HEMTs in a parallel and cascade configuration. [0033]
FIGS. 20A-20C illustrate alternative embodiments in which multiple HEMTs are connected with a common gate line. [0034]
FIGS. 21A-21B illustrate an embodiment in which multiple HEMTs are configured with common gate lines, common source lines and common drain lines. [0035] Figures …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A method of fabricating a nitride semiconductor wafer comprising the steps of: forming nanowires without threading dislocations on a substrate surface; forming nitride semiconductor nanostructures without threading dislocations by growing respective nitride semiconductor volume elements from the nanowires; planarizing the nitride semiconductor volume elements of the nitride semiconductor nanostructures to form separated individual mesas having exposed planar c-plane upper surfaces; and epitaxially growing a respective planar stoichiometric nitride semiconductor layer on the planar c-plane upper surfaces of the separated individual mesas, such that at least 90 % of the planar nitride semiconductor layers have no threading dislocations and a flat c-plane [[-]] surface. Currently amended
The method of claim 2, wherein the step of forming nitride semiconductor nanostructures comprises: providing a growth mask with openings on the substrate surface; and forming the nanowires by selectively growing an array of strain-relaxed nitride semiconductor nanowires from the apertures, wherein threading dislocations are rejected from the nanowires in an early stage of nanowire growth. Currently amended
The method according to claim 2, wherein the step of planarization is made through temperature assisted anisotropic etching. Previously presented
Previously Presented) The method according to claim 2, wherein the step of planarization is made in situ.
The method according to claim 2, wherein 90-99% of the at least planar stoichiometric nitride semiconductor layers do not have threading dislocations. Previously presented
The method of claim 2, wherein at least a part of the substrate is removed and replaced by a handle substrate. Previously presented
The method of claim 2, wherein the respective nitride semiconductor volume elements are grown from a side of the nanowires. New
The method of claim 2, wherein the planar stoichiometric nitride semiconductor layers are also grown on pyramidal side facets of the separated individual mesas. New
Layer stacks claimed or described, ordered top of device to substrate.
nitride semiconductor wafer with dislocation-free mesas
Materials described outside the worked examples.
nitride semiconductor nanowire
planar stoichiometric nitride semiconductor layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 0 a-c are SEM-images illustrating the result of growth conditions giving nanowires. [0022]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–500 nm | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR HAVING HIGH BREAKDOWN VOLTAGE AND FORMATION METHOD THEREFOR
GALLIUM NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR EPITAXIAL WAFER WITH AN INGAN/GAN CAP LAYER COMPRISING FIRST SUBLAYERS DOPED WITH A MAIN DOPING ELEMENT AND SECOND SUBLAYERS DOPED WITH THE FIRST DOPING ELEMENT AND AN AUXILIARY DOPING ELEMENT, AND PREPARATION METHOD THEREFOR
Patent
Atlas literature
Patent
US 10,236,178Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 0 a-c are SEM-images illustrating the result of growth conditions giving nanowires. [0022]
FIG. 2a illustrates schematically the method according to the embodiments of the invention and
FIGS. 3a-b are SEM images of nanowire structures according to the embodiments of the invention. [0015]
FIGS. 4, 12 a-d and 13 a-d illustrate schematically a method of making a device according to the embodiments of the invention. [0016]
FIGS. 5a-b illustrate schematically embodiments of a nanostructured LED device according to the embodiments of the invention. [0017]
FIG. 6 illustrates schematically a nanowire growth apparatus according to the embodiments of the invention. [0018]
FIGS. 7a-b are SEM-images illustrating the result of growth conditions not giving nanowires. [0019]
FIGS. 8a-b are SEM-images illustrating the result of growth conditions wherein nanowires are starting to form. [0020]
FIGS. 9a-b are SEM-images illustrating the result of growth conditions giving nanowires. [0021]
FIGS. 10a-lOc, wherein (a) is a top-view; (b) and (c) are 450 tilted. Although there are some crystallites larger than 100 nm, but most of the openings evolve …
FIGS. 12a-d are schematic diagrams illustrating a method of making a pyramidal volume element with an additional single crystal semiconductor epitaxial layer …
FIGS. 13a-d are schematic diagrams illustrating a method of making a transistor according to an embodiment. [0025]
FIGS. 14a-c are schematic diagrams of a) a Schottky diode, b) a p-n diode and c) a MOSFET that can be made according to the embodiments of the invention. …
FIGS. 15A-15 E illustrate an embodiment of a nanowire enabled power wafer according to an embodiment. [0029]
FIGS. 16A-16B illustrate a prior art planar high electron mobility transistor (HEMT). [0030]
FIGS. 17A-17B illustrate a HEMT according to an embodiment. [0031]
FIGS. 18A-18F illustrate alternative HEMT embodiments. [0032]
FIG. 19C illustrates an embodiment with HEMTs in a parallel and cascade configuration. [0033]
FIGS. 20A-20C illustrate alternative embodiments in which multiple HEMTs are connected with a common gate line. [0034]
FIGS. 21A-21B illustrate an embodiment in which multiple HEMTs are configured with common gate lines, common source lines and common drain lines. [0035] Figures …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A method of fabricating a nitride semiconductor wafer comprising the steps of: forming nanowires without threading dislocations on a substrate surface; forming nitride semiconductor nanostructures without threading dislocations by growing respective nitride semiconductor volume elements from the nanowires; planarizing the nitride semiconductor volume elements of the nitride semiconductor nanostructures to form separated individual mesas having exposed planar c-plane upper surfaces; and epitaxially growing a respective planar stoichiometric nitride semiconductor layer on the planar c-plane upper surfaces of the separated individual mesas, such that at least 90 % of the planar nitride semiconductor layers have no threading dislocations and a flat c-plane [[-]] surface. Currently amended
The method of claim 2, wherein the step of forming nitride semiconductor nanostructures comprises: providing a growth mask with openings on the substrate surface; and forming the nanowires by selectively growing an array of strain-relaxed nitride semiconductor nanowires from the apertures, wherein threading dislocations are rejected from the nanowires in an early stage of nanowire growth. Currently amended
The method according to claim 2, wherein the step of planarization is made through temperature assisted anisotropic etching. Previously presented
Previously Presented) The method according to claim 2, wherein the step of planarization is made in situ.
The method according to claim 2, wherein 90-99% of the at least planar stoichiometric nitride semiconductor layers do not have threading dislocations. Previously presented
The method of claim 2, wherein at least a part of the substrate is removed and replaced by a handle substrate. Previously presented
The method of claim 2, wherein the respective nitride semiconductor volume elements are grown from a side of the nanowires. New
The method of claim 2, wherein the planar stoichiometric nitride semiconductor layers are also grown on pyramidal side facets of the separated individual mesas. New
Layer stacks claimed or described, ordered top of device to substrate.
nitride semiconductor wafer with dislocation-free mesas
Materials described outside the worked examples.
nitride semiconductor nanowire
planar stoichiometric nitride semiconductor layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 0 a-c are SEM-images illustrating the result of growth conditions giving nanowires. [0022]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–500 nm | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR HAVING HIGH BREAKDOWN VOLTAGE AND FORMATION METHOD THEREFOR
GALLIUM NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR EPITAXIAL WAFER WITH AN INGAN/GAN CAP LAYER COMPRISING FIRST SUBLAYERS DOPED WITH A MAIN DOPING ELEMENT AND SECOND SUBLAYERS DOPED WITH THE FIRST DOPING ELEMENT AND AN AUXILIARY DOPING ELEMENT, AND PREPARATION METHOD THEREFOR
Patent
Atlas literature
Patent
US 10,236,178Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 0 a-c are SEM-images illustrating the result of growth conditions giving nanowires. [0022]
FIG. 2a illustrates schematically the method according to the embodiments of the invention and
FIGS. 3a-b are SEM images of nanowire structures according to the embodiments of the invention. [0015]
FIGS. 4, 12 a-d and 13 a-d illustrate schematically a method of making a device according to the embodiments of the invention. [0016]
FIGS. 5a-b illustrate schematically embodiments of a nanostructured LED device according to the embodiments of the invention. [0017]
FIG. 6 illustrates schematically a nanowire growth apparatus according to the embodiments of the invention. [0018]
FIGS. 7a-b are SEM-images illustrating the result of growth conditions not giving nanowires. [0019]
FIGS. 8a-b are SEM-images illustrating the result of growth conditions wherein nanowires are starting to form. [0020]
FIGS. 9a-b are SEM-images illustrating the result of growth conditions giving nanowires. [0021]
FIGS. 10a-lOc, wherein (a) is a top-view; (b) and (c) are 450 tilted. Although there are some crystallites larger than 100 nm, but most of the openings evolve …
FIGS. 12a-d are schematic diagrams illustrating a method of making a pyramidal volume element with an additional single crystal semiconductor epitaxial layer …
FIGS. 13a-d are schematic diagrams illustrating a method of making a transistor according to an embodiment. [0025]
FIGS. 14a-c are schematic diagrams of a) a Schottky diode, b) a p-n diode and c) a MOSFET that can be made according to the embodiments of the invention. …
FIGS. 15A-15 E illustrate an embodiment of a nanowire enabled power wafer according to an embodiment. [0029]
FIGS. 16A-16B illustrate a prior art planar high electron mobility transistor (HEMT). [0030]
FIGS. 17A-17B illustrate a HEMT according to an embodiment. [0031]
FIGS. 18A-18F illustrate alternative HEMT embodiments. [0032]
FIG. 19C illustrates an embodiment with HEMTs in a parallel and cascade configuration. [0033]
FIGS. 20A-20C illustrate alternative embodiments in which multiple HEMTs are connected with a common gate line. [0034]
FIGS. 21A-21B illustrate an embodiment in which multiple HEMTs are configured with common gate lines, common source lines and common drain lines. [0035] Figures …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A method of fabricating a nitride semiconductor wafer comprising the steps of: forming nanowires without threading dislocations on a substrate surface; forming nitride semiconductor nanostructures without threading dislocations by growing respective nitride semiconductor volume elements from the nanowires; planarizing the nitride semiconductor volume elements of the nitride semiconductor nanostructures to form separated individual mesas having exposed planar c-plane upper surfaces; and epitaxially growing a respective planar stoichiometric nitride semiconductor layer on the planar c-plane upper surfaces of the separated individual mesas, such that at least 90 % of the planar nitride semiconductor layers have no threading dislocations and a flat c-plane [[-]] surface. Currently amended
The method of claim 2, wherein the step of forming nitride semiconductor nanostructures comprises: providing a growth mask with openings on the substrate surface; and forming the nanowires by selectively growing an array of strain-relaxed nitride semiconductor nanowires from the apertures, wherein threading dislocations are rejected from the nanowires in an early stage of nanowire growth. Currently amended
The method according to claim 2, wherein the step of planarization is made through temperature assisted anisotropic etching. Previously presented
Previously Presented) The method according to claim 2, wherein the step of planarization is made in situ.
The method according to claim 2, wherein 90-99% of the at least planar stoichiometric nitride semiconductor layers do not have threading dislocations. Previously presented
The method of claim 2, wherein at least a part of the substrate is removed and replaced by a handle substrate. Previously presented
The method of claim 2, wherein the respective nitride semiconductor volume elements are grown from a side of the nanowires. New
The method of claim 2, wherein the planar stoichiometric nitride semiconductor layers are also grown on pyramidal side facets of the separated individual mesas. New
Layer stacks claimed or described, ordered top of device to substrate.
nitride semiconductor wafer with dislocation-free mesas
Materials described outside the worked examples.
nitride semiconductor nanowire
planar stoichiometric nitride semiconductor layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 0 a-c are SEM-images illustrating the result of growth conditions giving nanowires. [0022]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–500 nm | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR HAVING HIGH BREAKDOWN VOLTAGE AND FORMATION METHOD THEREFOR
GALLIUM NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR EPITAXIAL WAFER WITH AN INGAN/GAN CAP LAYER COMPRISING FIRST SUBLAYERS DOPED WITH A MAIN DOPING ELEMENT AND SECOND SUBLAYERS DOPED WITH THE FIRST DOPING ELEMENT AND AN AUXILIARY DOPING ELEMENT, AND PREPARATION METHOD THEREFOR
Patent
Atlas literature
Patent
US 10,236,178Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 0 a-c are SEM-images illustrating the result of growth conditions giving nanowires. [0022]
FIG. 2a illustrates schematically the method according to the embodiments of the invention and
FIGS. 3a-b are SEM images of nanowire structures according to the embodiments of the invention. [0015]
FIGS. 4, 12 a-d and 13 a-d illustrate schematically a method of making a device according to the embodiments of the invention. [0016]
FIGS. 5a-b illustrate schematically embodiments of a nanostructured LED device according to the embodiments of the invention. [0017]
FIG. 6 illustrates schematically a nanowire growth apparatus according to the embodiments of the invention. [0018]
FIGS. 7a-b are SEM-images illustrating the result of growth conditions not giving nanowires. [0019]
FIGS. 8a-b are SEM-images illustrating the result of growth conditions wherein nanowires are starting to form. [0020]
FIGS. 9a-b are SEM-images illustrating the result of growth conditions giving nanowires. [0021]
FIGS. 10a-lOc, wherein (a) is a top-view; (b) and (c) are 450 tilted. Although there are some crystallites larger than 100 nm, but most of the openings evolve …
FIGS. 12a-d are schematic diagrams illustrating a method of making a pyramidal volume element with an additional single crystal semiconductor epitaxial layer …
FIGS. 13a-d are schematic diagrams illustrating a method of making a transistor according to an embodiment. [0025]
FIGS. 14a-c are schematic diagrams of a) a Schottky diode, b) a p-n diode and c) a MOSFET that can be made according to the embodiments of the invention. …
FIGS. 15A-15 E illustrate an embodiment of a nanowire enabled power wafer according to an embodiment. [0029]
FIGS. 16A-16B illustrate a prior art planar high electron mobility transistor (HEMT). [0030]
FIGS. 17A-17B illustrate a HEMT according to an embodiment. [0031]
FIGS. 18A-18F illustrate alternative HEMT embodiments. [0032]
FIG. 19C illustrates an embodiment with HEMTs in a parallel and cascade configuration. [0033]
FIGS. 20A-20C illustrate alternative embodiments in which multiple HEMTs are connected with a common gate line. [0034]
FIGS. 21A-21B illustrate an embodiment in which multiple HEMTs are configured with common gate lines, common source lines and common drain lines. [0035] Figures …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A method of fabricating a nitride semiconductor wafer comprising the steps of: forming nanowires without threading dislocations on a substrate surface; forming nitride semiconductor nanostructures without threading dislocations by growing respective nitride semiconductor volume elements from the nanowires; planarizing the nitride semiconductor volume elements of the nitride semiconductor nanostructures to form separated individual mesas having exposed planar c-plane upper surfaces; and epitaxially growing a respective planar stoichiometric nitride semiconductor layer on the planar c-plane upper surfaces of the separated individual mesas, such that at least 90 % of the planar nitride semiconductor layers have no threading dislocations and a flat c-plane [[-]] surface. Currently amended
The method of claim 2, wherein the step of forming nitride semiconductor nanostructures comprises: providing a growth mask with openings on the substrate surface; and forming the nanowires by selectively growing an array of strain-relaxed nitride semiconductor nanowires from the apertures, wherein threading dislocations are rejected from the nanowires in an early stage of nanowire growth. Currently amended
The method according to claim 2, wherein the step of planarization is made through temperature assisted anisotropic etching. Previously presented
Previously Presented) The method according to claim 2, wherein the step of planarization is made in situ.
The method according to claim 2, wherein 90-99% of the at least planar stoichiometric nitride semiconductor layers do not have threading dislocations. Previously presented
The method of claim 2, wherein at least a part of the substrate is removed and replaced by a handle substrate. Previously presented
The method of claim 2, wherein the respective nitride semiconductor volume elements are grown from a side of the nanowires. New
The method of claim 2, wherein the planar stoichiometric nitride semiconductor layers are also grown on pyramidal side facets of the separated individual mesas. New
Layer stacks claimed or described, ordered top of device to substrate.
nitride semiconductor wafer with dislocation-free mesas
Materials described outside the worked examples.
nitride semiconductor nanowire
planar stoichiometric nitride semiconductor layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 0 a-c are SEM-images illustrating the result of growth conditions giving nanowires. [0022]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–500 nm | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR HAVING HIGH BREAKDOWN VOLTAGE AND FORMATION METHOD THEREFOR
GALLIUM NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR EPITAXIAL WAFER WITH AN INGAN/GAN CAP LAYER COMPRISING FIRST SUBLAYERS DOPED WITH A MAIN DOPING ELEMENT AND SECOND SUBLAYERS DOPED WITH THE FIRST DOPING ELEMENT AND AN AUXILIARY DOPING ELEMENT, AND PREPARATION METHOD THEREFOR
III-nitride semiconductor device (diode/transistor)
GaN
buffer layer
AlGaN
AlN
Al₂O₃
graphene
diamond
aluminum
Al
copper
Cu
SiNx growth mask
SiNx
SiOx growth mask
SiOx
FIGS. 3a-b are SEM images of nanowire structures according to the embodiments of the invention. [0015]
FIGS. 7a-b are SEM-images illustrating the result of growth conditions not giving nanowires. [0019]
FIGS. 8a-b are SEM-images illustrating the result of growth conditions wherein nanowires are starting to form. [0020]
FIGS. 9a-b are SEM-images illustrating the result of growth conditions giving nanowires. [0021]
FIGS. 13a-d are schematic diagrams illustrating a method of making a transistor according to an embodiment. [0025]
FIGS. 16A-16B illustrate a prior art planar high electron mobility transistor (HEMT). [0030]
| — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 2000 cm | — |
III-nitride semiconductor device (diode/transistor)
GaN
buffer layer
AlGaN
AlN
Al₂O₃
graphene
diamond
aluminum
Al
copper
Cu
SiNx growth mask
SiNx
SiOx growth mask
SiOx
FIGS. 3a-b are SEM images of nanowire structures according to the embodiments of the invention. [0015]
FIGS. 7a-b are SEM-images illustrating the result of growth conditions not giving nanowires. [0019]
FIGS. 8a-b are SEM-images illustrating the result of growth conditions wherein nanowires are starting to form. [0020]
FIGS. 9a-b are SEM-images illustrating the result of growth conditions giving nanowires. [0021]
FIGS. 13a-d are schematic diagrams illustrating a method of making a transistor according to an embodiment. [0025]
FIGS. 16A-16B illustrate a prior art planar high electron mobility transistor (HEMT). [0030]
| — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 2000 cm | — |
III-nitride semiconductor device (diode/transistor)
GaN
buffer layer
AlGaN
AlN
Al₂O₃
graphene
diamond
aluminum
Al
copper
Cu
SiNx growth mask
SiNx
SiOx growth mask
SiOx
FIGS. 3a-b are SEM images of nanowire structures according to the embodiments of the invention. [0015]
FIGS. 7a-b are SEM-images illustrating the result of growth conditions not giving nanowires. [0019]
FIGS. 8a-b are SEM-images illustrating the result of growth conditions wherein nanowires are starting to form. [0020]
FIGS. 9a-b are SEM-images illustrating the result of growth conditions giving nanowires. [0021]
FIGS. 13a-d are schematic diagrams illustrating a method of making a transistor according to an embodiment. [0025]
FIGS. 16A-16B illustrate a prior art planar high electron mobility transistor (HEMT). [0030]
| — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 2000 cm | — |
III-nitride semiconductor device (diode/transistor)
GaN
buffer layer
AlGaN
AlN
Al₂O₃
graphene
diamond
aluminum
Al
copper
Cu
SiNx growth mask
SiNx
SiOx growth mask
SiOx
FIGS. 3a-b are SEM images of nanowire structures according to the embodiments of the invention. [0015]
FIGS. 7a-b are SEM-images illustrating the result of growth conditions not giving nanowires. [0019]
FIGS. 8a-b are SEM-images illustrating the result of growth conditions wherein nanowires are starting to form. [0020]
FIGS. 9a-b are SEM-images illustrating the result of growth conditions giving nanowires. [0021]
FIGS. 13a-d are schematic diagrams illustrating a method of making a transistor according to an embodiment. [0025]
FIGS. 16A-16B illustrate a prior art planar high electron mobility transistor (HEMT). [0030]
| — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 2000 cm | — |