Patent
US 9,368,584GALLIUM NITRIDE POWER SEMICONDUCTOR DEVICE HAVING A VERTICAL STRUCTURE
Max SK Chen
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
Patent
US 9,368,584Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an example of a conventional GaN-based diode. [0008]
FIG. 2. [0010] FIG s. 8 and 9 show examples of a GaN-based metal-insulator-semiconductor (MIS) transistor constructed in accordance with the present invention. …
FIG. 3). The substrate 210 is a low resistivity substrate suitable for the deposition of GaN. Illustrative examples of suitable substrates may be formed from …
FIG. 4). The two- dimensional conduction channel 225, which is a thin, high mobility channel, confines carriers to an interface region between the G aN epi …
FIG. 5). For example, a photolithographic technique may be employed in which a photoresist is coated on an oxide layer that is formed on the barrier layer 235 …
FIG. 6) may be formed by sputtering, deposition, or vacuum evaporation of a low-resistivity conductive metal and patterned using lithography and subsequent …
FIG. 7 shows the final device structure after forming the anode 250 and cathode 260. The anode 250 may be formed by first profile shaping the passivation layer …
FIG. 9, the gate electrodes 355 are exposed. [0025]
FIG. 10 demonstrates a high-electron-mobility-transistor (HEM T) 400 that includes a substrate 410, a GaN buffer layer 420, a first active layer such as a GaN …
FIG. 11, the gate electrodes 455 are exposed. [0026] Among its other advantages, the power semiconductor devices described above have a reduced total …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate having first and second sides; a first active layer disposed over the first side of the substrate; a second active layer disposed on the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer; at least one trench extending through the first and second active layers and the two-dimensional electron gas layer and into the substrate; a conductive material lining the trench; a first electrode disposed on the second active layer; and a second electrode disposed on the second side of the substrate; a third electrode disposed on the second active layer, said first, second and third electrodes being source, drain and gate electrodes, respectively.
The semiconductor device of claim 1, wherein the at least one trench comprises a pair of trenches extending through the first and second active layers and the two- dimensional electron gas layer and into the substrate, each of the trenches being lined with a conductive material.
The semiconductor device of claim 1, wherein the first active layer includes an epitaxial layer.
The semiconductor device of claim 1, wherein the first electrode is a Schottky contact.
The semiconductor device of claim 1, wherein the first active layer comprises a group III nitride semiconductor material.
The semiconductor device of claim 1, wherein the second active layer comprises a group III nitride semiconductor material.
The semiconductor device of claim 1, further comprising a dielectric layer disposed between each of the third electrodes and the second active layer.
The semiconductor device of claim 1, wherein the third electrodes are Schottky electrodes.
The semiconductor device of claim 1, further comprising a passivation material filling the trench.
canceled
canceled
canceled
A method of forming a semiconductor device, comprising: forming a first active layer on a substrate; forming a second active layer over the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer; 3 forming at least one trench that extends through the first and second active layers and the two- dimensional electron gas layer and into the substrate; lining the trench with a conductive material; filling the trench with a passivation material; forming a first electrode on the second active layer; and forming a second electrode on a bottom. 4
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based power semiconductor device (diode/transistor)
Materials described outside the worked examples.
first active layer (group III nitride/GaN epitaxial layer)
second active layer (group III nitride, higher bandgap)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2. [0010] FIG s. 8 and 9 show examples of a GaN-based metal-insulator-semiconductor (MIS) transistor constructed in accordance with the present invention. …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,368,584Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an example of a conventional GaN-based diode. [0008]
FIG. 2. [0010] FIG s. 8 and 9 show examples of a GaN-based metal-insulator-semiconductor (MIS) transistor constructed in accordance with the present invention. …
FIG. 3). The substrate 210 is a low resistivity substrate suitable for the deposition of GaN. Illustrative examples of suitable substrates may be formed from …
FIG. 4). The two- dimensional conduction channel 225, which is a thin, high mobility channel, confines carriers to an interface region between the G aN epi …
FIG. 5). For example, a photolithographic technique may be employed in which a photoresist is coated on an oxide layer that is formed on the barrier layer 235 …
FIG. 6) may be formed by sputtering, deposition, or vacuum evaporation of a low-resistivity conductive metal and patterned using lithography and subsequent …
FIG. 7 shows the final device structure after forming the anode 250 and cathode 260. The anode 250 may be formed by first profile shaping the passivation layer …
FIG. 9, the gate electrodes 355 are exposed. [0025]
FIG. 10 demonstrates a high-electron-mobility-transistor (HEM T) 400 that includes a substrate 410, a GaN buffer layer 420, a first active layer such as a GaN …
FIG. 11, the gate electrodes 455 are exposed. [0026] Among its other advantages, the power semiconductor devices described above have a reduced total …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate having first and second sides; a first active layer disposed over the first side of the substrate; a second active layer disposed on the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer; at least one trench extending through the first and second active layers and the two-dimensional electron gas layer and into the substrate; a conductive material lining the trench; a first electrode disposed on the second active layer; and a second electrode disposed on the second side of the substrate; a third electrode disposed on the second active layer, said first, second and third electrodes being source, drain and gate electrodes, respectively.
The semiconductor device of claim 1, wherein the at least one trench comprises a pair of trenches extending through the first and second active layers and the two- dimensional electron gas layer and into the substrate, each of the trenches being lined with a conductive material.
The semiconductor device of claim 1, wherein the first active layer includes an epitaxial layer.
The semiconductor device of claim 1, wherein the first electrode is a Schottky contact.
The semiconductor device of claim 1, wherein the first active layer comprises a group III nitride semiconductor material.
The semiconductor device of claim 1, wherein the second active layer comprises a group III nitride semiconductor material.
The semiconductor device of claim 1, further comprising a dielectric layer disposed between each of the third electrodes and the second active layer.
The semiconductor device of claim 1, wherein the third electrodes are Schottky electrodes.
The semiconductor device of claim 1, further comprising a passivation material filling the trench.
canceled
canceled
canceled
A method of forming a semiconductor device, comprising: forming a first active layer on a substrate; forming a second active layer over the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer; 3 forming at least one trench that extends through the first and second active layers and the two- dimensional electron gas layer and into the substrate; lining the trench with a conductive material; filling the trench with a passivation material; forming a first electrode on the second active layer; and forming a second electrode on a bottom. 4
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based power semiconductor device (diode/transistor)
Materials described outside the worked examples.
first active layer (group III nitride/GaN epitaxial layer)
second active layer (group III nitride, higher bandgap)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2. [0010] FIG s. 8 and 9 show examples of a GaN-based metal-insulator-semiconductor (MIS) transistor constructed in accordance with the present invention. …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,368,584Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an example of a conventional GaN-based diode. [0008]
FIG. 2. [0010] FIG s. 8 and 9 show examples of a GaN-based metal-insulator-semiconductor (MIS) transistor constructed in accordance with the present invention. …
FIG. 3). The substrate 210 is a low resistivity substrate suitable for the deposition of GaN. Illustrative examples of suitable substrates may be formed from …
FIG. 4). The two- dimensional conduction channel 225, which is a thin, high mobility channel, confines carriers to an interface region between the G aN epi …
FIG. 5). For example, a photolithographic technique may be employed in which a photoresist is coated on an oxide layer that is formed on the barrier layer 235 …
FIG. 6) may be formed by sputtering, deposition, or vacuum evaporation of a low-resistivity conductive metal and patterned using lithography and subsequent …
FIG. 7 shows the final device structure after forming the anode 250 and cathode 260. The anode 250 may be formed by first profile shaping the passivation layer …
FIG. 9, the gate electrodes 355 are exposed. [0025]
FIG. 10 demonstrates a high-electron-mobility-transistor (HEM T) 400 that includes a substrate 410, a GaN buffer layer 420, a first active layer such as a GaN …
FIG. 11, the gate electrodes 455 are exposed. [0026] Among its other advantages, the power semiconductor devices described above have a reduced total …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate having first and second sides; a first active layer disposed over the first side of the substrate; a second active layer disposed on the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer; at least one trench extending through the first and second active layers and the two-dimensional electron gas layer and into the substrate; a conductive material lining the trench; a first electrode disposed on the second active layer; and a second electrode disposed on the second side of the substrate; a third electrode disposed on the second active layer, said first, second and third electrodes being source, drain and gate electrodes, respectively.
The semiconductor device of claim 1, wherein the at least one trench comprises a pair of trenches extending through the first and second active layers and the two- dimensional electron gas layer and into the substrate, each of the trenches being lined with a conductive material.
The semiconductor device of claim 1, wherein the first active layer includes an epitaxial layer.
The semiconductor device of claim 1, wherein the first electrode is a Schottky contact.
The semiconductor device of claim 1, wherein the first active layer comprises a group III nitride semiconductor material.
The semiconductor device of claim 1, wherein the second active layer comprises a group III nitride semiconductor material.
The semiconductor device of claim 1, further comprising a dielectric layer disposed between each of the third electrodes and the second active layer.
The semiconductor device of claim 1, wherein the third electrodes are Schottky electrodes.
The semiconductor device of claim 1, further comprising a passivation material filling the trench.
canceled
canceled
canceled
A method of forming a semiconductor device, comprising: forming a first active layer on a substrate; forming a second active layer over the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer; 3 forming at least one trench that extends through the first and second active layers and the two- dimensional electron gas layer and into the substrate; lining the trench with a conductive material; filling the trench with a passivation material; forming a first electrode on the second active layer; and forming a second electrode on a bottom. 4
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based power semiconductor device (diode/transistor)
Materials described outside the worked examples.
first active layer (group III nitride/GaN epitaxial layer)
second active layer (group III nitride, higher bandgap)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2. [0010] FIG s. 8 and 9 show examples of a GaN-based metal-insulator-semiconductor (MIS) transistor constructed in accordance with the present invention. …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,368,584Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an example of a conventional GaN-based diode. [0008]
FIG. 2. [0010] FIG s. 8 and 9 show examples of a GaN-based metal-insulator-semiconductor (MIS) transistor constructed in accordance with the present invention. …
FIG. 3). The substrate 210 is a low resistivity substrate suitable for the deposition of GaN. Illustrative examples of suitable substrates may be formed from …
FIG. 4). The two- dimensional conduction channel 225, which is a thin, high mobility channel, confines carriers to an interface region between the G aN epi …
FIG. 5). For example, a photolithographic technique may be employed in which a photoresist is coated on an oxide layer that is formed on the barrier layer 235 …
FIG. 6) may be formed by sputtering, deposition, or vacuum evaporation of a low-resistivity conductive metal and patterned using lithography and subsequent …
FIG. 7 shows the final device structure after forming the anode 250 and cathode 260. The anode 250 may be formed by first profile shaping the passivation layer …
FIG. 9, the gate electrodes 355 are exposed. [0025]
FIG. 10 demonstrates a high-electron-mobility-transistor (HEM T) 400 that includes a substrate 410, a GaN buffer layer 420, a first active layer such as a GaN …
FIG. 11, the gate electrodes 455 are exposed. [0026] Among its other advantages, the power semiconductor devices described above have a reduced total …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate having first and second sides; a first active layer disposed over the first side of the substrate; a second active layer disposed on the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer; at least one trench extending through the first and second active layers and the two-dimensional electron gas layer and into the substrate; a conductive material lining the trench; a first electrode disposed on the second active layer; and a second electrode disposed on the second side of the substrate; a third electrode disposed on the second active layer, said first, second and third electrodes being source, drain and gate electrodes, respectively.
The semiconductor device of claim 1, wherein the at least one trench comprises a pair of trenches extending through the first and second active layers and the two- dimensional electron gas layer and into the substrate, each of the trenches being lined with a conductive material.
The semiconductor device of claim 1, wherein the first active layer includes an epitaxial layer.
The semiconductor device of claim 1, wherein the first electrode is a Schottky contact.
The semiconductor device of claim 1, wherein the first active layer comprises a group III nitride semiconductor material.
The semiconductor device of claim 1, wherein the second active layer comprises a group III nitride semiconductor material.
The semiconductor device of claim 1, further comprising a dielectric layer disposed between each of the third electrodes and the second active layer.
The semiconductor device of claim 1, wherein the third electrodes are Schottky electrodes.
The semiconductor device of claim 1, further comprising a passivation material filling the trench.
canceled
canceled
canceled
A method of forming a semiconductor device, comprising: forming a first active layer on a substrate; forming a second active layer over the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer; 3 forming at least one trench that extends through the first and second active layers and the two- dimensional electron gas layer and into the substrate; lining the trench with a conductive material; filling the trench with a passivation material; forming a first electrode on the second active layer; and forming a second electrode on a bottom. 4
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based power semiconductor device (diode/transistor)
Materials described outside the worked examples.
first active layer (group III nitride/GaN epitaxial layer)
second active layer (group III nitride, higher bandgap)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2. [0010] FIG s. 8 and 9 show examples of a GaN-based metal-insulator-semiconductor (MIS) transistor constructed in accordance with the present invention. …
Related documents with shared materials, methods, properties, or citations.
conductive material lining trench
GaN
AlxGa₁-xN
passivation material
low resistivity substrate
trench conductive liner (Ti, Al, or Au)
FIG. 4). The two- dimensional conduction channel 225, which is a thin, high mobility channel, confines carriers to an interface region between the G aN epi …
FIG. 10 demonstrates a high-electron-mobility-transistor (HEM T) 400 that includes a substrate 410, a GaN buffer layer 420, a first active layer such as a GaN …
conductive material lining trench
GaN
AlxGa₁-xN
passivation material
low resistivity substrate
trench conductive liner (Ti, Al, or Au)
FIG. 4). The two- dimensional conduction channel 225, which is a thin, high mobility channel, confines carriers to an interface region between the G aN epi …
FIG. 10 demonstrates a high-electron-mobility-transistor (HEM T) 400 that includes a substrate 410, a GaN buffer layer 420, a first active layer such as a GaN …
conductive material lining trench
GaN
AlxGa₁-xN
passivation material
low resistivity substrate
trench conductive liner (Ti, Al, or Au)
FIG. 4). The two- dimensional conduction channel 225, which is a thin, high mobility channel, confines carriers to an interface region between the G aN epi …
FIG. 10 demonstrates a high-electron-mobility-transistor (HEM T) 400 that includes a substrate 410, a GaN buffer layer 420, a first active layer such as a GaN …
conductive material lining trench
GaN
AlxGa₁-xN
passivation material
low resistivity substrate
trench conductive liner (Ti, Al, or Au)
FIG. 4). The two- dimensional conduction channel 225, which is a thin, high mobility channel, confines carriers to an interface region between the G aN epi …
FIG. 10 demonstrates a high-electron-mobility-transistor (HEM T) 400 that includes a substrate 410, a GaN buffer layer 420, a first active layer such as a GaN …