Patent
Atlas literature
Patent
US 12,292,608 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1D-1G illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure for high speed optical …
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- 50 sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with an …
FIG. 6 illustrates cross-sectional views of various struc- 60 tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 65 multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a layer or substrate having a first region and a second region, the layer or substrate comprising gallium and nitrogen; a GaN-based device in or on the first region of the layer or substrate; a CMOS-based device over the second region of the layer or substrate; an interconnect structure over the GaN-based device and over the CMOS-based device, the interconnect struc-ture comprising conductive interconnects and vias in a dielectric layer; and a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the pho-tonics waveguide bonded to the dielectric layer of the interconnect structure.
The integrated circuit structure of claim 1, further comprising a tuning element over the interconnect structure, the tuning element comprising silicon, and the tuning ele-ment bonded to the dielectric layer of the interconnect structure.
The integrated circuit structure of claim 1, further comprising a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The integrated circuit structure of claim 1, further comprising a bonding layer between the photonics wave-guide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The integrated circuit structure of claim 1, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a layer or substrate having a first region and a second region, the layer or substrate comprising gallium and nitrogen; a GaN-based device in or on the first region of the layer or substrate; a CMOS-based device over the second region of the layer or substrate; an interconnect structure over the GaN-based device and over the CMOS-based device, the interconnect struc-ture comprising conductive interconnects and vias in a dielectric layer; and a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the pho-tonics waveguide bonded to the dielectric layer of the interconnect structure.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a tuning element over the interconnect structure, the tuning element compris-ing silicon, and the tuning element bonded to the dielectric layer of the interconnect structure.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a bonding layer between the photonics waveguide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The computing device of claim 6, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate.
A method of fabricating an integrated circuit structure, the method comprising: forming a layer or substrate having a first region and a second region, the layer or substrate comprising gal-lium and nitrogen; forming a GaN-based device in or on the first region of the layer or substrate; forming a CMOS-based device over the second region of the layer or substrate; forming an interconnect structure over the GaN-based device and over the CMOS-based device, the intercon-nect structure comprising conductive interconnects and vias in a dielectric layer; and forming a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.
The method of claim 15, wherein forming the pho-tonics waveguide over the interconnect structure comprises using a layer transfer process.
The method of claim 15, further comprising forming a tuning element over the interconnect structure, the tuning element comprising silicon, and the tuning element bonded to the dielectric layer of the interconnect structure.
The method of claim 15, further comprising forming a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The method of claim 15, further comprising forming a bonding layer between the photonics waveguide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The method of claim 15, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN integrated circuit structure with optical communication
Materials described outside the worked examples.
GaN layer or substrate
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,292,608 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1D-1G illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure for high speed optical …
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- 50 sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with an …
FIG. 6 illustrates cross-sectional views of various struc- 60 tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 65 multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a layer or substrate having a first region and a second region, the layer or substrate comprising gallium and nitrogen; a GaN-based device in or on the first region of the layer or substrate; a CMOS-based device over the second region of the layer or substrate; an interconnect structure over the GaN-based device and over the CMOS-based device, the interconnect struc-ture comprising conductive interconnects and vias in a dielectric layer; and a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the pho-tonics waveguide bonded to the dielectric layer of the interconnect structure.
The integrated circuit structure of claim 1, further comprising a tuning element over the interconnect structure, the tuning element comprising silicon, and the tuning ele-ment bonded to the dielectric layer of the interconnect structure.
The integrated circuit structure of claim 1, further comprising a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The integrated circuit structure of claim 1, further comprising a bonding layer between the photonics wave-guide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The integrated circuit structure of claim 1, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a layer or substrate having a first region and a second region, the layer or substrate comprising gallium and nitrogen; a GaN-based device in or on the first region of the layer or substrate; a CMOS-based device over the second region of the layer or substrate; an interconnect structure over the GaN-based device and over the CMOS-based device, the interconnect struc-ture comprising conductive interconnects and vias in a dielectric layer; and a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the pho-tonics waveguide bonded to the dielectric layer of the interconnect structure.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a tuning element over the interconnect structure, the tuning element compris-ing silicon, and the tuning element bonded to the dielectric layer of the interconnect structure.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a bonding layer between the photonics waveguide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The computing device of claim 6, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate.
A method of fabricating an integrated circuit structure, the method comprising: forming a layer or substrate having a first region and a second region, the layer or substrate comprising gal-lium and nitrogen; forming a GaN-based device in or on the first region of the layer or substrate; forming a CMOS-based device over the second region of the layer or substrate; forming an interconnect structure over the GaN-based device and over the CMOS-based device, the intercon-nect structure comprising conductive interconnects and vias in a dielectric layer; and forming a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.
The method of claim 15, wherein forming the pho-tonics waveguide over the interconnect structure comprises using a layer transfer process.
The method of claim 15, further comprising forming a tuning element over the interconnect structure, the tuning element comprising silicon, and the tuning element bonded to the dielectric layer of the interconnect structure.
The method of claim 15, further comprising forming a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The method of claim 15, further comprising forming a bonding layer between the photonics waveguide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The method of claim 15, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN integrated circuit structure with optical communication
Materials described outside the worked examples.
GaN layer or substrate
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,292,608 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1D-1G illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure for high speed optical …
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- 50 sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with an …
FIG. 6 illustrates cross-sectional views of various struc- 60 tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 65 multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a layer or substrate having a first region and a second region, the layer or substrate comprising gallium and nitrogen; a GaN-based device in or on the first region of the layer or substrate; a CMOS-based device over the second region of the layer or substrate; an interconnect structure over the GaN-based device and over the CMOS-based device, the interconnect struc-ture comprising conductive interconnects and vias in a dielectric layer; and a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the pho-tonics waveguide bonded to the dielectric layer of the interconnect structure.
The integrated circuit structure of claim 1, further comprising a tuning element over the interconnect structure, the tuning element comprising silicon, and the tuning ele-ment bonded to the dielectric layer of the interconnect structure.
The integrated circuit structure of claim 1, further comprising a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The integrated circuit structure of claim 1, further comprising a bonding layer between the photonics wave-guide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The integrated circuit structure of claim 1, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a layer or substrate having a first region and a second region, the layer or substrate comprising gallium and nitrogen; a GaN-based device in or on the first region of the layer or substrate; a CMOS-based device over the second region of the layer or substrate; an interconnect structure over the GaN-based device and over the CMOS-based device, the interconnect struc-ture comprising conductive interconnects and vias in a dielectric layer; and a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the pho-tonics waveguide bonded to the dielectric layer of the interconnect structure.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a tuning element over the interconnect structure, the tuning element compris-ing silicon, and the tuning element bonded to the dielectric layer of the interconnect structure.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a bonding layer between the photonics waveguide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The computing device of claim 6, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate.
A method of fabricating an integrated circuit structure, the method comprising: forming a layer or substrate having a first region and a second region, the layer or substrate comprising gal-lium and nitrogen; forming a GaN-based device in or on the first region of the layer or substrate; forming a CMOS-based device over the second region of the layer or substrate; forming an interconnect structure over the GaN-based device and over the CMOS-based device, the intercon-nect structure comprising conductive interconnects and vias in a dielectric layer; and forming a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.
The method of claim 15, wherein forming the pho-tonics waveguide over the interconnect structure comprises using a layer transfer process.
The method of claim 15, further comprising forming a tuning element over the interconnect structure, the tuning element comprising silicon, and the tuning element bonded to the dielectric layer of the interconnect structure.
The method of claim 15, further comprising forming a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The method of claim 15, further comprising forming a bonding layer between the photonics waveguide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The method of claim 15, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN integrated circuit structure with optical communication
Materials described outside the worked examples.
GaN layer or substrate
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,292,608 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1D-1G illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure for high speed optical …
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- 50 sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with an …
FIG. 6 illustrates cross-sectional views of various struc- 60 tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 65 multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a layer or substrate having a first region and a second region, the layer or substrate comprising gallium and nitrogen; a GaN-based device in or on the first region of the layer or substrate; a CMOS-based device over the second region of the layer or substrate; an interconnect structure over the GaN-based device and over the CMOS-based device, the interconnect struc-ture comprising conductive interconnects and vias in a dielectric layer; and a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the pho-tonics waveguide bonded to the dielectric layer of the interconnect structure.
The integrated circuit structure of claim 1, further comprising a tuning element over the interconnect structure, the tuning element comprising silicon, and the tuning ele-ment bonded to the dielectric layer of the interconnect structure.
The integrated circuit structure of claim 1, further comprising a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The integrated circuit structure of claim 1, further comprising a bonding layer between the photonics wave-guide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The integrated circuit structure of claim 1, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a layer or substrate having a first region and a second region, the layer or substrate comprising gallium and nitrogen; a GaN-based device in or on the first region of the layer or substrate; a CMOS-based device over the second region of the layer or substrate; an interconnect structure over the GaN-based device and over the CMOS-based device, the interconnect struc-ture comprising conductive interconnects and vias in a dielectric layer; and a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the pho-tonics waveguide bonded to the dielectric layer of the interconnect structure.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a tuning element over the interconnect structure, the tuning element compris-ing silicon, and the tuning element bonded to the dielectric layer of the interconnect structure.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The computing device of claim 6, wherein the inte-grated circuit structure further comprises a bonding layer between the photonics waveguide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The computing device of claim 6, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate.
A method of fabricating an integrated circuit structure, the method comprising: forming a layer or substrate having a first region and a second region, the layer or substrate comprising gal-lium and nitrogen; forming a GaN-based device in or on the first region of the layer or substrate; forming a CMOS-based device over the second region of the layer or substrate; forming an interconnect structure over the GaN-based device and over the CMOS-based device, the intercon-nect structure comprising conductive interconnects and vias in a dielectric layer; and forming a photonics waveguide over the interconnect structure, the photonics waveguide comprising silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.
The method of claim 15, wherein forming the pho-tonics waveguide over the interconnect structure comprises using a layer transfer process.
The method of claim 15, further comprising forming a tuning element over the interconnect structure, the tuning element comprising silicon, and the tuning element bonded to the dielectric layer of the interconnect structure.
The method of claim 15, further comprising forming a laser device above the photonics waveguide, the laser device comprising a Group III-V material.
The method of claim 15, further comprising forming a bonding layer between the photonics waveguide and the dielectric layer of the interconnect structure, the bonding layer comprising silicon and oxygen.
The method of claim 15, wherein the CMOS-based device comprises a silicon channel layer bonded to the layer or substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN integrated circuit structure with optical communication
Materials described outside the worked examples.
GaN layer or substrate
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Computing device with GaN integrated circuit structure
Group III-V material
bonding layer comprising silicon and oxygen
SiOx
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
Computing device with GaN integrated circuit structure
Group III-V material
bonding layer comprising silicon and oxygen
SiOx
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
Computing device with GaN integrated circuit structure
Group III-V material
bonding layer comprising silicon and oxygen
SiOx
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
Computing device with GaN integrated circuit structure
Group III-V material
bonding layer comprising silicon and oxygen
SiOx
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
