Patent
Atlas literature
Patent
US 12,334,421 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the inven- tion;
FIG. 2B is an isometric bottom view of the electronic package illustrated in
FIG. 3 is an isometric partial cross-sectional view of the electronic package illustrated in
FIG. 4 is an isometric partial cross-sectional view of an electronic device;
FIG. 5 is an isometric partial cross-sectional view of the electronic package illustrated in
FIG. 6C illustrates a simplified schematic of a desatura- tion detection circuit, according to embodiments of the 30 disclosure;
FIG. 7D is a transparent plan view of an electronic 45 package with the encapsulant removed, the package includ- ing an integrated controller with a …
FIG. 8 is a transparent plan view of an electronic package with the encapsulant removed, according to a stacked die single switch embodiment of the invention;
FIG. 9 is a transparent plan view of an electronic package with the encapsulant removed, according to a single switch 65 with an internal Zener reference …
FIG. 10B illustrates a simplified functional block diagram of the electronic package illustrated in
FIG. 11 is method of manufacturing an electronic package according to an embodiment of the invention.
FIG. 40 8, silicon-based high side driver/control die 1030 can be stacked on high side GaN-based transistor die 1005 and/or silicon-based low side …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a die-attach pad, at least one drain terminal, at least one source terminal and at least one gate terminal; and a gallium nitride (GaN) semiconductor substrate includ-ing a transistor formed therein, the transistor including a gate, a drain and a source, wherein: the GaN semiconductor substrate is electrically connected to the die-attach pad; the gate is directly electrically connected to the at least one gate terminal; the drain is directly electrically connected to the at least one drain terminal; and the source is directly electrically connected to the at least one source terminal, wherein the at least one source terminal is directly electrically connected to one or more current sense resistors.
The electronic device of claim 1 wherein the die-attach pad is arranged to be coupled to a ground potential.
The electronic device of claim 1 wherein the die-attach pad, the at least one drain terminal, the at least one source terminal and the at least one gate terminal are electrically isolated from each other.
The electronic device of claim 1 wherein at least a portion of the GaN semiconductor substrate is covered by an encapsulant.
The electronic device of claim 1 wherein the at least one source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The electronic device of claim 1 wherein the GaN semiconductor substrate includes one or more layers of GaN formed on a layer of silicon.
A device comprising: at least one die-attach terminal, at least one drain terminal, at least one source terminal and at least one gate terminal; and a gallium nitride (GaN) semiconductor substrate includ-ing at least one transistor having at least one gate, at least one drain and at least one source, wherein: the GaN semiconductor substrate is electrically and physi-cally connected to the at least one die-attach terminal; the at least one gate is directly electrically connected to the at least one gate terminal; the at least one drain is directly electrically connected to the at least one drain terminal; and the at least one source is directly electrically connected to the at least one source terminal and is directly electri-cally connected to one or more current sense resistors.
The device of claim 8 wherein the at least one die-attach terminal is arranged to be connected to a ground potential.
The device of claim 8 wherein the at least one die-attach terminal, the at least one drain terminal, the at least one source terminal and the at least one gate terminal are electrically isolated from each other.
The device of claim 8 further comprising an encap-sulant that covers at least a portion of the GaN substrate.
The device of claim 8 wherein the at least one source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The device of claim 8 wherein the GaN semiconductor substrate includes one or more layers of GaN formed on a layer of silicon.
An electronic package comprising: a plurality of external terminals including a ground ter-minal, a drain terminal, a source terminal and a gate terminal; and a gallium nitride (GaN) die including at least one tran-sistor having a drain contact, a source contact and a gate contact, the GaN die electrically and physically connected to the ground terminal, wherein the drain contact is directly electrically coupled to the drain terminal, the source contact is directly electrically coupled to the source terminal and the gate contact is directly electrically coupled to the gate terminal, and wherein the source terminal is directly electrically coupled to one or more current sense resistors; and an encapsulant disposed between each of the plurality of external terminals.
The electronic package of claim 15 wherein the ground terminal is arranged to be connected to a ground potential.
The electronic package of claim 15 wherein the ground terminal, the drain terminal, the source terminal and the gate terminal are electrically isolated from each other.
The electronic package of claim 15 wherein the encapsulant covers at least a portion of the GaN die.
The electronic package of claim 15 wherein the source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The electronic package of claim 15 wherein the GaN die includes one or more layers of GaN formed on a layer of silicon. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based electronic device/packaged transistor with current sense
GaN electronic package with current sense resistors and encapsulant
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
silicon
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 40 8, silicon-based high side driver/control die 1030 can be stacked on high side GaN-based transistor die 1005 and/or silicon-based low side …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–3 mm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 27
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,334,421 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the inven- tion;
FIG. 2B is an isometric bottom view of the electronic package illustrated in
FIG. 3 is an isometric partial cross-sectional view of the electronic package illustrated in
FIG. 4 is an isometric partial cross-sectional view of an electronic device;
FIG. 5 is an isometric partial cross-sectional view of the electronic package illustrated in
FIG. 6C illustrates a simplified schematic of a desatura- tion detection circuit, according to embodiments of the 30 disclosure;
FIG. 7D is a transparent plan view of an electronic 45 package with the encapsulant removed, the package includ- ing an integrated controller with a …
FIG. 8 is a transparent plan view of an electronic package with the encapsulant removed, according to a stacked die single switch embodiment of the invention;
FIG. 9 is a transparent plan view of an electronic package with the encapsulant removed, according to a single switch 65 with an internal Zener reference …
FIG. 10B illustrates a simplified functional block diagram of the electronic package illustrated in
FIG. 11 is method of manufacturing an electronic package according to an embodiment of the invention.
FIG. 40 8, silicon-based high side driver/control die 1030 can be stacked on high side GaN-based transistor die 1005 and/or silicon-based low side …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a die-attach pad, at least one drain terminal, at least one source terminal and at least one gate terminal; and a gallium nitride (GaN) semiconductor substrate includ-ing a transistor formed therein, the transistor including a gate, a drain and a source, wherein: the GaN semiconductor substrate is electrically connected to the die-attach pad; the gate is directly electrically connected to the at least one gate terminal; the drain is directly electrically connected to the at least one drain terminal; and the source is directly electrically connected to the at least one source terminal, wherein the at least one source terminal is directly electrically connected to one or more current sense resistors.
The electronic device of claim 1 wherein the die-attach pad is arranged to be coupled to a ground potential.
The electronic device of claim 1 wherein the die-attach pad, the at least one drain terminal, the at least one source terminal and the at least one gate terminal are electrically isolated from each other.
The electronic device of claim 1 wherein at least a portion of the GaN semiconductor substrate is covered by an encapsulant.
The electronic device of claim 1 wherein the at least one source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The electronic device of claim 1 wherein the GaN semiconductor substrate includes one or more layers of GaN formed on a layer of silicon.
A device comprising: at least one die-attach terminal, at least one drain terminal, at least one source terminal and at least one gate terminal; and a gallium nitride (GaN) semiconductor substrate includ-ing at least one transistor having at least one gate, at least one drain and at least one source, wherein: the GaN semiconductor substrate is electrically and physi-cally connected to the at least one die-attach terminal; the at least one gate is directly electrically connected to the at least one gate terminal; the at least one drain is directly electrically connected to the at least one drain terminal; and the at least one source is directly electrically connected to the at least one source terminal and is directly electri-cally connected to one or more current sense resistors.
The device of claim 8 wherein the at least one die-attach terminal is arranged to be connected to a ground potential.
The device of claim 8 wherein the at least one die-attach terminal, the at least one drain terminal, the at least one source terminal and the at least one gate terminal are electrically isolated from each other.
The device of claim 8 further comprising an encap-sulant that covers at least a portion of the GaN substrate.
The device of claim 8 wherein the at least one source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The device of claim 8 wherein the GaN semiconductor substrate includes one or more layers of GaN formed on a layer of silicon.
An electronic package comprising: a plurality of external terminals including a ground ter-minal, a drain terminal, a source terminal and a gate terminal; and a gallium nitride (GaN) die including at least one tran-sistor having a drain contact, a source contact and a gate contact, the GaN die electrically and physically connected to the ground terminal, wherein the drain contact is directly electrically coupled to the drain terminal, the source contact is directly electrically coupled to the source terminal and the gate contact is directly electrically coupled to the gate terminal, and wherein the source terminal is directly electrically coupled to one or more current sense resistors; and an encapsulant disposed between each of the plurality of external terminals.
The electronic package of claim 15 wherein the ground terminal is arranged to be connected to a ground potential.
The electronic package of claim 15 wherein the ground terminal, the drain terminal, the source terminal and the gate terminal are electrically isolated from each other.
The electronic package of claim 15 wherein the encapsulant covers at least a portion of the GaN die.
The electronic package of claim 15 wherein the source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The electronic package of claim 15 wherein the GaN die includes one or more layers of GaN formed on a layer of silicon. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based electronic device/packaged transistor with current sense
GaN electronic package with current sense resistors and encapsulant
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
silicon
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 40 8, silicon-based high side driver/control die 1030 can be stacked on high side GaN-based transistor die 1005 and/or silicon-based low side …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–3 mm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 27
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,334,421 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the inven- tion;
FIG. 2B is an isometric bottom view of the electronic package illustrated in
FIG. 3 is an isometric partial cross-sectional view of the electronic package illustrated in
FIG. 4 is an isometric partial cross-sectional view of an electronic device;
FIG. 5 is an isometric partial cross-sectional view of the electronic package illustrated in
FIG. 6C illustrates a simplified schematic of a desatura- tion detection circuit, according to embodiments of the 30 disclosure;
FIG. 7D is a transparent plan view of an electronic 45 package with the encapsulant removed, the package includ- ing an integrated controller with a …
FIG. 8 is a transparent plan view of an electronic package with the encapsulant removed, according to a stacked die single switch embodiment of the invention;
FIG. 9 is a transparent plan view of an electronic package with the encapsulant removed, according to a single switch 65 with an internal Zener reference …
FIG. 10B illustrates a simplified functional block diagram of the electronic package illustrated in
FIG. 11 is method of manufacturing an electronic package according to an embodiment of the invention.
FIG. 40 8, silicon-based high side driver/control die 1030 can be stacked on high side GaN-based transistor die 1005 and/or silicon-based low side …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a die-attach pad, at least one drain terminal, at least one source terminal and at least one gate terminal; and a gallium nitride (GaN) semiconductor substrate includ-ing a transistor formed therein, the transistor including a gate, a drain and a source, wherein: the GaN semiconductor substrate is electrically connected to the die-attach pad; the gate is directly electrically connected to the at least one gate terminal; the drain is directly electrically connected to the at least one drain terminal; and the source is directly electrically connected to the at least one source terminal, wherein the at least one source terminal is directly electrically connected to one or more current sense resistors.
The electronic device of claim 1 wherein the die-attach pad is arranged to be coupled to a ground potential.
The electronic device of claim 1 wherein the die-attach pad, the at least one drain terminal, the at least one source terminal and the at least one gate terminal are electrically isolated from each other.
The electronic device of claim 1 wherein at least a portion of the GaN semiconductor substrate is covered by an encapsulant.
The electronic device of claim 1 wherein the at least one source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The electronic device of claim 1 wherein the GaN semiconductor substrate includes one or more layers of GaN formed on a layer of silicon.
A device comprising: at least one die-attach terminal, at least one drain terminal, at least one source terminal and at least one gate terminal; and a gallium nitride (GaN) semiconductor substrate includ-ing at least one transistor having at least one gate, at least one drain and at least one source, wherein: the GaN semiconductor substrate is electrically and physi-cally connected to the at least one die-attach terminal; the at least one gate is directly electrically connected to the at least one gate terminal; the at least one drain is directly electrically connected to the at least one drain terminal; and the at least one source is directly electrically connected to the at least one source terminal and is directly electri-cally connected to one or more current sense resistors.
The device of claim 8 wherein the at least one die-attach terminal is arranged to be connected to a ground potential.
The device of claim 8 wherein the at least one die-attach terminal, the at least one drain terminal, the at least one source terminal and the at least one gate terminal are electrically isolated from each other.
The device of claim 8 further comprising an encap-sulant that covers at least a portion of the GaN substrate.
The device of claim 8 wherein the at least one source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The device of claim 8 wherein the GaN semiconductor substrate includes one or more layers of GaN formed on a layer of silicon.
An electronic package comprising: a plurality of external terminals including a ground ter-minal, a drain terminal, a source terminal and a gate terminal; and a gallium nitride (GaN) die including at least one tran-sistor having a drain contact, a source contact and a gate contact, the GaN die electrically and physically connected to the ground terminal, wherein the drain contact is directly electrically coupled to the drain terminal, the source contact is directly electrically coupled to the source terminal and the gate contact is directly electrically coupled to the gate terminal, and wherein the source terminal is directly electrically coupled to one or more current sense resistors; and an encapsulant disposed between each of the plurality of external terminals.
The electronic package of claim 15 wherein the ground terminal is arranged to be connected to a ground potential.
The electronic package of claim 15 wherein the ground terminal, the drain terminal, the source terminal and the gate terminal are electrically isolated from each other.
The electronic package of claim 15 wherein the encapsulant covers at least a portion of the GaN die.
The electronic package of claim 15 wherein the source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The electronic package of claim 15 wherein the GaN die includes one or more layers of GaN formed on a layer of silicon. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based electronic device/packaged transistor with current sense
GaN electronic package with current sense resistors and encapsulant
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
silicon
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 40 8, silicon-based high side driver/control die 1030 can be stacked on high side GaN-based transistor die 1005 and/or silicon-based low side …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–3 mm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 27
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,334,421 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the inven- tion;
FIG. 2B is an isometric bottom view of the electronic package illustrated in
FIG. 3 is an isometric partial cross-sectional view of the electronic package illustrated in
FIG. 4 is an isometric partial cross-sectional view of an electronic device;
FIG. 5 is an isometric partial cross-sectional view of the electronic package illustrated in
FIG. 6C illustrates a simplified schematic of a desatura- tion detection circuit, according to embodiments of the 30 disclosure;
FIG. 7D is a transparent plan view of an electronic 45 package with the encapsulant removed, the package includ- ing an integrated controller with a …
FIG. 8 is a transparent plan view of an electronic package with the encapsulant removed, according to a stacked die single switch embodiment of the invention;
FIG. 9 is a transparent plan view of an electronic package with the encapsulant removed, according to a single switch 65 with an internal Zener reference …
FIG. 10B illustrates a simplified functional block diagram of the electronic package illustrated in
FIG. 11 is method of manufacturing an electronic package according to an embodiment of the invention.
FIG. 40 8, silicon-based high side driver/control die 1030 can be stacked on high side GaN-based transistor die 1005 and/or silicon-based low side …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a die-attach pad, at least one drain terminal, at least one source terminal and at least one gate terminal; and a gallium nitride (GaN) semiconductor substrate includ-ing a transistor formed therein, the transistor including a gate, a drain and a source, wherein: the GaN semiconductor substrate is electrically connected to the die-attach pad; the gate is directly electrically connected to the at least one gate terminal; the drain is directly electrically connected to the at least one drain terminal; and the source is directly electrically connected to the at least one source terminal, wherein the at least one source terminal is directly electrically connected to one or more current sense resistors.
The electronic device of claim 1 wherein the die-attach pad is arranged to be coupled to a ground potential.
The electronic device of claim 1 wherein the die-attach pad, the at least one drain terminal, the at least one source terminal and the at least one gate terminal are electrically isolated from each other.
The electronic device of claim 1 wherein at least a portion of the GaN semiconductor substrate is covered by an encapsulant.
The electronic device of claim 1 wherein the at least one source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The electronic device of claim 1 wherein the GaN semiconductor substrate includes one or more layers of GaN formed on a layer of silicon.
A device comprising: at least one die-attach terminal, at least one drain terminal, at least one source terminal and at least one gate terminal; and a gallium nitride (GaN) semiconductor substrate includ-ing at least one transistor having at least one gate, at least one drain and at least one source, wherein: the GaN semiconductor substrate is electrically and physi-cally connected to the at least one die-attach terminal; the at least one gate is directly electrically connected to the at least one gate terminal; the at least one drain is directly electrically connected to the at least one drain terminal; and the at least one source is directly electrically connected to the at least one source terminal and is directly electri-cally connected to one or more current sense resistors.
The device of claim 8 wherein the at least one die-attach terminal is arranged to be connected to a ground potential.
The device of claim 8 wherein the at least one die-attach terminal, the at least one drain terminal, the at least one source terminal and the at least one gate terminal are electrically isolated from each other.
The device of claim 8 further comprising an encap-sulant that covers at least a portion of the GaN substrate.
The device of claim 8 wherein the at least one source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The device of claim 8 wherein the GaN semiconductor substrate includes one or more layers of GaN formed on a layer of silicon.
An electronic package comprising: a plurality of external terminals including a ground ter-minal, a drain terminal, a source terminal and a gate terminal; and a gallium nitride (GaN) die including at least one tran-sistor having a drain contact, a source contact and a gate contact, the GaN die electrically and physically connected to the ground terminal, wherein the drain contact is directly electrically coupled to the drain terminal, the source contact is directly electrically coupled to the source terminal and the gate contact is directly electrically coupled to the gate terminal, and wherein the source terminal is directly electrically coupled to one or more current sense resistors; and an encapsulant disposed between each of the plurality of external terminals.
The electronic package of claim 15 wherein the ground terminal is arranged to be connected to a ground potential.
The electronic package of claim 15 wherein the ground terminal, the drain terminal, the source terminal and the gate terminal are electrically isolated from each other.
The electronic package of claim 15 wherein the encapsulant covers at least a portion of the GaN die.
The electronic package of claim 15 wherein the source terminal is directly electrically coupled to the one or more current sense resistors via wirebonds, metallic clips, vias, or conductive epoxy.
The electronic package of claim 15 wherein the GaN die includes one or more layers of GaN formed on a layer of silicon. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based electronic device/packaged transistor with current sense
GaN electronic package with current sense resistors and encapsulant
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
silicon
Si
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 40 8, silicon-based high side driver/control die 1030 can be stacked on high side GaN-based transistor die 1005 and/or silicon-based low side …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–3 mm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 27
Related documents with shared materials, methods, properties, or citations.
GaN-based power conversion component (embodiment)
encapsulant
| — |
Thickness | 0.8–1.2 mm | — |
Thickness | 1.8–2.8 mm | — |
Thickness | 50–250 µm | — |
Thickness | 100–200 µm | — |
Thickness | 50000–1000000 nm | — |
Thickness | 150–500 µm | — |
Thickness | 2–3 mm | — |
Thickness | ≥ 1 mm | — |
Thickness | ≥ 1.5 mm | — |
Thickness | ≥ 2 mm | — |
Cited non-patent literature · 5
GaN-based power conversion component (embodiment)
encapsulant
| — |
Thickness | 0.8–1.2 mm | — |
Thickness | 1.8–2.8 mm | — |
Thickness | 50–250 µm | — |
Thickness | 100–200 µm | — |
Thickness | 50000–1000000 nm | — |
Thickness | 150–500 µm | — |
Thickness | 2–3 mm | — |
Thickness | ≥ 1 mm | — |
Thickness | ≥ 1.5 mm | — |
Thickness | ≥ 2 mm | — |
Cited non-patent literature · 5
GaN-based power conversion component (embodiment)
encapsulant
| — |
Thickness | 0.8–1.2 mm | — |
Thickness | 1.8–2.8 mm | — |
Thickness | 50–250 µm | — |
Thickness | 100–200 µm | — |
Thickness | 50000–1000000 nm | — |
Thickness | 150–500 µm | — |
Thickness | 2–3 mm | — |
Thickness | ≥ 1 mm | — |
Thickness | ≥ 1.5 mm | — |
Thickness | ≥ 2 mm | — |
Cited non-patent literature · 5
GaN-based power conversion component (embodiment)
encapsulant
| — |
Thickness | 0.8–1.2 mm | — |
Thickness | 1.8–2.8 mm | — |
Thickness | 50–250 µm | — |
Thickness | 100–200 µm | — |
Thickness | 50000–1000000 nm | — |
Thickness | 150–500 µm | — |
Thickness | 2–3 mm | — |
Thickness | ≥ 1 mm | — |
Thickness | ≥ 1.5 mm | — |
Thickness | ≥ 2 mm | — |
Cited non-patent literature · 5
