Patent
US 10,903,352MANUFACTURING METHOD OF VERTICAL GaN-BASED SEMICONDUCTOR DEVICE AND VERTICAL GaN-BASED SEMICONDUCTOR DEVICE
Shinya TAKASHIMA
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,903,352Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-section of a vertical MOSFET 200 according to a first embodiment. FIG 2 illustrates a Ga polarity plane, an N polarity plane and an m …
FIG. 2 illustrates a Ga polarity plane, an N polarity plane and an m plane in a G aN crystal. In this specification, the Ga polarity plane means a (0001) plane …
FIG. 3 illustrates a manufact u ring method of a vertical MOSFET 200.
FIG. 4 illustrates S 1 0 to S 60 of the manufacturing method of the vertical MOSFET 200.
FIG. 5 illustrates S₇₀ to S 100 of the manufacturing method of the vertical MOSFET 200.
FIG. 6 illustrates a state in which a laser beam is irradiated to a back surface 16 in S90.
FIG. 7 illustrates a cross-section of a vertical MOSFET 300 according to a second embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A manufacturing method of a vertical GaN-based semiconductor device, the vertical GaN-based semiconductor device comprising: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type impurity lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, the method includes: forming the MIS structure, implanting an n type dopant in a back surface of the GaN-based semiconductor substrate after the forming of the MIS structure, and annealing the GaN-based semiconductor substrate after the implanting of the n type dopant. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the back surface of the GaN-based semiconductor substrate has heat resistance higher than that of a gallium polarity plane. Withdrawn
(Withdrawn-Previously Amended): The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the back surface of the GaN-based semiconductor substrate is a nitrogen polarity plane or an m plane. Currently amended
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the annealing of the GaN-based semiconductor substrate includes: annealing the GaN-based semiconductor substrate without providing a protective layer contacting the back surface. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the annealing of the GaN-based semiconductor substrate includes: annealing the GaN-based semiconductor substrate by irradiating the back surface with a laser beam. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, further comprising: thinning the GaN-based semiconductor substrate before the implanting of the n type dopant in the back surface and the annealing of the GaN-based semiconductor substrate. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the GaN-based semiconductor substrate is annealed at a predetermined temperature from 1000 ° C to 1350 ° C in the annealing of the GaN-based semiconductor substrate. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein at least one of elements including silicon, germanium, and oxygen is implanted in the back surface of the GaN-based semiconductor substrate in the implanting of the n type dopant in the back surface. Withdrawn
A vertical GaN-based semiconductor device comprising: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type dopant lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, wherein doping concentration of an n type dopant in a lower region provided from a predetermined depth position to a back surface of the GaN-based semiconductor substrate is higher than doping concentration of an n type dopant in an upper region provided above the predetermined depth position of the GaN-based semiconductor substrate, and the lower region includes a peak in the doping concentration, the doping concentration at the peak being higher than or equal to the doping concentration at the back surface and higher than the doping concentration at the predetermined depth position, and the upper region includes a tail region in the doping concentration, the doping concentration in the tail region decreasing from the predetermined depth position toward the GaN-based semiconductor layer. Currently amended
The vertical GaN-based semiconductor device according to claim 9, wherein the back surface of the GaN-based semiconductor substrate has heat resistance higher than that of a gallium polarity plane. Original
The vertical GaN-based semiconductor device concentration of the lower region periodically surface. Original semiconductor device according to claim 9, semiconductor substrate is a nitrogen polarity plane or according to claim 9, wherein a peak of doping direction of the lower region is 1E+1 9cm -3 or according to claim 9, wherein carrier changes in a predetermined direction of the back
(Previously Amended): The vertical GaN-based wherein the back surface of the GaN-based an m plane. Currently amended
The vertical GaN-based semiconductor device concentration of an n type dopant in a depth more. Original
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based MOSFET (DMOS)
Materials described outside the worked examples.
GaN-based semiconductor substrate
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peak doping concentration of n type dopant in lower region | ≥ 10000000000000000000 cm⁻³ | GaN |
annealing temperature for back surface activation | 1000–1350 °C |
Related documents with shared materials, methods, properties, or citations.
GaN Devices With Ion Implanted Ohmic Contacts and Method of Fabricating Devices Incorporating the Same
Combining metal dewetting and lateral etching for the scalable top-down fabrication of GaN nanowire arrays with independently tunable diameter and spacing
Patent
Atlas literature
Patent
US 10,903,352Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-section of a vertical MOSFET 200 according to a first embodiment. FIG 2 illustrates a Ga polarity plane, an N polarity plane and an m …
FIG. 2 illustrates a Ga polarity plane, an N polarity plane and an m plane in a G aN crystal. In this specification, the Ga polarity plane means a (0001) plane …
FIG. 3 illustrates a manufact u ring method of a vertical MOSFET 200.
FIG. 4 illustrates S 1 0 to S 60 of the manufacturing method of the vertical MOSFET 200.
FIG. 5 illustrates S₇₀ to S 100 of the manufacturing method of the vertical MOSFET 200.
FIG. 6 illustrates a state in which a laser beam is irradiated to a back surface 16 in S90.
FIG. 7 illustrates a cross-section of a vertical MOSFET 300 according to a second embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A manufacturing method of a vertical GaN-based semiconductor device, the vertical GaN-based semiconductor device comprising: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type impurity lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, the method includes: forming the MIS structure, implanting an n type dopant in a back surface of the GaN-based semiconductor substrate after the forming of the MIS structure, and annealing the GaN-based semiconductor substrate after the implanting of the n type dopant. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the back surface of the GaN-based semiconductor substrate has heat resistance higher than that of a gallium polarity plane. Withdrawn
(Withdrawn-Previously Amended): The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the back surface of the GaN-based semiconductor substrate is a nitrogen polarity plane or an m plane. Currently amended
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the annealing of the GaN-based semiconductor substrate includes: annealing the GaN-based semiconductor substrate without providing a protective layer contacting the back surface. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the annealing of the GaN-based semiconductor substrate includes: annealing the GaN-based semiconductor substrate by irradiating the back surface with a laser beam. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, further comprising: thinning the GaN-based semiconductor substrate before the implanting of the n type dopant in the back surface and the annealing of the GaN-based semiconductor substrate. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the GaN-based semiconductor substrate is annealed at a predetermined temperature from 1000 ° C to 1350 ° C in the annealing of the GaN-based semiconductor substrate. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein at least one of elements including silicon, germanium, and oxygen is implanted in the back surface of the GaN-based semiconductor substrate in the implanting of the n type dopant in the back surface. Withdrawn
A vertical GaN-based semiconductor device comprising: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type dopant lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, wherein doping concentration of an n type dopant in a lower region provided from a predetermined depth position to a back surface of the GaN-based semiconductor substrate is higher than doping concentration of an n type dopant in an upper region provided above the predetermined depth position of the GaN-based semiconductor substrate, and the lower region includes a peak in the doping concentration, the doping concentration at the peak being higher than or equal to the doping concentration at the back surface and higher than the doping concentration at the predetermined depth position, and the upper region includes a tail region in the doping concentration, the doping concentration in the tail region decreasing from the predetermined depth position toward the GaN-based semiconductor layer. Currently amended
The vertical GaN-based semiconductor device according to claim 9, wherein the back surface of the GaN-based semiconductor substrate has heat resistance higher than that of a gallium polarity plane. Original
The vertical GaN-based semiconductor device concentration of the lower region periodically surface. Original semiconductor device according to claim 9, semiconductor substrate is a nitrogen polarity plane or according to claim 9, wherein a peak of doping direction of the lower region is 1E+1 9cm -3 or according to claim 9, wherein carrier changes in a predetermined direction of the back
(Previously Amended): The vertical GaN-based wherein the back surface of the GaN-based an m plane. Currently amended
The vertical GaN-based semiconductor device concentration of an n type dopant in a depth more. Original
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based MOSFET (DMOS)
Materials described outside the worked examples.
GaN-based semiconductor substrate
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peak doping concentration of n type dopant in lower region | ≥ 10000000000000000000 cm⁻³ | GaN |
annealing temperature for back surface activation | 1000–1350 °C |
Related documents with shared materials, methods, properties, or citations.
GaN Devices With Ion Implanted Ohmic Contacts and Method of Fabricating Devices Incorporating the Same
Combining metal dewetting and lateral etching for the scalable top-down fabrication of GaN nanowire arrays with independently tunable diameter and spacing
Patent
Atlas literature
Patent
US 10,903,352Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-section of a vertical MOSFET 200 according to a first embodiment. FIG 2 illustrates a Ga polarity plane, an N polarity plane and an m …
FIG. 2 illustrates a Ga polarity plane, an N polarity plane and an m plane in a G aN crystal. In this specification, the Ga polarity plane means a (0001) plane …
FIG. 3 illustrates a manufact u ring method of a vertical MOSFET 200.
FIG. 4 illustrates S 1 0 to S 60 of the manufacturing method of the vertical MOSFET 200.
FIG. 5 illustrates S₇₀ to S 100 of the manufacturing method of the vertical MOSFET 200.
FIG. 6 illustrates a state in which a laser beam is irradiated to a back surface 16 in S90.
FIG. 7 illustrates a cross-section of a vertical MOSFET 300 according to a second embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A manufacturing method of a vertical GaN-based semiconductor device, the vertical GaN-based semiconductor device comprising: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type impurity lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, the method includes: forming the MIS structure, implanting an n type dopant in a back surface of the GaN-based semiconductor substrate after the forming of the MIS structure, and annealing the GaN-based semiconductor substrate after the implanting of the n type dopant. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the back surface of the GaN-based semiconductor substrate has heat resistance higher than that of a gallium polarity plane. Withdrawn
(Withdrawn-Previously Amended): The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the back surface of the GaN-based semiconductor substrate is a nitrogen polarity plane or an m plane. Currently amended
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the annealing of the GaN-based semiconductor substrate includes: annealing the GaN-based semiconductor substrate without providing a protective layer contacting the back surface. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the annealing of the GaN-based semiconductor substrate includes: annealing the GaN-based semiconductor substrate by irradiating the back surface with a laser beam. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, further comprising: thinning the GaN-based semiconductor substrate before the implanting of the n type dopant in the back surface and the annealing of the GaN-based semiconductor substrate. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the GaN-based semiconductor substrate is annealed at a predetermined temperature from 1000 ° C to 1350 ° C in the annealing of the GaN-based semiconductor substrate. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein at least one of elements including silicon, germanium, and oxygen is implanted in the back surface of the GaN-based semiconductor substrate in the implanting of the n type dopant in the back surface. Withdrawn
A vertical GaN-based semiconductor device comprising: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type dopant lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, wherein doping concentration of an n type dopant in a lower region provided from a predetermined depth position to a back surface of the GaN-based semiconductor substrate is higher than doping concentration of an n type dopant in an upper region provided above the predetermined depth position of the GaN-based semiconductor substrate, and the lower region includes a peak in the doping concentration, the doping concentration at the peak being higher than or equal to the doping concentration at the back surface and higher than the doping concentration at the predetermined depth position, and the upper region includes a tail region in the doping concentration, the doping concentration in the tail region decreasing from the predetermined depth position toward the GaN-based semiconductor layer. Currently amended
The vertical GaN-based semiconductor device according to claim 9, wherein the back surface of the GaN-based semiconductor substrate has heat resistance higher than that of a gallium polarity plane. Original
The vertical GaN-based semiconductor device concentration of the lower region periodically surface. Original semiconductor device according to claim 9, semiconductor substrate is a nitrogen polarity plane or according to claim 9, wherein a peak of doping direction of the lower region is 1E+1 9cm -3 or according to claim 9, wherein carrier changes in a predetermined direction of the back
(Previously Amended): The vertical GaN-based wherein the back surface of the GaN-based an m plane. Currently amended
The vertical GaN-based semiconductor device concentration of an n type dopant in a depth more. Original
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based MOSFET (DMOS)
Materials described outside the worked examples.
GaN-based semiconductor substrate
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peak doping concentration of n type dopant in lower region | ≥ 10000000000000000000 cm⁻³ | GaN |
annealing temperature for back surface activation | 1000–1350 °C |
Related documents with shared materials, methods, properties, or citations.
GaN Devices With Ion Implanted Ohmic Contacts and Method of Fabricating Devices Incorporating the Same
Combining metal dewetting and lateral etching for the scalable top-down fabrication of GaN nanowire arrays with independently tunable diameter and spacing
Patent
Atlas literature
Patent
US 10,903,352Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-section of a vertical MOSFET 200 according to a first embodiment. FIG 2 illustrates a Ga polarity plane, an N polarity plane and an m …
FIG. 2 illustrates a Ga polarity plane, an N polarity plane and an m plane in a G aN crystal. In this specification, the Ga polarity plane means a (0001) plane …
FIG. 3 illustrates a manufact u ring method of a vertical MOSFET 200.
FIG. 4 illustrates S 1 0 to S 60 of the manufacturing method of the vertical MOSFET 200.
FIG. 5 illustrates S₇₀ to S 100 of the manufacturing method of the vertical MOSFET 200.
FIG. 6 illustrates a state in which a laser beam is irradiated to a back surface 16 in S90.
FIG. 7 illustrates a cross-section of a vertical MOSFET 300 according to a second embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A manufacturing method of a vertical GaN-based semiconductor device, the vertical GaN-based semiconductor device comprising: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type impurity lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, the method includes: forming the MIS structure, implanting an n type dopant in a back surface of the GaN-based semiconductor substrate after the forming of the MIS structure, and annealing the GaN-based semiconductor substrate after the implanting of the n type dopant. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the back surface of the GaN-based semiconductor substrate has heat resistance higher than that of a gallium polarity plane. Withdrawn
(Withdrawn-Previously Amended): The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the back surface of the GaN-based semiconductor substrate is a nitrogen polarity plane or an m plane. Currently amended
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the annealing of the GaN-based semiconductor substrate includes: annealing the GaN-based semiconductor substrate without providing a protective layer contacting the back surface. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the annealing of the GaN-based semiconductor substrate includes: annealing the GaN-based semiconductor substrate by irradiating the back surface with a laser beam. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, further comprising: thinning the GaN-based semiconductor substrate before the implanting of the n type dopant in the back surface and the annealing of the GaN-based semiconductor substrate. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein the GaN-based semiconductor substrate is annealed at a predetermined temperature from 1000 ° C to 1350 ° C in the annealing of the GaN-based semiconductor substrate. Withdrawn
The manufacturing method of the vertical GaN-based semiconductor device according to claim 1, wherein at least one of elements including silicon, germanium, and oxygen is implanted in the back surface of the GaN-based semiconductor substrate in the implanting of the n type dopant in the back surface. Withdrawn
A vertical GaN-based semiconductor device comprising: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type dopant lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, wherein doping concentration of an n type dopant in a lower region provided from a predetermined depth position to a back surface of the GaN-based semiconductor substrate is higher than doping concentration of an n type dopant in an upper region provided above the predetermined depth position of the GaN-based semiconductor substrate, and the lower region includes a peak in the doping concentration, the doping concentration at the peak being higher than or equal to the doping concentration at the back surface and higher than the doping concentration at the predetermined depth position, and the upper region includes a tail region in the doping concentration, the doping concentration in the tail region decreasing from the predetermined depth position toward the GaN-based semiconductor layer. Currently amended
The vertical GaN-based semiconductor device according to claim 9, wherein the back surface of the GaN-based semiconductor substrate has heat resistance higher than that of a gallium polarity plane. Original
The vertical GaN-based semiconductor device concentration of the lower region periodically surface. Original semiconductor device according to claim 9, semiconductor substrate is a nitrogen polarity plane or according to claim 9, wherein a peak of doping direction of the lower region is 1E+1 9cm -3 or according to claim 9, wherein carrier changes in a predetermined direction of the back
(Previously Amended): The vertical GaN-based wherein the back surface of the GaN-based an m plane. Currently amended
The vertical GaN-based semiconductor device concentration of an n type dopant in a depth more. Original
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based MOSFET (DMOS)
Materials described outside the worked examples.
GaN-based semiconductor substrate
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peak doping concentration of n type dopant in lower region | ≥ 10000000000000000000 cm⁻³ | GaN |
annealing temperature for back surface activation | 1000–1350 °C |
Related documents with shared materials, methods, properties, or citations.
GaN Devices With Ion Implanted Ohmic Contacts and Method of Fabricating Devices Incorporating the Same
Combining metal dewetting and lateral etching for the scalable top-down fabrication of GaN nanowire arrays with independently tunable diameter and spacing
germanium
Ge
oxygen
O
insulating film
magnesium
Mg
GaN substrate thickness | 50–200 μm | GaN |
Thickness | ≤ 300 nm | — |
germanium
Ge
oxygen
O
insulating film
magnesium
Mg
GaN substrate thickness | 50–200 μm | GaN |
Thickness | ≤ 300 nm | — |
germanium
Ge
oxygen
O
insulating film
magnesium
Mg
GaN substrate thickness | 50–200 μm | GaN |
Thickness | ≤ 300 nm | — |
germanium
Ge
oxygen
O
insulating film
magnesium
Mg
GaN substrate thickness | 50–200 μm | GaN |
Thickness | ≤ 300 nm | — |