Patent
US 10,454,481GaN LOGIC CIRCUITS
Santosh Sharma
NAVITAS SEMICONDUCTOR, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,454,481Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of an embodiment of a GaN inverter. [0006]
FIG. 2 is a waveform diagram illustrating the operation of the inverter of
FIG. 3 is a simplified schematic of an embodiment of a GaN inverter. [0008]
FIG. 4 is a waveform diagram illustrating the operation of the inverter of
FIG. 5 is a simplified schematic of an embodiment of a GaN inverter. [0010]
FIG. 6 is a waveform diagram illustrating the operation of the inverter of
FIG. 7 is a simplified schematic of an embodiment of a GaN NOR gate. [0012]
FIG. 8 is a waveform diagram illustrating the operation of the NOR gate of
FIG. 9 is a simplified schematic of an embodiment of a GaN NOR gate. [0014]
FIG. 10 is a waveform diagram illustrating the operation of the NOR gate of
FIG. 11 is a simplified schematic of an embodiment of a GaN NAND gate. [0016]
FIG. 12 is a waveform diagram illustrating the operation of the NAND gate of
FIG. 13 is a simplified schematic of an embodiment of a GaN NAND gate. [0018]
FIG. 14 is a waveform diagram illustrating the operation of the NAND gate of
FIG. 15 is a simplified schematic of an embodiment of a GaN buffer. [0020]
FIG. 16 is a waveform diagram illustrating the operation of the buffer of
FIG. 17 is a simplified schematic of an embodiment of a GaN OR gate. [0022]
FIG. 18 is a waveform diagram illustrating the operation of the OR gate of
FIG. 19 is a simplified schematic of an embodiment of a GaN AND gate. [0024]
FIG. 20 is a waveform diagram illustrating the operation of the AND gate of
FIG. 21 is a simplified schematic of an embodiment of a GaN AO I gate. [0026]
FIG. 22 is a simplified schematic of an embodiment of a level shift circuit, for example, for a GaN AO I gate. [0027]
FIG. 23 is a simplified schematic of an embodiment of an AO I logic circuit for a GaN AOI gate. [0028]
FIG. 24 is a simplified schematic of an embodiment of a GaN AO gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN digital circuit, comprising: a substrate comprising GaN; a first output node on the substrate, wherein a voltage at the first output node is configured to switch between first and second voltages, wherein the first voltage is less than the second voltage; a pull up switch on the substrate, the pull up switch comprising: a gate, a source connected to the first output node, and a drain connected to a power supply node having a voltage equal to or substantially equal to the second voltage, wherein the pull up switch is configured to cause a voltage at the first output node to be equal to the second voltage in response to a voltage at the gate; a capacitor on the substrate, the capacitor having a first terminal configured to cause the voltage at the gate to increase to substantially the sum of the second voltage and a third voltage in response to the voltage at the first output node increasing to the second voltage; and a first depletion mode charging switch on the substrate, wherein the first depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage.
The GaN digital circuit of claim 1, wherein the first depletion mode charging switch comprises a gate, wherein the first depletion mode charging switch is configured to cause the voltage at the first terminal of the capacitor to become substantially equal to the second voltage in response to a voltage at the gate of the first depletion mode charging switch being substantially equal to the second voltage.
The GaN digital circuit of claim 1, wherein the second and third voltages are equal.
The GaN digital circuit of claim 1, further comprising a second output node, wherein the second output node is connected to the first terminal of the capacitor.
The GaN digital circuit of claim 1, wherein the first terminal of the capacitor is connected to the gate of the pull up switch through a resistive element.
The GaN digital circuit of claim 1, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to a single input, and the digital circuit performs at least one of a logical inversion and a logical buffer function.
The GaN digital circuit of claim 1, further comprising a second depletion mode charging switch on the substrate, wherein the second depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to first and second inputs, and the digital circuit performs at least one of a logical NOR function and a logical NAND function.
The GaN digital circuit of claim 1 9, wherein the first and second voltages of the second GaN di g ita l log ic circuit are not equal.
A GaN digital circuit, comprising: a substrate comprising GaN; first and second GaN digital logic circuits on the substrate, wherein an output of the first GaN digital logic circuit is electrically connected with an input of the second GaN digital logic circuit, wherein each of the first and second GaN digital logic circuits comprises: a first output node on the substrate, wherein a voltage at the first output node is configured to switch between first and second voltages, wherein the first voltage is less than the second voltage; a pull up switch on the substrate, the pull up switch comprising: a gate, a source connected to the first output node, and a drain connected to a power supply node having a voltage equal to or substantially equal to the second voltage, wherein the pull up switch is configured to cause a voltage at the first output node to be equal to the second voltage in response to a voltage at the gate; a capacitor on the substrate, the capacitor having a first terminal connected to the gate of the pull up switch, wherein the capacitor is configured to cause the voltage at the gate to increase to substantially the sum of the second voltage and a third voltage in response to the voltage at the first output node increasing to the second voltage; and a first depletion mode charging switch on the substrate, wherein the first depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first vo ltag e and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage.
The GaN digital circuit of claim 17, wherein the first GaN digital logic circuit further comprises a second depletion mode char ging switch on the substrate. wherein the second depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second volta g e, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to first and second inputs, wherein the first GaN digital logic circuit performs one of a logical NOR function and a logical NAND function, and wherein the second GaN digital logic circuit performs a logic inversion function.
The GaN digital circuit of claim 17, wherein the first and second voltages of the first GaN digital logic circuit are equal.
Layer stacks claimed or described, ordered top of device to substrate.
GaN digital circuit (single logic gate)
GaN digital circuit (cascaded first and second logic circuits)
GaN inverter 100
GaN inverter 300 with level shift FET and level shift capacitor
Materials described outside the worked examples.
GaN
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,454,481Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of an embodiment of a GaN inverter. [0006]
FIG. 2 is a waveform diagram illustrating the operation of the inverter of
FIG. 3 is a simplified schematic of an embodiment of a GaN inverter. [0008]
FIG. 4 is a waveform diagram illustrating the operation of the inverter of
FIG. 5 is a simplified schematic of an embodiment of a GaN inverter. [0010]
FIG. 6 is a waveform diagram illustrating the operation of the inverter of
FIG. 7 is a simplified schematic of an embodiment of a GaN NOR gate. [0012]
FIG. 8 is a waveform diagram illustrating the operation of the NOR gate of
FIG. 9 is a simplified schematic of an embodiment of a GaN NOR gate. [0014]
FIG. 10 is a waveform diagram illustrating the operation of the NOR gate of
FIG. 11 is a simplified schematic of an embodiment of a GaN NAND gate. [0016]
FIG. 12 is a waveform diagram illustrating the operation of the NAND gate of
FIG. 13 is a simplified schematic of an embodiment of a GaN NAND gate. [0018]
FIG. 14 is a waveform diagram illustrating the operation of the NAND gate of
FIG. 15 is a simplified schematic of an embodiment of a GaN buffer. [0020]
FIG. 16 is a waveform diagram illustrating the operation of the buffer of
FIG. 17 is a simplified schematic of an embodiment of a GaN OR gate. [0022]
FIG. 18 is a waveform diagram illustrating the operation of the OR gate of
FIG. 19 is a simplified schematic of an embodiment of a GaN AND gate. [0024]
FIG. 20 is a waveform diagram illustrating the operation of the AND gate of
FIG. 21 is a simplified schematic of an embodiment of a GaN AO I gate. [0026]
FIG. 22 is a simplified schematic of an embodiment of a level shift circuit, for example, for a GaN AO I gate. [0027]
FIG. 23 is a simplified schematic of an embodiment of an AO I logic circuit for a GaN AOI gate. [0028]
FIG. 24 is a simplified schematic of an embodiment of a GaN AO gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN digital circuit, comprising: a substrate comprising GaN; a first output node on the substrate, wherein a voltage at the first output node is configured to switch between first and second voltages, wherein the first voltage is less than the second voltage; a pull up switch on the substrate, the pull up switch comprising: a gate, a source connected to the first output node, and a drain connected to a power supply node having a voltage equal to or substantially equal to the second voltage, wherein the pull up switch is configured to cause a voltage at the first output node to be equal to the second voltage in response to a voltage at the gate; a capacitor on the substrate, the capacitor having a first terminal configured to cause the voltage at the gate to increase to substantially the sum of the second voltage and a third voltage in response to the voltage at the first output node increasing to the second voltage; and a first depletion mode charging switch on the substrate, wherein the first depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage.
The GaN digital circuit of claim 1, wherein the first depletion mode charging switch comprises a gate, wherein the first depletion mode charging switch is configured to cause the voltage at the first terminal of the capacitor to become substantially equal to the second voltage in response to a voltage at the gate of the first depletion mode charging switch being substantially equal to the second voltage.
The GaN digital circuit of claim 1, wherein the second and third voltages are equal.
The GaN digital circuit of claim 1, further comprising a second output node, wherein the second output node is connected to the first terminal of the capacitor.
The GaN digital circuit of claim 1, wherein the first terminal of the capacitor is connected to the gate of the pull up switch through a resistive element.
The GaN digital circuit of claim 1, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to a single input, and the digital circuit performs at least one of a logical inversion and a logical buffer function.
The GaN digital circuit of claim 1, further comprising a second depletion mode charging switch on the substrate, wherein the second depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to first and second inputs, and the digital circuit performs at least one of a logical NOR function and a logical NAND function.
The GaN digital circuit of claim 1 9, wherein the first and second voltages of the second GaN di g ita l log ic circuit are not equal.
A GaN digital circuit, comprising: a substrate comprising GaN; first and second GaN digital logic circuits on the substrate, wherein an output of the first GaN digital logic circuit is electrically connected with an input of the second GaN digital logic circuit, wherein each of the first and second GaN digital logic circuits comprises: a first output node on the substrate, wherein a voltage at the first output node is configured to switch between first and second voltages, wherein the first voltage is less than the second voltage; a pull up switch on the substrate, the pull up switch comprising: a gate, a source connected to the first output node, and a drain connected to a power supply node having a voltage equal to or substantially equal to the second voltage, wherein the pull up switch is configured to cause a voltage at the first output node to be equal to the second voltage in response to a voltage at the gate; a capacitor on the substrate, the capacitor having a first terminal connected to the gate of the pull up switch, wherein the capacitor is configured to cause the voltage at the gate to increase to substantially the sum of the second voltage and a third voltage in response to the voltage at the first output node increasing to the second voltage; and a first depletion mode charging switch on the substrate, wherein the first depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first vo ltag e and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage.
The GaN digital circuit of claim 17, wherein the first GaN digital logic circuit further comprises a second depletion mode char ging switch on the substrate. wherein the second depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second volta g e, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to first and second inputs, wherein the first GaN digital logic circuit performs one of a logical NOR function and a logical NAND function, and wherein the second GaN digital logic circuit performs a logic inversion function.
The GaN digital circuit of claim 17, wherein the first and second voltages of the first GaN digital logic circuit are equal.
Layer stacks claimed or described, ordered top of device to substrate.
GaN digital circuit (single logic gate)
GaN digital circuit (cascaded first and second logic circuits)
GaN inverter 100
GaN inverter 300 with level shift FET and level shift capacitor
Materials described outside the worked examples.
GaN
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,454,481Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of an embodiment of a GaN inverter. [0006]
FIG. 2 is a waveform diagram illustrating the operation of the inverter of
FIG. 3 is a simplified schematic of an embodiment of a GaN inverter. [0008]
FIG. 4 is a waveform diagram illustrating the operation of the inverter of
FIG. 5 is a simplified schematic of an embodiment of a GaN inverter. [0010]
FIG. 6 is a waveform diagram illustrating the operation of the inverter of
FIG. 7 is a simplified schematic of an embodiment of a GaN NOR gate. [0012]
FIG. 8 is a waveform diagram illustrating the operation of the NOR gate of
FIG. 9 is a simplified schematic of an embodiment of a GaN NOR gate. [0014]
FIG. 10 is a waveform diagram illustrating the operation of the NOR gate of
FIG. 11 is a simplified schematic of an embodiment of a GaN NAND gate. [0016]
FIG. 12 is a waveform diagram illustrating the operation of the NAND gate of
FIG. 13 is a simplified schematic of an embodiment of a GaN NAND gate. [0018]
FIG. 14 is a waveform diagram illustrating the operation of the NAND gate of
FIG. 15 is a simplified schematic of an embodiment of a GaN buffer. [0020]
FIG. 16 is a waveform diagram illustrating the operation of the buffer of
FIG. 17 is a simplified schematic of an embodiment of a GaN OR gate. [0022]
FIG. 18 is a waveform diagram illustrating the operation of the OR gate of
FIG. 19 is a simplified schematic of an embodiment of a GaN AND gate. [0024]
FIG. 20 is a waveform diagram illustrating the operation of the AND gate of
FIG. 21 is a simplified schematic of an embodiment of a GaN AO I gate. [0026]
FIG. 22 is a simplified schematic of an embodiment of a level shift circuit, for example, for a GaN AO I gate. [0027]
FIG. 23 is a simplified schematic of an embodiment of an AO I logic circuit for a GaN AOI gate. [0028]
FIG. 24 is a simplified schematic of an embodiment of a GaN AO gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN digital circuit, comprising: a substrate comprising GaN; a first output node on the substrate, wherein a voltage at the first output node is configured to switch between first and second voltages, wherein the first voltage is less than the second voltage; a pull up switch on the substrate, the pull up switch comprising: a gate, a source connected to the first output node, and a drain connected to a power supply node having a voltage equal to or substantially equal to the second voltage, wherein the pull up switch is configured to cause a voltage at the first output node to be equal to the second voltage in response to a voltage at the gate; a capacitor on the substrate, the capacitor having a first terminal configured to cause the voltage at the gate to increase to substantially the sum of the second voltage and a third voltage in response to the voltage at the first output node increasing to the second voltage; and a first depletion mode charging switch on the substrate, wherein the first depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage.
The GaN digital circuit of claim 1, wherein the first depletion mode charging switch comprises a gate, wherein the first depletion mode charging switch is configured to cause the voltage at the first terminal of the capacitor to become substantially equal to the second voltage in response to a voltage at the gate of the first depletion mode charging switch being substantially equal to the second voltage.
The GaN digital circuit of claim 1, wherein the second and third voltages are equal.
The GaN digital circuit of claim 1, further comprising a second output node, wherein the second output node is connected to the first terminal of the capacitor.
The GaN digital circuit of claim 1, wherein the first terminal of the capacitor is connected to the gate of the pull up switch through a resistive element.
The GaN digital circuit of claim 1, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to a single input, and the digital circuit performs at least one of a logical inversion and a logical buffer function.
The GaN digital circuit of claim 1, further comprising a second depletion mode charging switch on the substrate, wherein the second depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to first and second inputs, and the digital circuit performs at least one of a logical NOR function and a logical NAND function.
The GaN digital circuit of claim 1 9, wherein the first and second voltages of the second GaN di g ita l log ic circuit are not equal.
A GaN digital circuit, comprising: a substrate comprising GaN; first and second GaN digital logic circuits on the substrate, wherein an output of the first GaN digital logic circuit is electrically connected with an input of the second GaN digital logic circuit, wherein each of the first and second GaN digital logic circuits comprises: a first output node on the substrate, wherein a voltage at the first output node is configured to switch between first and second voltages, wherein the first voltage is less than the second voltage; a pull up switch on the substrate, the pull up switch comprising: a gate, a source connected to the first output node, and a drain connected to a power supply node having a voltage equal to or substantially equal to the second voltage, wherein the pull up switch is configured to cause a voltage at the first output node to be equal to the second voltage in response to a voltage at the gate; a capacitor on the substrate, the capacitor having a first terminal connected to the gate of the pull up switch, wherein the capacitor is configured to cause the voltage at the gate to increase to substantially the sum of the second voltage and a third voltage in response to the voltage at the first output node increasing to the second voltage; and a first depletion mode charging switch on the substrate, wherein the first depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first vo ltag e and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage.
The GaN digital circuit of claim 17, wherein the first GaN digital logic circuit further comprises a second depletion mode char ging switch on the substrate. wherein the second depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second volta g e, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to first and second inputs, wherein the first GaN digital logic circuit performs one of a logical NOR function and a logical NAND function, and wherein the second GaN digital logic circuit performs a logic inversion function.
The GaN digital circuit of claim 17, wherein the first and second voltages of the first GaN digital logic circuit are equal.
Layer stacks claimed or described, ordered top of device to substrate.
GaN digital circuit (single logic gate)
GaN digital circuit (cascaded first and second logic circuits)
GaN inverter 100
GaN inverter 300 with level shift FET and level shift capacitor
Materials described outside the worked examples.
GaN
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,454,481Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of an embodiment of a GaN inverter. [0006]
FIG. 2 is a waveform diagram illustrating the operation of the inverter of
FIG. 3 is a simplified schematic of an embodiment of a GaN inverter. [0008]
FIG. 4 is a waveform diagram illustrating the operation of the inverter of
FIG. 5 is a simplified schematic of an embodiment of a GaN inverter. [0010]
FIG. 6 is a waveform diagram illustrating the operation of the inverter of
FIG. 7 is a simplified schematic of an embodiment of a GaN NOR gate. [0012]
FIG. 8 is a waveform diagram illustrating the operation of the NOR gate of
FIG. 9 is a simplified schematic of an embodiment of a GaN NOR gate. [0014]
FIG. 10 is a waveform diagram illustrating the operation of the NOR gate of
FIG. 11 is a simplified schematic of an embodiment of a GaN NAND gate. [0016]
FIG. 12 is a waveform diagram illustrating the operation of the NAND gate of
FIG. 13 is a simplified schematic of an embodiment of a GaN NAND gate. [0018]
FIG. 14 is a waveform diagram illustrating the operation of the NAND gate of
FIG. 15 is a simplified schematic of an embodiment of a GaN buffer. [0020]
FIG. 16 is a waveform diagram illustrating the operation of the buffer of
FIG. 17 is a simplified schematic of an embodiment of a GaN OR gate. [0022]
FIG. 18 is a waveform diagram illustrating the operation of the OR gate of
FIG. 19 is a simplified schematic of an embodiment of a GaN AND gate. [0024]
FIG. 20 is a waveform diagram illustrating the operation of the AND gate of
FIG. 21 is a simplified schematic of an embodiment of a GaN AO I gate. [0026]
FIG. 22 is a simplified schematic of an embodiment of a level shift circuit, for example, for a GaN AO I gate. [0027]
FIG. 23 is a simplified schematic of an embodiment of an AO I logic circuit for a GaN AOI gate. [0028]
FIG. 24 is a simplified schematic of an embodiment of a GaN AO gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN digital circuit, comprising: a substrate comprising GaN; a first output node on the substrate, wherein a voltage at the first output node is configured to switch between first and second voltages, wherein the first voltage is less than the second voltage; a pull up switch on the substrate, the pull up switch comprising: a gate, a source connected to the first output node, and a drain connected to a power supply node having a voltage equal to or substantially equal to the second voltage, wherein the pull up switch is configured to cause a voltage at the first output node to be equal to the second voltage in response to a voltage at the gate; a capacitor on the substrate, the capacitor having a first terminal configured to cause the voltage at the gate to increase to substantially the sum of the second voltage and a third voltage in response to the voltage at the first output node increasing to the second voltage; and a first depletion mode charging switch on the substrate, wherein the first depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage.
The GaN digital circuit of claim 1, wherein the first depletion mode charging switch comprises a gate, wherein the first depletion mode charging switch is configured to cause the voltage at the first terminal of the capacitor to become substantially equal to the second voltage in response to a voltage at the gate of the first depletion mode charging switch being substantially equal to the second voltage.
The GaN digital circuit of claim 1, wherein the second and third voltages are equal.
The GaN digital circuit of claim 1, further comprising a second output node, wherein the second output node is connected to the first terminal of the capacitor.
The GaN digital circuit of claim 1, wherein the first terminal of the capacitor is connected to the gate of the pull up switch through a resistive element.
The GaN digital circuit of claim 1, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to a single input, and the digital circuit performs at least one of a logical inversion and a logical buffer function.
The GaN digital circuit of claim 1, further comprising a second depletion mode charging switch on the substrate, wherein the second depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to first and second inputs, and the digital circuit performs at least one of a logical NOR function and a logical NAND function.
The GaN digital circuit of claim 1 9, wherein the first and second voltages of the second GaN di g ita l log ic circuit are not equal.
A GaN digital circuit, comprising: a substrate comprising GaN; first and second GaN digital logic circuits on the substrate, wherein an output of the first GaN digital logic circuit is electrically connected with an input of the second GaN digital logic circuit, wherein each of the first and second GaN digital logic circuits comprises: a first output node on the substrate, wherein a voltage at the first output node is configured to switch between first and second voltages, wherein the first voltage is less than the second voltage; a pull up switch on the substrate, the pull up switch comprising: a gate, a source connected to the first output node, and a drain connected to a power supply node having a voltage equal to or substantially equal to the second voltage, wherein the pull up switch is configured to cause a voltage at the first output node to be equal to the second voltage in response to a voltage at the gate; a capacitor on the substrate, the capacitor having a first terminal connected to the gate of the pull up switch, wherein the capacitor is configured to cause the voltage at the gate to increase to substantially the sum of the second voltage and a third voltage in response to the voltage at the first output node increasing to the second voltage; and a first depletion mode charging switch on the substrate, wherein the first depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first vo ltag e and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second voltage.
The GaN digital circuit of claim 17, wherein the first GaN digital logic circuit further comprises a second depletion mode char ging switch on the substrate. wherein the second depletion mode charging switch is configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is equal to or substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is equal to or substantially equal to the second volta g e, wherein the voltage at the first output node is configured to switch between the first and second voltages in response to first and second inputs, wherein the first GaN digital logic circuit performs one of a logical NOR function and a logical NAND function, and wherein the second GaN digital logic circuit performs a logic inversion function.
The GaN digital circuit of claim 17, wherein the first and second voltages of the first GaN digital logic circuit are equal.
Layer stacks claimed or described, ordered top of device to substrate.
GaN digital circuit (single logic gate)
GaN digital circuit (cascaded first and second logic circuits)
GaN inverter 100
GaN inverter 300 with level shift FET and level shift capacitor
Materials described outside the worked examples.
GaN
Related documents with shared materials, methods, properties, or citations.