Patent
Atlas literature
Patent
US 12,224,344 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A is a simplified cross-sectional diagram illustrat- ing a substrate structure at a first stage of fabrication according to an embodiment of the present …
FIG. 2B is a simplified plan view of a set of mask patterns aligned with respect to a substrate plane according to an embodiment of the present invention.
FIG. 3A is a simplified perspective diagram illustrating a hexagonal crystal structure.
FIG. 4 is a plot illustrating variation in threshold voltage as a function of mask pattern alignment with respect to an orientation flat according to an …
FIG. 5 is a simplified flowchart illustrating a method of 5 fabricating a vertical transistor according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising: providing the III-nitride substrate; aligning a mask with respect to the III-nitride substrate; forming a mask layer including a plurality of mask patterns; providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and adjoining a channel region extending between a source region and a drain region; forming a plurality of gate regions in contact with the plurality of gate interface regions; forming a gate electrode coupled to the plurality of gate regions; forming a source electrode coupled to the source region; and forming a drain electrode coupled to the drain region.
The method of claim 1 wherein aligning the mask with respect to the III-nitride substrate comprises: determining an orientation of an alignment reference structure of the III-nitride substrate, wherein the align-ment reference structure defines a reference direction on the III-nitride substrate; and determining the <1210> directions of the III-nitride substrate.
The method of claim 1 wherein each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3°.
The method of claim 1 wherein forming the drain electrode comprises forming a back-side metal electrode on the III-nitride substrate.
The method of claim 1, wherein: forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.
A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising: providing the III-nitride substrate comprising an align-ment reference structure, wherein the alignment refer-ence structure defines a reference direction on the III-nitride substrate; determining <1210> directions of the III-nitride substrate; computing a difference between the reference direction and the <1210> directions to define a correction factor; aligning a mask with respect to the III-nitride substrate using correction factor; forming a mask layer including a plurality of mask patterns; providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and defining a channel region extending between a source region and a drain region; forming a plurality of gate regions in contact with the plurality of gate interface regions; forming a gate electrode coupled to the plurality of gate regions; forming a source electrode coupled to the source region; and forming a drain electrode coupled to the drain region.
The method of claim 9 wherein: each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3°.
The method of claim 9, wherein: forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.
The method of claim 9, wherein: providing the plurality of gate interface regions comprises providing a fin defining the channel region vertically extending between the source region and the drain region.
The method of claim 9, wherein aligning the mask comprises: aligning the mask to the alignment reference structure; and thereafter, re-aligning the mask based on the correction factor.
The method of claim 9, wherein: providing the III-nitride substrate comprises providing the alignment reference structure comprising an orientation flat. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical III-N field effect transistor (FET)
vertical GaN FinFET
Materials described outside the worked examples.
III-nitride (III-N)
gallium nitride (GaN)
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a simplified flowchart illustrating a method of 5 fabricating a vertical transistor according to an embodiment of the present invention.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage shift per degree of sidewall misorientation from m-plane | 0.3 V/0.1° | GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,224,344 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A is a simplified cross-sectional diagram illustrat- ing a substrate structure at a first stage of fabrication according to an embodiment of the present …
FIG. 2B is a simplified plan view of a set of mask patterns aligned with respect to a substrate plane according to an embodiment of the present invention.
FIG. 3A is a simplified perspective diagram illustrating a hexagonal crystal structure.
FIG. 4 is a plot illustrating variation in threshold voltage as a function of mask pattern alignment with respect to an orientation flat according to an …
FIG. 5 is a simplified flowchart illustrating a method of 5 fabricating a vertical transistor according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising: providing the III-nitride substrate; aligning a mask with respect to the III-nitride substrate; forming a mask layer including a plurality of mask patterns; providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and adjoining a channel region extending between a source region and a drain region; forming a plurality of gate regions in contact with the plurality of gate interface regions; forming a gate electrode coupled to the plurality of gate regions; forming a source electrode coupled to the source region; and forming a drain electrode coupled to the drain region.
The method of claim 1 wherein aligning the mask with respect to the III-nitride substrate comprises: determining an orientation of an alignment reference structure of the III-nitride substrate, wherein the align-ment reference structure defines a reference direction on the III-nitride substrate; and determining the <1210> directions of the III-nitride substrate.
The method of claim 1 wherein each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3°.
The method of claim 1 wherein forming the drain electrode comprises forming a back-side metal electrode on the III-nitride substrate.
The method of claim 1, wherein: forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.
A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising: providing the III-nitride substrate comprising an align-ment reference structure, wherein the alignment refer-ence structure defines a reference direction on the III-nitride substrate; determining <1210> directions of the III-nitride substrate; computing a difference between the reference direction and the <1210> directions to define a correction factor; aligning a mask with respect to the III-nitride substrate using correction factor; forming a mask layer including a plurality of mask patterns; providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and defining a channel region extending between a source region and a drain region; forming a plurality of gate regions in contact with the plurality of gate interface regions; forming a gate electrode coupled to the plurality of gate regions; forming a source electrode coupled to the source region; and forming a drain electrode coupled to the drain region.
The method of claim 9 wherein: each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3°.
The method of claim 9, wherein: forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.
The method of claim 9, wherein: providing the plurality of gate interface regions comprises providing a fin defining the channel region vertically extending between the source region and the drain region.
The method of claim 9, wherein aligning the mask comprises: aligning the mask to the alignment reference structure; and thereafter, re-aligning the mask based on the correction factor.
The method of claim 9, wherein: providing the III-nitride substrate comprises providing the alignment reference structure comprising an orientation flat. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical III-N field effect transistor (FET)
vertical GaN FinFET
Materials described outside the worked examples.
III-nitride (III-N)
gallium nitride (GaN)
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a simplified flowchart illustrating a method of 5 fabricating a vertical transistor according to an embodiment of the present invention.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage shift per degree of sidewall misorientation from m-plane | 0.3 V/0.1° | GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,224,344 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A is a simplified cross-sectional diagram illustrat- ing a substrate structure at a first stage of fabrication according to an embodiment of the present …
FIG. 2B is a simplified plan view of a set of mask patterns aligned with respect to a substrate plane according to an embodiment of the present invention.
FIG. 3A is a simplified perspective diagram illustrating a hexagonal crystal structure.
FIG. 4 is a plot illustrating variation in threshold voltage as a function of mask pattern alignment with respect to an orientation flat according to an …
FIG. 5 is a simplified flowchart illustrating a method of 5 fabricating a vertical transistor according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising: providing the III-nitride substrate; aligning a mask with respect to the III-nitride substrate; forming a mask layer including a plurality of mask patterns; providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and adjoining a channel region extending between a source region and a drain region; forming a plurality of gate regions in contact with the plurality of gate interface regions; forming a gate electrode coupled to the plurality of gate regions; forming a source electrode coupled to the source region; and forming a drain electrode coupled to the drain region.
The method of claim 1 wherein aligning the mask with respect to the III-nitride substrate comprises: determining an orientation of an alignment reference structure of the III-nitride substrate, wherein the align-ment reference structure defines a reference direction on the III-nitride substrate; and determining the <1210> directions of the III-nitride substrate.
The method of claim 1 wherein each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3°.
The method of claim 1 wherein forming the drain electrode comprises forming a back-side metal electrode on the III-nitride substrate.
The method of claim 1, wherein: forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.
A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising: providing the III-nitride substrate comprising an align-ment reference structure, wherein the alignment refer-ence structure defines a reference direction on the III-nitride substrate; determining <1210> directions of the III-nitride substrate; computing a difference between the reference direction and the <1210> directions to define a correction factor; aligning a mask with respect to the III-nitride substrate using correction factor; forming a mask layer including a plurality of mask patterns; providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and defining a channel region extending between a source region and a drain region; forming a plurality of gate regions in contact with the plurality of gate interface regions; forming a gate electrode coupled to the plurality of gate regions; forming a source electrode coupled to the source region; and forming a drain electrode coupled to the drain region.
The method of claim 9 wherein: each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3°.
The method of claim 9, wherein: forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.
The method of claim 9, wherein: providing the plurality of gate interface regions comprises providing a fin defining the channel region vertically extending between the source region and the drain region.
The method of claim 9, wherein aligning the mask comprises: aligning the mask to the alignment reference structure; and thereafter, re-aligning the mask based on the correction factor.
The method of claim 9, wherein: providing the III-nitride substrate comprises providing the alignment reference structure comprising an orientation flat. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical III-N field effect transistor (FET)
vertical GaN FinFET
Materials described outside the worked examples.
III-nitride (III-N)
gallium nitride (GaN)
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a simplified flowchart illustrating a method of 5 fabricating a vertical transistor according to an embodiment of the present invention.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage shift per degree of sidewall misorientation from m-plane | 0.3 V/0.1° | GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,224,344 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A is a simplified cross-sectional diagram illustrat- ing a substrate structure at a first stage of fabrication according to an embodiment of the present …
FIG. 2B is a simplified plan view of a set of mask patterns aligned with respect to a substrate plane according to an embodiment of the present invention.
FIG. 3A is a simplified perspective diagram illustrating a hexagonal crystal structure.
FIG. 4 is a plot illustrating variation in threshold voltage as a function of mask pattern alignment with respect to an orientation flat according to an …
FIG. 5 is a simplified flowchart illustrating a method of 5 fabricating a vertical transistor according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising: providing the III-nitride substrate; aligning a mask with respect to the III-nitride substrate; forming a mask layer including a plurality of mask patterns; providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and adjoining a channel region extending between a source region and a drain region; forming a plurality of gate regions in contact with the plurality of gate interface regions; forming a gate electrode coupled to the plurality of gate regions; forming a source electrode coupled to the source region; and forming a drain electrode coupled to the drain region.
The method of claim 1 wherein aligning the mask with respect to the III-nitride substrate comprises: determining an orientation of an alignment reference structure of the III-nitride substrate, wherein the align-ment reference structure defines a reference direction on the III-nitride substrate; and determining the <1210> directions of the III-nitride substrate.
The method of claim 1 wherein each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3°.
The method of claim 1 wherein forming the drain electrode comprises forming a back-side metal electrode on the III-nitride substrate.
The method of claim 1, wherein: forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.
A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising: providing the III-nitride substrate comprising an align-ment reference structure, wherein the alignment refer-ence structure defines a reference direction on the III-nitride substrate; determining <1210> directions of the III-nitride substrate; computing a difference between the reference direction and the <1210> directions to define a correction factor; aligning a mask with respect to the III-nitride substrate using correction factor; forming a mask layer including a plurality of mask patterns; providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and defining a channel region extending between a source region and a drain region; forming a plurality of gate regions in contact with the plurality of gate interface regions; forming a gate electrode coupled to the plurality of gate regions; forming a source electrode coupled to the source region; and forming a drain electrode coupled to the drain region.
The method of claim 9 wherein: each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3°.
The method of claim 9, wherein: forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.
The method of claim 9, wherein: providing the plurality of gate interface regions comprises providing a fin defining the channel region vertically extending between the source region and the drain region.
The method of claim 9, wherein aligning the mask comprises: aligning the mask to the alignment reference structure; and thereafter, re-aligning the mask based on the correction factor.
The method of claim 9, wherein: providing the III-nitride substrate comprises providing the alignment reference structure comprising an orientation flat. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical III-N field effect transistor (FET)
vertical GaN FinFET
Materials described outside the worked examples.
III-nitride (III-N)
gallium nitride (GaN)
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a simplified flowchart illustrating a method of 5 fabricating a vertical transistor according to an embodiment of the present invention.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage shift per degree of sidewall misorientation from m-plane | 0.3 V/0.1° | GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
