Patent
US 10,943,836GALLIUM NITRIDE NMOS ON SI (111) CO-INTEGRATED WITH A SILICON PMOS
Marko Radosavljevic
US
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US 10,943,836Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
FIG. 2 is a schematic illustration of a stereographic representation of a silicon 111 wafer and notch locations in accordance with embodiments of the present …
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 4 is a schematic diagram of a perspective view of a silicon 111 substrate showing crystal structure directions in accordance with embodiments of the …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
FIG. 9 is an interposer implementing one or more embodiments of the invention in accordance with embodiments of the present disclosure. [15]
FIG. 10 is a computing device built in accordance with an embodiment of the invention in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus, comprising: a support structure comprising a silicon material; a trench in the support structure, the trench having sidewalls and a bottom, where the trench includes an island of the silicon material extending from a portion of the bottom of the trench; a semiconductor material comprising gallium and nitrogen, the semiconductor material provided in a portion of the trench that is closest to the bottom of the trench so that the semiconductor material encloses sidewalls and a top side of the island; and a transistor having a channel portion, the channel portion including a portion of the semiconductor material. Original
The apparatus according to claim 1, wherein a long axis of the island is in a [11-2] direction of the silicon material. Original
The apparatus according to claim 1, wherein the top side of the island has a 111 orientation of the silicon material. Original
The apparatus according to claim 1, wherein at least one of the sidewalls of the island has a 110 orientation of the silicon material. Original
The apparatus according to claim 1, wherein the bottom of the trench has a 111 orientation of the silicon material. Original
The apparatus according to claim 1, wherein the channel portion of the transistor is in the trench. Original
The apparatus according to claim 1, wherein each of a source region and a drain region of the transistor is in the trench. Original
The apparatus according to claim 1, further comprising a silicon layer over the semiconductor material, the silicon layer comprising silicon or polysilicon. Original
The apparatus according to claim 1, wherein the transistor is an N-type transistor. Original
The apparatus according to claim 1, wherein the support structure is a silicon 111 substrate. Original
The apparatus according to claim 1, wherein the apparatus is one of a switch, a voltage regulator, and a power amplifier. Original
The method according to claim 1, further comprising forming an island of a silicon material at a bottom of the trench, wherein a first portion of the semiconductor material in the trench is over the bottom of the trench and a second portion of the semiconductor material is over the island. Withdrawn
An apparatus, comprising: a support structure comprising a silicon material; a trench in the support structure; a semiconductor material comprising ga ll ium and nitrogen, the semiconductor material being in a portion of the trench that is closest to a bottom of the trench; a transistor having a channel portion that includes a portion of the semiconductor material; and a silicon layer, provided in the trench so that the semiconductor material is between the silicon layer and the bottom of the trench, the silicon layer comprising silicon or polysilicon. Original
The apparatus according to claim 16, wherein the transistor is an N-type transistor, and the apparatus further includes a P-type transistor having a channel portion that includes a portion of the silicon material. Original
The apparatus according to claim 16, wherein the apparatus is one of a switch, a voltage regulator, and a power amplifier. Original
A method for forming a semiconductor device on a silicon substrate, the method comprising: forming a trench in the silicon substrate; providing a semiconductor material in the trench, the semiconductor material comprising gallium and nitrogen; forming a first transistor, the first transistor having a channel portion that includes a portion of the semiconductor material; and forming a second transistor, the second transistor having a channel portion that includes a portion of the silicon substrate. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor in trench
Si PMOS transistor
CMOS device (GaN NMOS + Si PMOS)
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,943,836Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
FIG. 2 is a schematic illustration of a stereographic representation of a silicon 111 wafer and notch locations in accordance with embodiments of the present …
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 4 is a schematic diagram of a perspective view of a silicon 111 substrate showing crystal structure directions in accordance with embodiments of the …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
FIG. 9 is an interposer implementing one or more embodiments of the invention in accordance with embodiments of the present disclosure. [15]
FIG. 10 is a computing device built in accordance with an embodiment of the invention in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus, comprising: a support structure comprising a silicon material; a trench in the support structure, the trench having sidewalls and a bottom, where the trench includes an island of the silicon material extending from a portion of the bottom of the trench; a semiconductor material comprising gallium and nitrogen, the semiconductor material provided in a portion of the trench that is closest to the bottom of the trench so that the semiconductor material encloses sidewalls and a top side of the island; and a transistor having a channel portion, the channel portion including a portion of the semiconductor material. Original
The apparatus according to claim 1, wherein a long axis of the island is in a [11-2] direction of the silicon material. Original
The apparatus according to claim 1, wherein the top side of the island has a 111 orientation of the silicon material. Original
The apparatus according to claim 1, wherein at least one of the sidewalls of the island has a 110 orientation of the silicon material. Original
The apparatus according to claim 1, wherein the bottom of the trench has a 111 orientation of the silicon material. Original
The apparatus according to claim 1, wherein the channel portion of the transistor is in the trench. Original
The apparatus according to claim 1, wherein each of a source region and a drain region of the transistor is in the trench. Original
The apparatus according to claim 1, further comprising a silicon layer over the semiconductor material, the silicon layer comprising silicon or polysilicon. Original
The apparatus according to claim 1, wherein the transistor is an N-type transistor. Original
The apparatus according to claim 1, wherein the support structure is a silicon 111 substrate. Original
The apparatus according to claim 1, wherein the apparatus is one of a switch, a voltage regulator, and a power amplifier. Original
The method according to claim 1, further comprising forming an island of a silicon material at a bottom of the trench, wherein a first portion of the semiconductor material in the trench is over the bottom of the trench and a second portion of the semiconductor material is over the island. Withdrawn
An apparatus, comprising: a support structure comprising a silicon material; a trench in the support structure; a semiconductor material comprising ga ll ium and nitrogen, the semiconductor material being in a portion of the trench that is closest to a bottom of the trench; a transistor having a channel portion that includes a portion of the semiconductor material; and a silicon layer, provided in the trench so that the semiconductor material is between the silicon layer and the bottom of the trench, the silicon layer comprising silicon or polysilicon. Original
The apparatus according to claim 16, wherein the transistor is an N-type transistor, and the apparatus further includes a P-type transistor having a channel portion that includes a portion of the silicon material. Original
The apparatus according to claim 16, wherein the apparatus is one of a switch, a voltage regulator, and a power amplifier. Original
A method for forming a semiconductor device on a silicon substrate, the method comprising: forming a trench in the silicon substrate; providing a semiconductor material in the trench, the semiconductor material comprising gallium and nitrogen; forming a first transistor, the first transistor having a channel portion that includes a portion of the semiconductor material; and forming a second transistor, the second transistor having a channel portion that includes a portion of the silicon substrate. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor in trench
Si PMOS transistor
CMOS device (GaN NMOS + Si PMOS)
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,943,836Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
FIG. 2 is a schematic illustration of a stereographic representation of a silicon 111 wafer and notch locations in accordance with embodiments of the present …
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 4 is a schematic diagram of a perspective view of a silicon 111 substrate showing crystal structure directions in accordance with embodiments of the …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
FIG. 9 is an interposer implementing one or more embodiments of the invention in accordance with embodiments of the present disclosure. [15]
FIG. 10 is a computing device built in accordance with an embodiment of the invention in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus, comprising: a support structure comprising a silicon material; a trench in the support structure, the trench having sidewalls and a bottom, where the trench includes an island of the silicon material extending from a portion of the bottom of the trench; a semiconductor material comprising gallium and nitrogen, the semiconductor material provided in a portion of the trench that is closest to the bottom of the trench so that the semiconductor material encloses sidewalls and a top side of the island; and a transistor having a channel portion, the channel portion including a portion of the semiconductor material. Original
The apparatus according to claim 1, wherein a long axis of the island is in a [11-2] direction of the silicon material. Original
The apparatus according to claim 1, wherein the top side of the island has a 111 orientation of the silicon material. Original
The apparatus according to claim 1, wherein at least one of the sidewalls of the island has a 110 orientation of the silicon material. Original
The apparatus according to claim 1, wherein the bottom of the trench has a 111 orientation of the silicon material. Original
The apparatus according to claim 1, wherein the channel portion of the transistor is in the trench. Original
The apparatus according to claim 1, wherein each of a source region and a drain region of the transistor is in the trench. Original
The apparatus according to claim 1, further comprising a silicon layer over the semiconductor material, the silicon layer comprising silicon or polysilicon. Original
The apparatus according to claim 1, wherein the transistor is an N-type transistor. Original
The apparatus according to claim 1, wherein the support structure is a silicon 111 substrate. Original
The apparatus according to claim 1, wherein the apparatus is one of a switch, a voltage regulator, and a power amplifier. Original
The method according to claim 1, further comprising forming an island of a silicon material at a bottom of the trench, wherein a first portion of the semiconductor material in the trench is over the bottom of the trench and a second portion of the semiconductor material is over the island. Withdrawn
An apparatus, comprising: a support structure comprising a silicon material; a trench in the support structure; a semiconductor material comprising ga ll ium and nitrogen, the semiconductor material being in a portion of the trench that is closest to a bottom of the trench; a transistor having a channel portion that includes a portion of the semiconductor material; and a silicon layer, provided in the trench so that the semiconductor material is between the silicon layer and the bottom of the trench, the silicon layer comprising silicon or polysilicon. Original
The apparatus according to claim 16, wherein the transistor is an N-type transistor, and the apparatus further includes a P-type transistor having a channel portion that includes a portion of the silicon material. Original
The apparatus according to claim 16, wherein the apparatus is one of a switch, a voltage regulator, and a power amplifier. Original
A method for forming a semiconductor device on a silicon substrate, the method comprising: forming a trench in the silicon substrate; providing a semiconductor material in the trench, the semiconductor material comprising gallium and nitrogen; forming a first transistor, the first transistor having a channel portion that includes a portion of the semiconductor material; and forming a second transistor, the second transistor having a channel portion that includes a portion of the silicon substrate. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor in trench
Si PMOS transistor
CMOS device (GaN NMOS + Si PMOS)
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,943,836Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
FIG. 2 is a schematic illustration of a stereographic representation of a silicon 111 wafer and notch locations in accordance with embodiments of the present …
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 4 is a schematic diagram of a perspective view of a silicon 111 substrate showing crystal structure directions in accordance with embodiments of the …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
FIG. 9 is an interposer implementing one or more embodiments of the invention in accordance with embodiments of the present disclosure. [15]
FIG. 10 is a computing device built in accordance with an embodiment of the invention in accordance with embodiments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus, comprising: a support structure comprising a silicon material; a trench in the support structure, the trench having sidewalls and a bottom, where the trench includes an island of the silicon material extending from a portion of the bottom of the trench; a semiconductor material comprising gallium and nitrogen, the semiconductor material provided in a portion of the trench that is closest to the bottom of the trench so that the semiconductor material encloses sidewalls and a top side of the island; and a transistor having a channel portion, the channel portion including a portion of the semiconductor material. Original
The apparatus according to claim 1, wherein a long axis of the island is in a [11-2] direction of the silicon material. Original
The apparatus according to claim 1, wherein the top side of the island has a 111 orientation of the silicon material. Original
The apparatus according to claim 1, wherein at least one of the sidewalls of the island has a 110 orientation of the silicon material. Original
The apparatus according to claim 1, wherein the bottom of the trench has a 111 orientation of the silicon material. Original
The apparatus according to claim 1, wherein the channel portion of the transistor is in the trench. Original
The apparatus according to claim 1, wherein each of a source region and a drain region of the transistor is in the trench. Original
The apparatus according to claim 1, further comprising a silicon layer over the semiconductor material, the silicon layer comprising silicon or polysilicon. Original
The apparatus according to claim 1, wherein the transistor is an N-type transistor. Original
The apparatus according to claim 1, wherein the support structure is a silicon 111 substrate. Original
The apparatus according to claim 1, wherein the apparatus is one of a switch, a voltage regulator, and a power amplifier. Original
The method according to claim 1, further comprising forming an island of a silicon material at a bottom of the trench, wherein a first portion of the semiconductor material in the trench is over the bottom of the trench and a second portion of the semiconductor material is over the island. Withdrawn
An apparatus, comprising: a support structure comprising a silicon material; a trench in the support structure; a semiconductor material comprising ga ll ium and nitrogen, the semiconductor material being in a portion of the trench that is closest to a bottom of the trench; a transistor having a channel portion that includes a portion of the semiconductor material; and a silicon layer, provided in the trench so that the semiconductor material is between the silicon layer and the bottom of the trench, the silicon layer comprising silicon or polysilicon. Original
The apparatus according to claim 16, wherein the transistor is an N-type transistor, and the apparatus further includes a P-type transistor having a channel portion that includes a portion of the silicon material. Original
The apparatus according to claim 16, wherein the apparatus is one of a switch, a voltage regulator, and a power amplifier. Original
A method for forming a semiconductor device on a silicon substrate, the method comprising: forming a trench in the silicon substrate; providing a semiconductor material in the trench, the semiconductor material comprising gallium and nitrogen; forming a first transistor, the first transistor having a channel portion that includes a portion of the semiconductor material; and forming a second transistor, the second transistor having a channel portion that includes a portion of the silicon substrate. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor in trench
Si PMOS transistor
CMOS device (GaN NMOS + Si PMOS)
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic diagram of a communications device that includes a gallium nitride transistor formed on a silicon 111 substrate in accordance with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Related documents with shared materials, methods, properties, or citations.
silicon or polysilicon layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
| — |
Thickness | 130–150 nm | — |
Thickness | 60–80 nm | — |
Thickness | 400–440 nm | — |
Thickness | 70–90 nm | — |
Thickness | 30–50 nm | — |
Thickness | 85–115 nm | — |
Thickness | 180–220 nm | — |
Thickness | 20–40 nm | — |
Thickness | 125–175 nm | — |
Thickness | 35–65 nm | — |
silicon or polysilicon layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
| — |
Thickness | 130–150 nm | — |
Thickness | 60–80 nm | — |
Thickness | 400–440 nm | — |
Thickness | 70–90 nm | — |
Thickness | 30–50 nm | — |
Thickness | 85–115 nm | — |
Thickness | 180–220 nm | — |
Thickness | 20–40 nm | — |
Thickness | 125–175 nm | — |
Thickness | 35–65 nm | — |
silicon or polysilicon layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
| — |
Thickness | 130–150 nm | — |
Thickness | 60–80 nm | — |
Thickness | 400–440 nm | — |
Thickness | 70–90 nm | — |
Thickness | 30–50 nm | — |
Thickness | 85–115 nm | — |
Thickness | 180–220 nm | — |
Thickness | 20–40 nm | — |
Thickness | 125–175 nm | — |
Thickness | 35–65 nm | — |
silicon or polysilicon layer
FIG. 3 is a schematic illustration of a gallium nitride transistor formed on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 5A-5F are schematic diagrams for forming a gallium nitride transistor on a silicon 111 substrate in accordance with embodiments of the present disclosure. …
FIG. 6A is a schematic diagram of a cross sectional view of a gallium nitride NMOS transistor on a silicon substrate and two silicon PMOS transistors formed on …
FIG. 7A-7C are schematic diagrams for forming trench contacts for the gallium nitride transistor and for forming trench contacts to form a silicon PMOS …
FIGS. 8A-8D are schematic diagrams for a process flow for forming trench contacts on silicon 111 for the silicon transistor. [14]
| — |
Thickness | 130–150 nm | — |
Thickness | 60–80 nm | — |
Thickness | 400–440 nm | — |
Thickness | 70–90 nm | — |
Thickness | 30–50 nm | — |
Thickness | 85–115 nm | — |
Thickness | 180–220 nm | — |
Thickness | 20–40 nm | — |
Thickness | 125–175 nm | — |
Thickness | 35–65 nm | — |