Patent
US 10,475,913EPITAXIAL STRUCTURE OF N-FACE AlGaN/GaN, ACTIVE DEVICE, AND METHOD FOR FABRICATING THE SAME WITH INTEGRATION AND POLARITY INVERSION
CHIH-SHU HUANG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,475,913Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows distributions of E P s and E Pz in Ga-face and N-face A l GaN/GaN and GaN/InGaN systems in d iff erent stains according to the present invention;
FIG. 2 shows a schematic diagram of Ga-face and N-face GaN grown on a substrate;
FIG. 3 shows a schematic diagram of the d if ferent locations of 2DEG generated at the junctions between A I GaN and G aN due to different polarization …
FIG. 4B ~ 4D show the operations of the SEG p-GaN gate E-m o de N-face AIGaN/GaN HEMT with polarity inversion at a fixed Vd and va r ying gate voltages Vg …
FIG. 5 B shows a second structure diagram of the epitaxial structure of the N-face AI GaN/GaN HEMT acc o rding to the present i nvent ion;
FIG. 6A-2 sh ow cr o ss-sectional views of the SEG p-GaN gate E-mode N-face A l GaN/GaN HE M T with polarity inversion according to the present invention;
FIG. 7E-2 sh ow schematic diagrams of f o rming the metal gate electrode and the bonding pads and interconnection metals f or drain and source in the SEG p-GaN …
FIG. 8A-2 show c ross-sectional views of the SEG p-GaN anode N-face A l GaN/GaN SBD with polarity inversion according to the present invention;
FIG. 9A shows an equivalent circuit diagram of a hybrid E-mode N-face A l GaN/GaN HEMT with p o larity inversi o n f o rmed by casc o ding an SEG E-m o de …
FIG. 10 A shows a schematic diagram of the equivalent circuit in
FIG. 11 A-2; Figures 12A to 12F-2 show schematic diagrams of the process steps f o r fabricating the structures in F I G. 11A-1 and F I G. 11 A-2 according to …
FIG. 12C. Next, use destructive io n implantat io n as sh own i n
FIG. 13A-2; Figures 1 4A-1 to 1 4 A-4 show schematic diagrams o f the process steps for fabricating the structures in
FIG. 15 shows an equivalent circuit diagram o f a hybrid N-face A l GaN/GaN SBD with polarity inversion f ormed by cascoding an SEG p-GaN anode N-face Al …
FIG. 16B sh o ws a t o p view of
FIG. 17B shows a t o p view o f
FIG. 18A-2 sh ow cr o ss-sectional views of the SEG p-GaN gate and self-aligned gate metal E-mo de G -face A l GaN/GaN HEMT with polarity inversion according …
FIG. 19A. First, use PECVD to deposit a layer of Si O₂ mas k 105 as a buffer layer. Thereby, during i on implantation, the peak value of the Gaussian …
FIG. 20A-2 show cr o ss-sectional views of the SEG p-GaN anode and self-aligned gate m etal E- mo de N-face A IG aN/G aN SBD with polarity inversion according …
FIG. 21A-2 show c ross-sectional views of the hybrid E -mode N-face AI GaN/GaN HEMT with polarity inversion according to the present invention;
FIG. 22G-2 show cro ss-sectional views of the process steps f o r
FIG. 23A-2 show cross-sectional views of the hybrid E- m ode N-face AIG aN/G aN HEMT with polarity inversion according to the present invention;
FIG. 24B-2 show cro ss-sectional views of the process steps f o r Figures 23A- 1 and 23A-2;
FIG. 26A- 1 and F I G. 26A-2 show cross-sectional views of the hybrid N- face Al GaN/GaN SBD with polarity inversion according to the present invention; and FI …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The structure of claim 1, wherein an i-A l z GaN grading buffer layer is further disposed between said C-doped i-GaN layer and said i-A ly GaN buffer layer and z=0.01 ~0.75.
A method for fabricating an enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion using said epitaxial structure of claim 1, comprising steps of: providing an epitaxia l structure of N-face AIGaN/GaN; and forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face A l GaN/GaN using selective epitaxial growth for controlling the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A i X GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of clai m 3, and in said step of forming said p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN, further comprising steps of: forming a silicon oxynitride mask layer on said epitaxial structure of N-face AI GaN/GaN; exposing and developing said silicon oxynitride mask layer for defining a gate selective epitaxial growth region; etching said gate selective epitaxial growth region using buffered oxide etchant for forming an inverted trapezoidal structure; growing p-GaN in said inverted trapezoidal structure for forming said p-GaN inverted trapezoidal gate structure; and removing said silicon oxynitride mask layer.
A selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of AI GaN/G aN; and a p-GaN inverted trapezoidal gate structure, located on an i-A l x GaN layer; where the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure is depleted, and said epitaxial structure of N-face AI GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i- C aN channel layer, located on said i-A ly GaN buffer layer; and said i-A l X GaN layer, located on said i-GaN channel layer; where x= O.1~0.3; y= 0.05-0.75.
A method for fabricating a hybrid enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion using said epitaxial structure of claim 1, comprising steps of: providing an epitaxial structure of N-face AlGaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right re gion; forming a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion in said left region by steps comprising: forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN using selective epitaxial growth for controlling the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; and forming a depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer in said right region; where said epitaxial structure of N-face A I GaN/GaN co m prises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-Al y GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A I X GaN layer, located on said i-GaN channel layer; where x= 0.10.3; y= 0.05~0.75.
The method of claim 6, wherein said selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion and said depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer are fabricated concurrent ly.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of N-face A I GaN/GaN, divided into a left region and a right region; a selective-epitaxia l -growth p-GaN gate enhancement-mode N-face Al GaN/GaN high electron mobi l ity transistor with polarity inversion, located in said left region, comprising a p-GaN inverted trapezoidal gate structure, and the two-dimensional electron gas below said p- GaN inverted trapezoidal gate structure being depleted; and a depletion-m o de N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer, located in said right region; where said epitaxial structure of N-face AlGaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A lyG aN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A lx GaN layer, located on said i-GaN channel layer; where x =0.1-0.3; y =0.05~0.75.
A method for fabricating a hybrid enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion, comprising steps of: providing an epitaxial structure of N-face A t GaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right region; forming a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion in said left region by steps comprising: forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN using selective epitaxial growth for control l ing the 38 two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; and forming a depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and gate dielectric layer in said right region; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i- C aN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= O.1~0.3; y= 0.050.75.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of N-face A l GaN/GaN, divided into a left region and a right region; a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion, located in said left region, comprising a p-GaN inverted trapezoidal gate structure, and the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure being depleted; and a depletion-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion and gate dielectric layer, located in said right region; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
11. A method for fabricating a selective-epitaxial-growth p-GaN gate enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion, comprising steps o f: providing an epitaxial structure of N-face AIGaN/GaN; forming a first source ion implantation region and a first drain ion implantation region in said i-A h x GaN layer; forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face A l GaN/GaN using selective epitaxial growth; forming a f irst gate metal layer on said p-GaN inverted trapezoidal gate structure; and forming a first source metal layer and a f i rst drain metal layer on said epitaxia l structure of N-face A l GaN/GaN, said first source meta l layer located on said first source ion implantation region, and said first drain metal layer located on said first drain ion implantation region; where said epitaxial structure of N-face A I GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A iy GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of claim 11, and in said steps of forming said p-GaN inverted trapezoidal gate structure and said first gate metal layer, further comprising steps o f: forming a silicon oxynitride mas k layer on said epitaxia l structure of N-face AI GaN/GaN; fo rming an inverted trapez o idal structure by patterning said si licon o xynitride mask layer using a patterned photoresist layer and buffered oxide etchant; grow ing p-GaN in said inverted trapez o idal structure f o r f o rming said p-GaN inverted trapezoidal gate structure; fo rming a f ir st metal layer o n the surfaces of sa i d s ilicon o xynitride mas k layer and said p-GaN inverted trapezoidal gate structure; and removing said silicon oxynitride mask layer and said metal layer on said silicon o xynitride mas k layer, and reserving the fi rst metal layer o n the surface of said p-GaN inverted trapezoidal gate structure for acting as said first gate metal layer.
The meth o d of claim 1 1, and in said step of f o rming said first s o urc e ion implantation region and said first drain ion implantation region in said i-A X GaN layer, further comprising steps of: forming an ion implantation buffer layer on said epitaxial structure of N-face A₁ GaN/GaN; fo rming a patterned ph oto resist layer o n said i o n implantation buffer layer and exposing a portion of said ion implantation buffer layer; doping n-type si lico n to said i o n implantation buffer l ayer expo sed fro m said patterned photoresist layer and activating f or fo rmi ng said first source ion implantation region and said first drain i o n implantation region in said i-A l X GaN layer; and removing said patterned photoresist layer and said ion implantation buffer layer.
The method of claim 13, wherein said activation is performed by a thermal treatment at a te m perature between 6 00 and 9 000 SVG 16124596.09-07-2018.JLSAAS₁BRXEAPX3.CLM.7.24.1519.2515.1547.2549.svg 0.113 0.093 Chemistry Black and white
15. A selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxia l structure of N-face AIGaN/GaN; a p-GaN inverted trap ezo idal gate structure, a fi rst s o urce metal layer, and a first drain metal layer, located on said i-A l X GaN layer, and the two-dimensional electr o n gas b elo w said p-GaN inverted trap ezo idal gate structure being depleted; a fir st s o urce io n implantat io n reg io n and a first dra in ion i mplantati o n reg ion, located in said i-A l X GaN layer, said first s o urce ion implantation region located below said fir st source metal layer, and said fir st drain ion im plantati o n regi o n l o cated below said first drain metal layer; and a first gate metal layer, located on said p-GaN inverted trapezoidal gate structu re; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i -GaN layer, l o cated o n said C-doped buffer layer; an i-A l y GaN buffer layer, located o n said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN bu ff er layer; and an i-A l X GaN layer, l o cated o n said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
A method for fabricating a hybrid enhancement-mode N-face A l GaN/GaN high electr o n mobility transistor with polarity inversion, comprising steps of: providing an epitaxial structure o f N-face A l GaN/GaN, and dividing said epitaxial structure of N-face A L GaN/GaN into a l eft region and a right region; forming a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A IG aN/GaN high electr on mo bility transistor with polarity inversion in said left region by steps comprising: fo rming a first s o urce i o n implantation regi o n and a first drain i on implantation region in said i-A l X GaN layer; fo rming a p-GaN inverted trapezoidal gate structure o n said epitaxial structure of N-face A lG aN/GaN using selective epitaxial growth and 42 the two-di m ensi o nal electr o n gas below said p-GaN inverted trapezoidal gate structure being depleted; fo rming a first gate metal layer o n said p-GaN inverted trapezoidal gate structure; and fo rming a first source metal layer and a f ir st drain metal layer o n sa id epitaxial structure of A l GaN/GaN, said first source metal layer located on said f ir st source ion implantation region, and said first drain m etal layer located o n said fi rst drain i o n i m plantation regi on; and fo rming a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and without gate dielectric layer in said right regi o n by steps comprising: forming a second source ion implantation region and a second drain ion i mplantati o n regi on i n said i-Al x GaN layer; and forming a second source metal layer and a second drain metal layer on said epitaxial structure of N-face A I GaN/GaN, said second source metal layer located o n said sec o nd s o urce i o n i m plantation regi on, and said second drain metal layer located on said second drain ion SVG 16124596.09-07-2018.JLSAAS₁BRXEAPX3.CLM.9.19.755.1897.804.1931.svg 0.113 0.163 Chemistry Black and white m plantati o n regi on; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN l ayer, l ocated on said C-doped buffer l ayer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A l x G aN layer, located o n said i- G aN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of claim 16, and in said step of forming said first source ion implantation regi o n, said first drain i o n implantation regi o n, said sec o nd s o urce io n implantation regi o n, and said sec o nd drain i o n implantation regi o n in said 43 i-A lx GaN layer, further c o mprising steps of: forming an ion implantation buffer layer on said epitaxial structure of N-face Al GaN/GaN; forming a patterned photoresist layer on said ion implantation buffer layer and expos i ng a portion of said ion i mplantat io n buffer layer; doping n-type silicon to said ion implantation buffer layer exposed from said patterned photoresist layer and activating for forming said first source ion implantati o n regi o n, said fi rst drain i o n implantati o n regi o n, said sec ond source ion implantation region, and said second drain ion implantation regi o n in said i-A l X GaN layer; and removing said patterned photoresist layer and said ion implantation buffer l ayer.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, c o mprising: an epitaxial structure of N-face A l GaN/GaN, divided into a left region and a right regi on; a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A l GaN/GaN high electron mobility transistor with polarity inversion, l ocated in said left region, comprising: a p-GaN inverted trapezoidal gate structure, a fi rst source metal layer, and a first drain metal layer, l ocated on said i-A l X GaN layer, and the two-dimensional electron gas below said p-GaN inverted trapezoida l gate structure being depleted; a first source ion implantation region and a first drain ion implantation regi o n, located in said i-A lx GaN layer, said first source i on implantation region located below said first source metal layer, and said first drain i o n implantation regi o n located below said first drain metal layer; and a f irst gate metal layer, l o cated o n said p-GaN inverted trapezoidal gate structure; and a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and without gate dielectric layer, located in said right reg io n, comprising: a second source metal layer and a second drain metal layer, located on said i-A l x GaN layer; and a sec o nd s o urce i o n i m plantati o n regi o n and a sec o nd drain i on implantation regi o n, located in said i-A l x GaN layer, said sec ond so urce i o n implantati o n regi o n l o cated below said sec o nd s o urce metal layer, and said sec o nd drain i o n implantati o n regi o n l o cated below said sec o nd drain metal layer; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, l o cated on said C-doped bu ff er layer; an i-A lyG aN buffer layer, l o cated o n said C-doped i-GaN layer; an i-GaN channel layer, l o cated on said i-Al y GaN buffer layer; and an i-A lx GaN layer, l o cated o n said i-GaN channel layer; where x =0.1~ 0.3; y =0.05~0.75.
A method f o r fabricating a hybrid enhancement-m o de N-face A l GaN/GaN high electr o n mobility transistor with polarity inversion, c om prising steps of: providing an epitaxial structure of N-face A t GaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right regi on; forming a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion in said left region by steps comprising: fo rming a f irst s o urce i o n implantati o n regi o n and a f irst drain i on implantati o n regi o n in said i-A l x GaN layer; fo rming a p-GaN inverted trapezoidal gate structure o n said epitaxia l structure of N-face A l GaN/GaN using selective epitaxial growth and the two-dimensional electr o n gas below said p-GaN inverted trapezoidal gate structure being depleted; fo rming a fir st gate metal layer o n sa i d p-GaN i nverted trapez oi dal gate structure; and forming a first source metal layer and a fi rst drain metal layer o n said epitaxial structure of N-face A IG aN/G aN, said fi rst s o urce metal layer located on said first source ion implantation regi o n, and said first drain metal layer l o cated o n said first drain i o n implantati on region; and fo rming a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and gate dielectric layer in said right region by steps comprising: forming a second source ion implantation region and a second drain ion implantation region in said i-A lx GaN layer; fo rming a sec o nd s o urce metal layer and a sec o nd drain metal layer on said epitaxial structure of N-face A l GaN/GaN, said second source metal layer l o cated o n said sec o nd s o urce i o n implantati o n regi on, and said second drain metal layer located on said second drain ion implantati o n regi o n; and forming a gate dielectric layer on said epitaxial structure of N-face AI GaN/GaN; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-d o ped buffer layer, l o cated o n said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, l o cated o n said C-d o ped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A l X GaN layer, l o cated o n said i-GaN channel layer; where x= 0.10.3; y= 0.05~0.75.
The method of claim 20, and in said step of forming said first source ion implantati o n regi o n, said first drain i o n implantati o n regi o n, said sec o nd s o urce ion implantation region, and said second drain ion implantation region in said i-Alx GaN layer, further comprising steps of: fo rming an i o n implantation buffer layer o n said epitaxial structure o f N-face Al GaN/GaN; fo rming a patterned ph oto resist layer o n said i o n implantati o n bu ff er layer and exposing a portion of said ion implantation buffer layer; doping n-type silicon to said i o n implantation buffer l ayer exposed fro m said patterned photoresist layer and activating for forming said first source ion implantation regi o n, said first drain i o n implantation regi o n, said sec ond source ion implantation region, and said second drain ion implantation reg io n in sa id i-Al x GaN layer; and removing said patterned photoresist layer and said ion implantation buffer l ayer.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion of claim 1, comprising: an epitaxial structure o f N-face A l GaN/GaN, divided into a left region and a right region; a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, located in said left regi o n, co m prising: a p-GaN inverted trapezoidal gate structure, a first source metal layer, and a first drain metal layer, located o n said i-A l X GaN layer, and the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure being depleted; a first s o urce i o n implantation regi o n and a first drain ion implantation 47 regi o n, l o cated in said i-A l x GaN layer, said first s o urce i on implantation region located bel o w said first source metal layer, and said first drain i o n implantati o n regi o n l o cated bel o w said first drain metal layer; and a f ir st gate metal layer, located o n sa i d p-GaN i nverted trapez oi dal gate structure; and a depletion-mode N-face A I GaN/GaN high electron mobility transistor with gate dielectric layer, located in said right regi o n, comprising: a second source metal layer and a second drain metal layer, located on said i-A l y GaN layer; a gate dielectric layer, located on said i-A l X GaN layer and between said sec o nd s o urce metal layer and said sec o nd drain metal layer; and a second source ion implantation region and a second drain ion i mplantati o n reg io n, l o cated i n sa i d i-A l y GaN layer, sa i d sec ond source ion implantation regi o n located below said second source metal layer, and said second drain ion implantation region located below said sec o nd drain metal layer; where said epitaxial structure of N-face A I GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, l ocated o n said C-doped buffer layer; an i-A ly GaN buffer layer, located o n said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A Iy GaN buffer layer; and an i-A l y GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
Layer stacks claimed or described, ordered top of device to substrate.
selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN HEMT with polarity inversion
Materials described outside the worked examples.
C-doped buffer layer
C-doped i-GaN layer
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4B ~ 4D show the operations of the SEG p-GaN gate E-m o de N-face AIGaN/GaN HEMT with polarity inversion at a fixed Vd and va r ying gate voltages Vg …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 nm | — |
Thickness | ≥ 2500 nm |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE (GAN) POWER AMPLIFIERS (PA) WITH ANGLED ELECTRODES AND 100 CMOS AND METHOD FOR PRODUCING THE SAME
GALLIUM NITRIDE (GAN) SELECTIVE EPITAXIAL WINDOWS FOR INTEGRATED CIRCUIT TECHNOLOGY
Patent
Atlas literature
Patent
US 10,475,913Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows distributions of E P s and E Pz in Ga-face and N-face A l GaN/GaN and GaN/InGaN systems in d iff erent stains according to the present invention;
FIG. 2 shows a schematic diagram of Ga-face and N-face GaN grown on a substrate;
FIG. 3 shows a schematic diagram of the d if ferent locations of 2DEG generated at the junctions between A I GaN and G aN due to different polarization …
FIG. 4B ~ 4D show the operations of the SEG p-GaN gate E-m o de N-face AIGaN/GaN HEMT with polarity inversion at a fixed Vd and va r ying gate voltages Vg …
FIG. 5 B shows a second structure diagram of the epitaxial structure of the N-face AI GaN/GaN HEMT acc o rding to the present i nvent ion;
FIG. 6A-2 sh ow cr o ss-sectional views of the SEG p-GaN gate E-mode N-face A l GaN/GaN HE M T with polarity inversion according to the present invention;
FIG. 7E-2 sh ow schematic diagrams of f o rming the metal gate electrode and the bonding pads and interconnection metals f or drain and source in the SEG p-GaN …
FIG. 8A-2 show c ross-sectional views of the SEG p-GaN anode N-face A l GaN/GaN SBD with polarity inversion according to the present invention;
FIG. 9A shows an equivalent circuit diagram of a hybrid E-mode N-face A l GaN/GaN HEMT with p o larity inversi o n f o rmed by casc o ding an SEG E-m o de …
FIG. 10 A shows a schematic diagram of the equivalent circuit in
FIG. 11 A-2; Figures 12A to 12F-2 show schematic diagrams of the process steps f o r fabricating the structures in F I G. 11A-1 and F I G. 11 A-2 according to …
FIG. 12C. Next, use destructive io n implantat io n as sh own i n
FIG. 13A-2; Figures 1 4A-1 to 1 4 A-4 show schematic diagrams o f the process steps for fabricating the structures in
FIG. 15 shows an equivalent circuit diagram o f a hybrid N-face A l GaN/GaN SBD with polarity inversion f ormed by cascoding an SEG p-GaN anode N-face Al …
FIG. 16B sh o ws a t o p view of
FIG. 17B shows a t o p view o f
FIG. 18A-2 sh ow cr o ss-sectional views of the SEG p-GaN gate and self-aligned gate metal E-mo de G -face A l GaN/GaN HEMT with polarity inversion according …
FIG. 19A. First, use PECVD to deposit a layer of Si O₂ mas k 105 as a buffer layer. Thereby, during i on implantation, the peak value of the Gaussian …
FIG. 20A-2 show cr o ss-sectional views of the SEG p-GaN anode and self-aligned gate m etal E- mo de N-face A IG aN/G aN SBD with polarity inversion according …
FIG. 21A-2 show c ross-sectional views of the hybrid E -mode N-face AI GaN/GaN HEMT with polarity inversion according to the present invention;
FIG. 22G-2 show cro ss-sectional views of the process steps f o r
FIG. 23A-2 show cross-sectional views of the hybrid E- m ode N-face AIG aN/G aN HEMT with polarity inversion according to the present invention;
FIG. 24B-2 show cro ss-sectional views of the process steps f o r Figures 23A- 1 and 23A-2;
FIG. 26A- 1 and F I G. 26A-2 show cross-sectional views of the hybrid N- face Al GaN/GaN SBD with polarity inversion according to the present invention; and FI …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The structure of claim 1, wherein an i-A l z GaN grading buffer layer is further disposed between said C-doped i-GaN layer and said i-A ly GaN buffer layer and z=0.01 ~0.75.
A method for fabricating an enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion using said epitaxial structure of claim 1, comprising steps of: providing an epitaxia l structure of N-face AIGaN/GaN; and forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face A l GaN/GaN using selective epitaxial growth for controlling the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A i X GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of clai m 3, and in said step of forming said p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN, further comprising steps of: forming a silicon oxynitride mask layer on said epitaxial structure of N-face AI GaN/GaN; exposing and developing said silicon oxynitride mask layer for defining a gate selective epitaxial growth region; etching said gate selective epitaxial growth region using buffered oxide etchant for forming an inverted trapezoidal structure; growing p-GaN in said inverted trapezoidal structure for forming said p-GaN inverted trapezoidal gate structure; and removing said silicon oxynitride mask layer.
A selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of AI GaN/G aN; and a p-GaN inverted trapezoidal gate structure, located on an i-A l x GaN layer; where the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure is depleted, and said epitaxial structure of N-face AI GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i- C aN channel layer, located on said i-A ly GaN buffer layer; and said i-A l X GaN layer, located on said i-GaN channel layer; where x= O.1~0.3; y= 0.05-0.75.
A method for fabricating a hybrid enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion using said epitaxial structure of claim 1, comprising steps of: providing an epitaxial structure of N-face AlGaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right re gion; forming a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion in said left region by steps comprising: forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN using selective epitaxial growth for controlling the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; and forming a depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer in said right region; where said epitaxial structure of N-face A I GaN/GaN co m prises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-Al y GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A I X GaN layer, located on said i-GaN channel layer; where x= 0.10.3; y= 0.05~0.75.
The method of claim 6, wherein said selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion and said depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer are fabricated concurrent ly.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of N-face A I GaN/GaN, divided into a left region and a right region; a selective-epitaxia l -growth p-GaN gate enhancement-mode N-face Al GaN/GaN high electron mobi l ity transistor with polarity inversion, located in said left region, comprising a p-GaN inverted trapezoidal gate structure, and the two-dimensional electron gas below said p- GaN inverted trapezoidal gate structure being depleted; and a depletion-m o de N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer, located in said right region; where said epitaxial structure of N-face AlGaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A lyG aN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A lx GaN layer, located on said i-GaN channel layer; where x =0.1-0.3; y =0.05~0.75.
A method for fabricating a hybrid enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion, comprising steps of: providing an epitaxial structure of N-face A t GaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right region; forming a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion in said left region by steps comprising: forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN using selective epitaxial growth for control l ing the 38 two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; and forming a depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and gate dielectric layer in said right region; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i- C aN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= O.1~0.3; y= 0.050.75.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of N-face A l GaN/GaN, divided into a left region and a right region; a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion, located in said left region, comprising a p-GaN inverted trapezoidal gate structure, and the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure being depleted; and a depletion-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion and gate dielectric layer, located in said right region; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
11. A method for fabricating a selective-epitaxial-growth p-GaN gate enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion, comprising steps o f: providing an epitaxial structure of N-face AIGaN/GaN; forming a first source ion implantation region and a first drain ion implantation region in said i-A h x GaN layer; forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face A l GaN/GaN using selective epitaxial growth; forming a f irst gate metal layer on said p-GaN inverted trapezoidal gate structure; and forming a first source metal layer and a f i rst drain metal layer on said epitaxia l structure of N-face A l GaN/GaN, said first source meta l layer located on said first source ion implantation region, and said first drain metal layer located on said first drain ion implantation region; where said epitaxial structure of N-face A I GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A iy GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of claim 11, and in said steps of forming said p-GaN inverted trapezoidal gate structure and said first gate metal layer, further comprising steps o f: forming a silicon oxynitride mas k layer on said epitaxia l structure of N-face AI GaN/GaN; fo rming an inverted trapez o idal structure by patterning said si licon o xynitride mask layer using a patterned photoresist layer and buffered oxide etchant; grow ing p-GaN in said inverted trapez o idal structure f o r f o rming said p-GaN inverted trapezoidal gate structure; fo rming a f ir st metal layer o n the surfaces of sa i d s ilicon o xynitride mas k layer and said p-GaN inverted trapezoidal gate structure; and removing said silicon oxynitride mask layer and said metal layer on said silicon o xynitride mas k layer, and reserving the fi rst metal layer o n the surface of said p-GaN inverted trapezoidal gate structure for acting as said first gate metal layer.
The meth o d of claim 1 1, and in said step of f o rming said first s o urc e ion implantation region and said first drain ion implantation region in said i-A X GaN layer, further comprising steps of: forming an ion implantation buffer layer on said epitaxial structure of N-face A₁ GaN/GaN; fo rming a patterned ph oto resist layer o n said i o n implantation buffer layer and exposing a portion of said ion implantation buffer layer; doping n-type si lico n to said i o n implantation buffer l ayer expo sed fro m said patterned photoresist layer and activating f or fo rmi ng said first source ion implantation region and said first drain i o n implantation region in said i-A l X GaN layer; and removing said patterned photoresist layer and said ion implantation buffer layer.
The method of claim 13, wherein said activation is performed by a thermal treatment at a te m perature between 6 00 and 9 000 SVG 16124596.09-07-2018.JLSAAS₁BRXEAPX3.CLM.7.24.1519.2515.1547.2549.svg 0.113 0.093 Chemistry Black and white
15. A selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxia l structure of N-face AIGaN/GaN; a p-GaN inverted trap ezo idal gate structure, a fi rst s o urce metal layer, and a first drain metal layer, located on said i-A l X GaN layer, and the two-dimensional electr o n gas b elo w said p-GaN inverted trap ezo idal gate structure being depleted; a fir st s o urce io n implantat io n reg io n and a first dra in ion i mplantati o n reg ion, located in said i-A l X GaN layer, said first s o urce ion implantation region located below said fir st source metal layer, and said fir st drain ion im plantati o n regi o n l o cated below said first drain metal layer; and a first gate metal layer, located on said p-GaN inverted trapezoidal gate structu re; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i -GaN layer, l o cated o n said C-doped buffer layer; an i-A l y GaN buffer layer, located o n said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN bu ff er layer; and an i-A l X GaN layer, l o cated o n said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
A method for fabricating a hybrid enhancement-mode N-face A l GaN/GaN high electr o n mobility transistor with polarity inversion, comprising steps of: providing an epitaxial structure o f N-face A l GaN/GaN, and dividing said epitaxial structure of N-face A L GaN/GaN into a l eft region and a right region; forming a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A IG aN/GaN high electr on mo bility transistor with polarity inversion in said left region by steps comprising: fo rming a first s o urce i o n implantation regi o n and a first drain i on implantation region in said i-A l X GaN layer; fo rming a p-GaN inverted trapezoidal gate structure o n said epitaxial structure of N-face A lG aN/GaN using selective epitaxial growth and 42 the two-di m ensi o nal electr o n gas below said p-GaN inverted trapezoidal gate structure being depleted; fo rming a first gate metal layer o n said p-GaN inverted trapezoidal gate structure; and fo rming a first source metal layer and a f ir st drain metal layer o n sa id epitaxial structure of A l GaN/GaN, said first source metal layer located on said f ir st source ion implantation region, and said first drain m etal layer located o n said fi rst drain i o n i m plantation regi on; and fo rming a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and without gate dielectric layer in said right regi o n by steps comprising: forming a second source ion implantation region and a second drain ion i mplantati o n regi on i n said i-Al x GaN layer; and forming a second source metal layer and a second drain metal layer on said epitaxial structure of N-face A I GaN/GaN, said second source metal layer located o n said sec o nd s o urce i o n i m plantation regi on, and said second drain metal layer located on said second drain ion SVG 16124596.09-07-2018.JLSAAS₁BRXEAPX3.CLM.9.19.755.1897.804.1931.svg 0.113 0.163 Chemistry Black and white m plantati o n regi on; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN l ayer, l ocated on said C-doped buffer l ayer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A l x G aN layer, located o n said i- G aN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of claim 16, and in said step of forming said first source ion implantation regi o n, said first drain i o n implantation regi o n, said sec o nd s o urce io n implantation regi o n, and said sec o nd drain i o n implantation regi o n in said 43 i-A lx GaN layer, further c o mprising steps of: forming an ion implantation buffer layer on said epitaxial structure of N-face Al GaN/GaN; forming a patterned photoresist layer on said ion implantation buffer layer and expos i ng a portion of said ion i mplantat io n buffer layer; doping n-type silicon to said ion implantation buffer layer exposed from said patterned photoresist layer and activating for forming said first source ion implantati o n regi o n, said fi rst drain i o n implantati o n regi o n, said sec ond source ion implantation region, and said second drain ion implantation regi o n in said i-A l X GaN layer; and removing said patterned photoresist layer and said ion implantation buffer l ayer.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, c o mprising: an epitaxial structure of N-face A l GaN/GaN, divided into a left region and a right regi on; a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A l GaN/GaN high electron mobility transistor with polarity inversion, l ocated in said left region, comprising: a p-GaN inverted trapezoidal gate structure, a fi rst source metal layer, and a first drain metal layer, l ocated on said i-A l X GaN layer, and the two-dimensional electron gas below said p-GaN inverted trapezoida l gate structure being depleted; a first source ion implantation region and a first drain ion implantation regi o n, located in said i-A lx GaN layer, said first source i on implantation region located below said first source metal layer, and said first drain i o n implantation regi o n located below said first drain metal layer; and a f irst gate metal layer, l o cated o n said p-GaN inverted trapezoidal gate structure; and a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and without gate dielectric layer, located in said right reg io n, comprising: a second source metal layer and a second drain metal layer, located on said i-A l x GaN layer; and a sec o nd s o urce i o n i m plantati o n regi o n and a sec o nd drain i on implantation regi o n, located in said i-A l x GaN layer, said sec ond so urce i o n implantati o n regi o n l o cated below said sec o nd s o urce metal layer, and said sec o nd drain i o n implantati o n regi o n l o cated below said sec o nd drain metal layer; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, l o cated on said C-doped bu ff er layer; an i-A lyG aN buffer layer, l o cated o n said C-doped i-GaN layer; an i-GaN channel layer, l o cated on said i-Al y GaN buffer layer; and an i-A lx GaN layer, l o cated o n said i-GaN channel layer; where x =0.1~ 0.3; y =0.05~0.75.
A method f o r fabricating a hybrid enhancement-m o de N-face A l GaN/GaN high electr o n mobility transistor with polarity inversion, c om prising steps of: providing an epitaxial structure of N-face A t GaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right regi on; forming a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion in said left region by steps comprising: fo rming a f irst s o urce i o n implantati o n regi o n and a f irst drain i on implantati o n regi o n in said i-A l x GaN layer; fo rming a p-GaN inverted trapezoidal gate structure o n said epitaxia l structure of N-face A l GaN/GaN using selective epitaxial growth and the two-dimensional electr o n gas below said p-GaN inverted trapezoidal gate structure being depleted; fo rming a fir st gate metal layer o n sa i d p-GaN i nverted trapez oi dal gate structure; and forming a first source metal layer and a fi rst drain metal layer o n said epitaxial structure of N-face A IG aN/G aN, said fi rst s o urce metal layer located on said first source ion implantation regi o n, and said first drain metal layer l o cated o n said first drain i o n implantati on region; and fo rming a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and gate dielectric layer in said right region by steps comprising: forming a second source ion implantation region and a second drain ion implantation region in said i-A lx GaN layer; fo rming a sec o nd s o urce metal layer and a sec o nd drain metal layer on said epitaxial structure of N-face A l GaN/GaN, said second source metal layer l o cated o n said sec o nd s o urce i o n implantati o n regi on, and said second drain metal layer located on said second drain ion implantati o n regi o n; and forming a gate dielectric layer on said epitaxial structure of N-face AI GaN/GaN; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-d o ped buffer layer, l o cated o n said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, l o cated o n said C-d o ped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A l X GaN layer, l o cated o n said i-GaN channel layer; where x= 0.10.3; y= 0.05~0.75.
The method of claim 20, and in said step of forming said first source ion implantati o n regi o n, said first drain i o n implantati o n regi o n, said sec o nd s o urce ion implantation region, and said second drain ion implantation region in said i-Alx GaN layer, further comprising steps of: fo rming an i o n implantation buffer layer o n said epitaxial structure o f N-face Al GaN/GaN; fo rming a patterned ph oto resist layer o n said i o n implantati o n bu ff er layer and exposing a portion of said ion implantation buffer layer; doping n-type silicon to said i o n implantation buffer l ayer exposed fro m said patterned photoresist layer and activating for forming said first source ion implantation regi o n, said first drain i o n implantation regi o n, said sec ond source ion implantation region, and said second drain ion implantation reg io n in sa id i-Al x GaN layer; and removing said patterned photoresist layer and said ion implantation buffer l ayer.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion of claim 1, comprising: an epitaxial structure o f N-face A l GaN/GaN, divided into a left region and a right region; a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, located in said left regi o n, co m prising: a p-GaN inverted trapezoidal gate structure, a first source metal layer, and a first drain metal layer, located o n said i-A l X GaN layer, and the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure being depleted; a first s o urce i o n implantation regi o n and a first drain ion implantation 47 regi o n, l o cated in said i-A l x GaN layer, said first s o urce i on implantation region located bel o w said first source metal layer, and said first drain i o n implantati o n regi o n l o cated bel o w said first drain metal layer; and a f ir st gate metal layer, located o n sa i d p-GaN i nverted trapez oi dal gate structure; and a depletion-mode N-face A I GaN/GaN high electron mobility transistor with gate dielectric layer, located in said right regi o n, comprising: a second source metal layer and a second drain metal layer, located on said i-A l y GaN layer; a gate dielectric layer, located on said i-A l X GaN layer and between said sec o nd s o urce metal layer and said sec o nd drain metal layer; and a second source ion implantation region and a second drain ion i mplantati o n reg io n, l o cated i n sa i d i-A l y GaN layer, sa i d sec ond source ion implantation regi o n located below said second source metal layer, and said second drain ion implantation region located below said sec o nd drain metal layer; where said epitaxial structure of N-face A I GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, l ocated o n said C-doped buffer layer; an i-A ly GaN buffer layer, located o n said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A Iy GaN buffer layer; and an i-A l y GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
Layer stacks claimed or described, ordered top of device to substrate.
selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN HEMT with polarity inversion
Materials described outside the worked examples.
C-doped buffer layer
C-doped i-GaN layer
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4B ~ 4D show the operations of the SEG p-GaN gate E-m o de N-face AIGaN/GaN HEMT with polarity inversion at a fixed Vd and va r ying gate voltages Vg …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 nm | — |
Thickness | ≥ 2500 nm |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE (GAN) POWER AMPLIFIERS (PA) WITH ANGLED ELECTRODES AND 100 CMOS AND METHOD FOR PRODUCING THE SAME
GALLIUM NITRIDE (GAN) SELECTIVE EPITAXIAL WINDOWS FOR INTEGRATED CIRCUIT TECHNOLOGY
Patent
Atlas literature
Patent
US 10,475,913Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows distributions of E P s and E Pz in Ga-face and N-face A l GaN/GaN and GaN/InGaN systems in d iff erent stains according to the present invention;
FIG. 2 shows a schematic diagram of Ga-face and N-face GaN grown on a substrate;
FIG. 3 shows a schematic diagram of the d if ferent locations of 2DEG generated at the junctions between A I GaN and G aN due to different polarization …
FIG. 4B ~ 4D show the operations of the SEG p-GaN gate E-m o de N-face AIGaN/GaN HEMT with polarity inversion at a fixed Vd and va r ying gate voltages Vg …
FIG. 5 B shows a second structure diagram of the epitaxial structure of the N-face AI GaN/GaN HEMT acc o rding to the present i nvent ion;
FIG. 6A-2 sh ow cr o ss-sectional views of the SEG p-GaN gate E-mode N-face A l GaN/GaN HE M T with polarity inversion according to the present invention;
FIG. 7E-2 sh ow schematic diagrams of f o rming the metal gate electrode and the bonding pads and interconnection metals f or drain and source in the SEG p-GaN …
FIG. 8A-2 show c ross-sectional views of the SEG p-GaN anode N-face A l GaN/GaN SBD with polarity inversion according to the present invention;
FIG. 9A shows an equivalent circuit diagram of a hybrid E-mode N-face A l GaN/GaN HEMT with p o larity inversi o n f o rmed by casc o ding an SEG E-m o de …
FIG. 10 A shows a schematic diagram of the equivalent circuit in
FIG. 11 A-2; Figures 12A to 12F-2 show schematic diagrams of the process steps f o r fabricating the structures in F I G. 11A-1 and F I G. 11 A-2 according to …
FIG. 12C. Next, use destructive io n implantat io n as sh own i n
FIG. 13A-2; Figures 1 4A-1 to 1 4 A-4 show schematic diagrams o f the process steps for fabricating the structures in
FIG. 15 shows an equivalent circuit diagram o f a hybrid N-face A l GaN/GaN SBD with polarity inversion f ormed by cascoding an SEG p-GaN anode N-face Al …
FIG. 16B sh o ws a t o p view of
FIG. 17B shows a t o p view o f
FIG. 18A-2 sh ow cr o ss-sectional views of the SEG p-GaN gate and self-aligned gate metal E-mo de G -face A l GaN/GaN HEMT with polarity inversion according …
FIG. 19A. First, use PECVD to deposit a layer of Si O₂ mas k 105 as a buffer layer. Thereby, during i on implantation, the peak value of the Gaussian …
FIG. 20A-2 show cr o ss-sectional views of the SEG p-GaN anode and self-aligned gate m etal E- mo de N-face A IG aN/G aN SBD with polarity inversion according …
FIG. 21A-2 show c ross-sectional views of the hybrid E -mode N-face AI GaN/GaN HEMT with polarity inversion according to the present invention;
FIG. 22G-2 show cro ss-sectional views of the process steps f o r
FIG. 23A-2 show cross-sectional views of the hybrid E- m ode N-face AIG aN/G aN HEMT with polarity inversion according to the present invention;
FIG. 24B-2 show cro ss-sectional views of the process steps f o r Figures 23A- 1 and 23A-2;
FIG. 26A- 1 and F I G. 26A-2 show cross-sectional views of the hybrid N- face Al GaN/GaN SBD with polarity inversion according to the present invention; and FI …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The structure of claim 1, wherein an i-A l z GaN grading buffer layer is further disposed between said C-doped i-GaN layer and said i-A ly GaN buffer layer and z=0.01 ~0.75.
A method for fabricating an enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion using said epitaxial structure of claim 1, comprising steps of: providing an epitaxia l structure of N-face AIGaN/GaN; and forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face A l GaN/GaN using selective epitaxial growth for controlling the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A i X GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of clai m 3, and in said step of forming said p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN, further comprising steps of: forming a silicon oxynitride mask layer on said epitaxial structure of N-face AI GaN/GaN; exposing and developing said silicon oxynitride mask layer for defining a gate selective epitaxial growth region; etching said gate selective epitaxial growth region using buffered oxide etchant for forming an inverted trapezoidal structure; growing p-GaN in said inverted trapezoidal structure for forming said p-GaN inverted trapezoidal gate structure; and removing said silicon oxynitride mask layer.
A selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of AI GaN/G aN; and a p-GaN inverted trapezoidal gate structure, located on an i-A l x GaN layer; where the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure is depleted, and said epitaxial structure of N-face AI GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i- C aN channel layer, located on said i-A ly GaN buffer layer; and said i-A l X GaN layer, located on said i-GaN channel layer; where x= O.1~0.3; y= 0.05-0.75.
A method for fabricating a hybrid enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion using said epitaxial structure of claim 1, comprising steps of: providing an epitaxial structure of N-face AlGaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right re gion; forming a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion in said left region by steps comprising: forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN using selective epitaxial growth for controlling the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; and forming a depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer in said right region; where said epitaxial structure of N-face A I GaN/GaN co m prises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-Al y GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A I X GaN layer, located on said i-GaN channel layer; where x= 0.10.3; y= 0.05~0.75.
The method of claim 6, wherein said selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion and said depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer are fabricated concurrent ly.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of N-face A I GaN/GaN, divided into a left region and a right region; a selective-epitaxia l -growth p-GaN gate enhancement-mode N-face Al GaN/GaN high electron mobi l ity transistor with polarity inversion, located in said left region, comprising a p-GaN inverted trapezoidal gate structure, and the two-dimensional electron gas below said p- GaN inverted trapezoidal gate structure being depleted; and a depletion-m o de N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer, located in said right region; where said epitaxial structure of N-face AlGaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A lyG aN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A lx GaN layer, located on said i-GaN channel layer; where x =0.1-0.3; y =0.05~0.75.
A method for fabricating a hybrid enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion, comprising steps of: providing an epitaxial structure of N-face A t GaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right region; forming a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion in said left region by steps comprising: forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN using selective epitaxial growth for control l ing the 38 two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; and forming a depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and gate dielectric layer in said right region; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i- C aN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= O.1~0.3; y= 0.050.75.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of N-face A l GaN/GaN, divided into a left region and a right region; a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion, located in said left region, comprising a p-GaN inverted trapezoidal gate structure, and the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure being depleted; and a depletion-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion and gate dielectric layer, located in said right region; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
11. A method for fabricating a selective-epitaxial-growth p-GaN gate enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion, comprising steps o f: providing an epitaxial structure of N-face AIGaN/GaN; forming a first source ion implantation region and a first drain ion implantation region in said i-A h x GaN layer; forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face A l GaN/GaN using selective epitaxial growth; forming a f irst gate metal layer on said p-GaN inverted trapezoidal gate structure; and forming a first source metal layer and a f i rst drain metal layer on said epitaxia l structure of N-face A l GaN/GaN, said first source meta l layer located on said first source ion implantation region, and said first drain metal layer located on said first drain ion implantation region; where said epitaxial structure of N-face A I GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A iy GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of claim 11, and in said steps of forming said p-GaN inverted trapezoidal gate structure and said first gate metal layer, further comprising steps o f: forming a silicon oxynitride mas k layer on said epitaxia l structure of N-face AI GaN/GaN; fo rming an inverted trapez o idal structure by patterning said si licon o xynitride mask layer using a patterned photoresist layer and buffered oxide etchant; grow ing p-GaN in said inverted trapez o idal structure f o r f o rming said p-GaN inverted trapezoidal gate structure; fo rming a f ir st metal layer o n the surfaces of sa i d s ilicon o xynitride mas k layer and said p-GaN inverted trapezoidal gate structure; and removing said silicon oxynitride mask layer and said metal layer on said silicon o xynitride mas k layer, and reserving the fi rst metal layer o n the surface of said p-GaN inverted trapezoidal gate structure for acting as said first gate metal layer.
The meth o d of claim 1 1, and in said step of f o rming said first s o urc e ion implantation region and said first drain ion implantation region in said i-A X GaN layer, further comprising steps of: forming an ion implantation buffer layer on said epitaxial structure of N-face A₁ GaN/GaN; fo rming a patterned ph oto resist layer o n said i o n implantation buffer layer and exposing a portion of said ion implantation buffer layer; doping n-type si lico n to said i o n implantation buffer l ayer expo sed fro m said patterned photoresist layer and activating f or fo rmi ng said first source ion implantation region and said first drain i o n implantation region in said i-A l X GaN layer; and removing said patterned photoresist layer and said ion implantation buffer layer.
The method of claim 13, wherein said activation is performed by a thermal treatment at a te m perature between 6 00 and 9 000 SVG 16124596.09-07-2018.JLSAAS₁BRXEAPX3.CLM.7.24.1519.2515.1547.2549.svg 0.113 0.093 Chemistry Black and white
15. A selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxia l structure of N-face AIGaN/GaN; a p-GaN inverted trap ezo idal gate structure, a fi rst s o urce metal layer, and a first drain metal layer, located on said i-A l X GaN layer, and the two-dimensional electr o n gas b elo w said p-GaN inverted trap ezo idal gate structure being depleted; a fir st s o urce io n implantat io n reg io n and a first dra in ion i mplantati o n reg ion, located in said i-A l X GaN layer, said first s o urce ion implantation region located below said fir st source metal layer, and said fir st drain ion im plantati o n regi o n l o cated below said first drain metal layer; and a first gate metal layer, located on said p-GaN inverted trapezoidal gate structu re; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i -GaN layer, l o cated o n said C-doped buffer layer; an i-A l y GaN buffer layer, located o n said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN bu ff er layer; and an i-A l X GaN layer, l o cated o n said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
A method for fabricating a hybrid enhancement-mode N-face A l GaN/GaN high electr o n mobility transistor with polarity inversion, comprising steps of: providing an epitaxial structure o f N-face A l GaN/GaN, and dividing said epitaxial structure of N-face A L GaN/GaN into a l eft region and a right region; forming a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A IG aN/GaN high electr on mo bility transistor with polarity inversion in said left region by steps comprising: fo rming a first s o urce i o n implantation regi o n and a first drain i on implantation region in said i-A l X GaN layer; fo rming a p-GaN inverted trapezoidal gate structure o n said epitaxial structure of N-face A lG aN/GaN using selective epitaxial growth and 42 the two-di m ensi o nal electr o n gas below said p-GaN inverted trapezoidal gate structure being depleted; fo rming a first gate metal layer o n said p-GaN inverted trapezoidal gate structure; and fo rming a first source metal layer and a f ir st drain metal layer o n sa id epitaxial structure of A l GaN/GaN, said first source metal layer located on said f ir st source ion implantation region, and said first drain m etal layer located o n said fi rst drain i o n i m plantation regi on; and fo rming a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and without gate dielectric layer in said right regi o n by steps comprising: forming a second source ion implantation region and a second drain ion i mplantati o n regi on i n said i-Al x GaN layer; and forming a second source metal layer and a second drain metal layer on said epitaxial structure of N-face A I GaN/GaN, said second source metal layer located o n said sec o nd s o urce i o n i m plantation regi on, and said second drain metal layer located on said second drain ion SVG 16124596.09-07-2018.JLSAAS₁BRXEAPX3.CLM.9.19.755.1897.804.1931.svg 0.113 0.163 Chemistry Black and white m plantati o n regi on; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN l ayer, l ocated on said C-doped buffer l ayer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A l x G aN layer, located o n said i- G aN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of claim 16, and in said step of forming said first source ion implantation regi o n, said first drain i o n implantation regi o n, said sec o nd s o urce io n implantation regi o n, and said sec o nd drain i o n implantation regi o n in said 43 i-A lx GaN layer, further c o mprising steps of: forming an ion implantation buffer layer on said epitaxial structure of N-face Al GaN/GaN; forming a patterned photoresist layer on said ion implantation buffer layer and expos i ng a portion of said ion i mplantat io n buffer layer; doping n-type silicon to said ion implantation buffer layer exposed from said patterned photoresist layer and activating for forming said first source ion implantati o n regi o n, said fi rst drain i o n implantati o n regi o n, said sec ond source ion implantation region, and said second drain ion implantation regi o n in said i-A l X GaN layer; and removing said patterned photoresist layer and said ion implantation buffer l ayer.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, c o mprising: an epitaxial structure of N-face A l GaN/GaN, divided into a left region and a right regi on; a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A l GaN/GaN high electron mobility transistor with polarity inversion, l ocated in said left region, comprising: a p-GaN inverted trapezoidal gate structure, a fi rst source metal layer, and a first drain metal layer, l ocated on said i-A l X GaN layer, and the two-dimensional electron gas below said p-GaN inverted trapezoida l gate structure being depleted; a first source ion implantation region and a first drain ion implantation regi o n, located in said i-A lx GaN layer, said first source i on implantation region located below said first source metal layer, and said first drain i o n implantation regi o n located below said first drain metal layer; and a f irst gate metal layer, l o cated o n said p-GaN inverted trapezoidal gate structure; and a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and without gate dielectric layer, located in said right reg io n, comprising: a second source metal layer and a second drain metal layer, located on said i-A l x GaN layer; and a sec o nd s o urce i o n i m plantati o n regi o n and a sec o nd drain i on implantation regi o n, located in said i-A l x GaN layer, said sec ond so urce i o n implantati o n regi o n l o cated below said sec o nd s o urce metal layer, and said sec o nd drain i o n implantati o n regi o n l o cated below said sec o nd drain metal layer; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, l o cated on said C-doped bu ff er layer; an i-A lyG aN buffer layer, l o cated o n said C-doped i-GaN layer; an i-GaN channel layer, l o cated on said i-Al y GaN buffer layer; and an i-A lx GaN layer, l o cated o n said i-GaN channel layer; where x =0.1~ 0.3; y =0.05~0.75.
A method f o r fabricating a hybrid enhancement-m o de N-face A l GaN/GaN high electr o n mobility transistor with polarity inversion, c om prising steps of: providing an epitaxial structure of N-face A t GaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right regi on; forming a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion in said left region by steps comprising: fo rming a f irst s o urce i o n implantati o n regi o n and a f irst drain i on implantati o n regi o n in said i-A l x GaN layer; fo rming a p-GaN inverted trapezoidal gate structure o n said epitaxia l structure of N-face A l GaN/GaN using selective epitaxial growth and the two-dimensional electr o n gas below said p-GaN inverted trapezoidal gate structure being depleted; fo rming a fir st gate metal layer o n sa i d p-GaN i nverted trapez oi dal gate structure; and forming a first source metal layer and a fi rst drain metal layer o n said epitaxial structure of N-face A IG aN/G aN, said fi rst s o urce metal layer located on said first source ion implantation regi o n, and said first drain metal layer l o cated o n said first drain i o n implantati on region; and fo rming a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and gate dielectric layer in said right region by steps comprising: forming a second source ion implantation region and a second drain ion implantation region in said i-A lx GaN layer; fo rming a sec o nd s o urce metal layer and a sec o nd drain metal layer on said epitaxial structure of N-face A l GaN/GaN, said second source metal layer l o cated o n said sec o nd s o urce i o n implantati o n regi on, and said second drain metal layer located on said second drain ion implantati o n regi o n; and forming a gate dielectric layer on said epitaxial structure of N-face AI GaN/GaN; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-d o ped buffer layer, l o cated o n said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, l o cated o n said C-d o ped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A l X GaN layer, l o cated o n said i-GaN channel layer; where x= 0.10.3; y= 0.05~0.75.
The method of claim 20, and in said step of forming said first source ion implantati o n regi o n, said first drain i o n implantati o n regi o n, said sec o nd s o urce ion implantation region, and said second drain ion implantation region in said i-Alx GaN layer, further comprising steps of: fo rming an i o n implantation buffer layer o n said epitaxial structure o f N-face Al GaN/GaN; fo rming a patterned ph oto resist layer o n said i o n implantati o n bu ff er layer and exposing a portion of said ion implantation buffer layer; doping n-type silicon to said i o n implantation buffer l ayer exposed fro m said patterned photoresist layer and activating for forming said first source ion implantation regi o n, said first drain i o n implantation regi o n, said sec ond source ion implantation region, and said second drain ion implantation reg io n in sa id i-Al x GaN layer; and removing said patterned photoresist layer and said ion implantation buffer l ayer.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion of claim 1, comprising: an epitaxial structure o f N-face A l GaN/GaN, divided into a left region and a right region; a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, located in said left regi o n, co m prising: a p-GaN inverted trapezoidal gate structure, a first source metal layer, and a first drain metal layer, located o n said i-A l X GaN layer, and the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure being depleted; a first s o urce i o n implantation regi o n and a first drain ion implantation 47 regi o n, l o cated in said i-A l x GaN layer, said first s o urce i on implantation region located bel o w said first source metal layer, and said first drain i o n implantati o n regi o n l o cated bel o w said first drain metal layer; and a f ir st gate metal layer, located o n sa i d p-GaN i nverted trapez oi dal gate structure; and a depletion-mode N-face A I GaN/GaN high electron mobility transistor with gate dielectric layer, located in said right regi o n, comprising: a second source metal layer and a second drain metal layer, located on said i-A l y GaN layer; a gate dielectric layer, located on said i-A l X GaN layer and between said sec o nd s o urce metal layer and said sec o nd drain metal layer; and a second source ion implantation region and a second drain ion i mplantati o n reg io n, l o cated i n sa i d i-A l y GaN layer, sa i d sec ond source ion implantation regi o n located below said second source metal layer, and said second drain ion implantation region located below said sec o nd drain metal layer; where said epitaxial structure of N-face A I GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, l ocated o n said C-doped buffer layer; an i-A ly GaN buffer layer, located o n said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A Iy GaN buffer layer; and an i-A l y GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
Layer stacks claimed or described, ordered top of device to substrate.
selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN HEMT with polarity inversion
Materials described outside the worked examples.
C-doped buffer layer
C-doped i-GaN layer
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4B ~ 4D show the operations of the SEG p-GaN gate E-m o de N-face AIGaN/GaN HEMT with polarity inversion at a fixed Vd and va r ying gate voltages Vg …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 nm | — |
Thickness | ≥ 2500 nm |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE (GAN) POWER AMPLIFIERS (PA) WITH ANGLED ELECTRODES AND 100 CMOS AND METHOD FOR PRODUCING THE SAME
GALLIUM NITRIDE (GAN) SELECTIVE EPITAXIAL WINDOWS FOR INTEGRATED CIRCUIT TECHNOLOGY
Patent
Atlas literature
Patent
US 10,475,913Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows distributions of E P s and E Pz in Ga-face and N-face A l GaN/GaN and GaN/InGaN systems in d iff erent stains according to the present invention;
FIG. 2 shows a schematic diagram of Ga-face and N-face GaN grown on a substrate;
FIG. 3 shows a schematic diagram of the d if ferent locations of 2DEG generated at the junctions between A I GaN and G aN due to different polarization …
FIG. 4B ~ 4D show the operations of the SEG p-GaN gate E-m o de N-face AIGaN/GaN HEMT with polarity inversion at a fixed Vd and va r ying gate voltages Vg …
FIG. 5 B shows a second structure diagram of the epitaxial structure of the N-face AI GaN/GaN HEMT acc o rding to the present i nvent ion;
FIG. 6A-2 sh ow cr o ss-sectional views of the SEG p-GaN gate E-mode N-face A l GaN/GaN HE M T with polarity inversion according to the present invention;
FIG. 7E-2 sh ow schematic diagrams of f o rming the metal gate electrode and the bonding pads and interconnection metals f or drain and source in the SEG p-GaN …
FIG. 8A-2 show c ross-sectional views of the SEG p-GaN anode N-face A l GaN/GaN SBD with polarity inversion according to the present invention;
FIG. 9A shows an equivalent circuit diagram of a hybrid E-mode N-face A l GaN/GaN HEMT with p o larity inversi o n f o rmed by casc o ding an SEG E-m o de …
FIG. 10 A shows a schematic diagram of the equivalent circuit in
FIG. 11 A-2; Figures 12A to 12F-2 show schematic diagrams of the process steps f o r fabricating the structures in F I G. 11A-1 and F I G. 11 A-2 according to …
FIG. 12C. Next, use destructive io n implantat io n as sh own i n
FIG. 13A-2; Figures 1 4A-1 to 1 4 A-4 show schematic diagrams o f the process steps for fabricating the structures in
FIG. 15 shows an equivalent circuit diagram o f a hybrid N-face A l GaN/GaN SBD with polarity inversion f ormed by cascoding an SEG p-GaN anode N-face Al …
FIG. 16B sh o ws a t o p view of
FIG. 17B shows a t o p view o f
FIG. 18A-2 sh ow cr o ss-sectional views of the SEG p-GaN gate and self-aligned gate metal E-mo de G -face A l GaN/GaN HEMT with polarity inversion according …
FIG. 19A. First, use PECVD to deposit a layer of Si O₂ mas k 105 as a buffer layer. Thereby, during i on implantation, the peak value of the Gaussian …
FIG. 20A-2 show cr o ss-sectional views of the SEG p-GaN anode and self-aligned gate m etal E- mo de N-face A IG aN/G aN SBD with polarity inversion according …
FIG. 21A-2 show c ross-sectional views of the hybrid E -mode N-face AI GaN/GaN HEMT with polarity inversion according to the present invention;
FIG. 22G-2 show cro ss-sectional views of the process steps f o r
FIG. 23A-2 show cross-sectional views of the hybrid E- m ode N-face AIG aN/G aN HEMT with polarity inversion according to the present invention;
FIG. 24B-2 show cro ss-sectional views of the process steps f o r Figures 23A- 1 and 23A-2;
FIG. 26A- 1 and F I G. 26A-2 show cross-sectional views of the hybrid N- face Al GaN/GaN SBD with polarity inversion according to the present invention; and FI …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The structure of claim 1, wherein an i-A l z GaN grading buffer layer is further disposed between said C-doped i-GaN layer and said i-A ly GaN buffer layer and z=0.01 ~0.75.
A method for fabricating an enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion using said epitaxial structure of claim 1, comprising steps of: providing an epitaxia l structure of N-face AIGaN/GaN; and forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face A l GaN/GaN using selective epitaxial growth for controlling the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A i X GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of clai m 3, and in said step of forming said p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN, further comprising steps of: forming a silicon oxynitride mask layer on said epitaxial structure of N-face AI GaN/GaN; exposing and developing said silicon oxynitride mask layer for defining a gate selective epitaxial growth region; etching said gate selective epitaxial growth region using buffered oxide etchant for forming an inverted trapezoidal structure; growing p-GaN in said inverted trapezoidal structure for forming said p-GaN inverted trapezoidal gate structure; and removing said silicon oxynitride mask layer.
A selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of AI GaN/G aN; and a p-GaN inverted trapezoidal gate structure, located on an i-A l x GaN layer; where the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure is depleted, and said epitaxial structure of N-face AI GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i- C aN channel layer, located on said i-A ly GaN buffer layer; and said i-A l X GaN layer, located on said i-GaN channel layer; where x= O.1~0.3; y= 0.05-0.75.
A method for fabricating a hybrid enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion using said epitaxial structure of claim 1, comprising steps of: providing an epitaxial structure of N-face AlGaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right re gion; forming a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion in said left region by steps comprising: forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN using selective epitaxial growth for controlling the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; and forming a depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer in said right region; where said epitaxial structure of N-face A I GaN/GaN co m prises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-Al y GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A I X GaN layer, located on said i-GaN channel layer; where x= 0.10.3; y= 0.05~0.75.
The method of claim 6, wherein said selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion and said depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer are fabricated concurrent ly.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of N-face A I GaN/GaN, divided into a left region and a right region; a selective-epitaxia l -growth p-GaN gate enhancement-mode N-face Al GaN/GaN high electron mobi l ity transistor with polarity inversion, located in said left region, comprising a p-GaN inverted trapezoidal gate structure, and the two-dimensional electron gas below said p- GaN inverted trapezoidal gate structure being depleted; and a depletion-m o de N-face A l GaN/GaN high electron mobility transistor with polarity inversion and without gate dielectric layer, located in said right region; where said epitaxial structure of N-face AlGaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A lyG aN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A lx GaN layer, located on said i-GaN channel layer; where x =0.1-0.3; y =0.05~0.75.
A method for fabricating a hybrid enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion, comprising steps of: providing an epitaxial structure of N-face A t GaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right region; forming a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion in said left region by steps comprising: forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face AlGaN/GaN using selective epitaxial growth for control l ing the 38 two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure to be depleted; and forming a depletion-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion and gate dielectric layer in said right region; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i- C aN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= O.1~0.3; y= 0.050.75.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxial structure of N-face A l GaN/GaN, divided into a left region and a right region; a selective-epitaxial-growth p-GaN gate enhancement-mode N-face AI GaN/GaN high electron mobility transistor with polarity inversion, located in said left region, comprising a p-GaN inverted trapezoidal gate structure, and the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure being depleted; and a depletion-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion and gate dielectric layer, located in said right region; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A ly GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
11. A method for fabricating a selective-epitaxial-growth p-GaN gate enhancement-mode N-face A I GaN/GaN high electron mobility transistor with polarity inversion, comprising steps o f: providing an epitaxial structure of N-face AIGaN/GaN; forming a first source ion implantation region and a first drain ion implantation region in said i-A h x GaN layer; forming a p-GaN inverted trapezoidal gate structure on said epitaxial structure of N-face A l GaN/GaN using selective epitaxial growth; forming a f irst gate metal layer on said p-GaN inverted trapezoidal gate structure; and forming a first source metal layer and a f i rst drain metal layer on said epitaxia l structure of N-face A l GaN/GaN, said first source meta l layer located on said first source ion implantation region, and said first drain metal layer located on said first drain ion implantation region; where said epitaxial structure of N-face A I GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A iy GaN buffer layer; and an i-A l x GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of claim 11, and in said steps of forming said p-GaN inverted trapezoidal gate structure and said first gate metal layer, further comprising steps o f: forming a silicon oxynitride mas k layer on said epitaxia l structure of N-face AI GaN/GaN; fo rming an inverted trapez o idal structure by patterning said si licon o xynitride mask layer using a patterned photoresist layer and buffered oxide etchant; grow ing p-GaN in said inverted trapez o idal structure f o r f o rming said p-GaN inverted trapezoidal gate structure; fo rming a f ir st metal layer o n the surfaces of sa i d s ilicon o xynitride mas k layer and said p-GaN inverted trapezoidal gate structure; and removing said silicon oxynitride mask layer and said metal layer on said silicon o xynitride mas k layer, and reserving the fi rst metal layer o n the surface of said p-GaN inverted trapezoidal gate structure for acting as said first gate metal layer.
The meth o d of claim 1 1, and in said step of f o rming said first s o urc e ion implantation region and said first drain ion implantation region in said i-A X GaN layer, further comprising steps of: forming an ion implantation buffer layer on said epitaxial structure of N-face A₁ GaN/GaN; fo rming a patterned ph oto resist layer o n said i o n implantation buffer layer and exposing a portion of said ion implantation buffer layer; doping n-type si lico n to said i o n implantation buffer l ayer expo sed fro m said patterned photoresist layer and activating f or fo rmi ng said first source ion implantation region and said first drain i o n implantation region in said i-A l X GaN layer; and removing said patterned photoresist layer and said ion implantation buffer layer.
The method of claim 13, wherein said activation is performed by a thermal treatment at a te m perature between 6 00 and 9 000 SVG 16124596.09-07-2018.JLSAAS₁BRXEAPX3.CLM.7.24.1519.2515.1547.2549.svg 0.113 0.093 Chemistry Black and white
15. A selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, comprising: an epitaxia l structure of N-face AIGaN/GaN; a p-GaN inverted trap ezo idal gate structure, a fi rst s o urce metal layer, and a first drain metal layer, located on said i-A l X GaN layer, and the two-dimensional electr o n gas b elo w said p-GaN inverted trap ezo idal gate structure being depleted; a fir st s o urce io n implantat io n reg io n and a first dra in ion i mplantati o n reg ion, located in said i-A l X GaN layer, said first s o urce ion implantation region located below said fir st source metal layer, and said fir st drain ion im plantati o n regi o n l o cated below said first drain metal layer; and a first gate metal layer, located on said p-GaN inverted trapezoidal gate structu re; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i -GaN layer, l o cated o n said C-doped buffer layer; an i-A l y GaN buffer layer, located o n said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN bu ff er layer; and an i-A l X GaN layer, l o cated o n said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
A method for fabricating a hybrid enhancement-mode N-face A l GaN/GaN high electr o n mobility transistor with polarity inversion, comprising steps of: providing an epitaxial structure o f N-face A l GaN/GaN, and dividing said epitaxial structure of N-face A L GaN/GaN into a l eft region and a right region; forming a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A IG aN/GaN high electr on mo bility transistor with polarity inversion in said left region by steps comprising: fo rming a first s o urce i o n implantation regi o n and a first drain i on implantation region in said i-A l X GaN layer; fo rming a p-GaN inverted trapezoidal gate structure o n said epitaxial structure of N-face A lG aN/GaN using selective epitaxial growth and 42 the two-di m ensi o nal electr o n gas below said p-GaN inverted trapezoidal gate structure being depleted; fo rming a first gate metal layer o n said p-GaN inverted trapezoidal gate structure; and fo rming a first source metal layer and a f ir st drain metal layer o n sa id epitaxial structure of A l GaN/GaN, said first source metal layer located on said f ir st source ion implantation region, and said first drain m etal layer located o n said fi rst drain i o n i m plantation regi on; and fo rming a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and without gate dielectric layer in said right regi o n by steps comprising: forming a second source ion implantation region and a second drain ion i mplantati o n regi on i n said i-Al x GaN layer; and forming a second source metal layer and a second drain metal layer on said epitaxial structure of N-face A I GaN/GaN, said second source metal layer located o n said sec o nd s o urce i o n i m plantation regi on, and said second drain metal layer located on said second drain ion SVG 16124596.09-07-2018.JLSAAS₁BRXEAPX3.CLM.9.19.755.1897.804.1931.svg 0.113 0.163 Chemistry Black and white m plantati o n regi on; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN l ayer, l ocated on said C-doped buffer l ayer; an i-A ly GaN buffer layer, located on said C-doped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A l x G aN layer, located o n said i- G aN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
The method of claim 16, and in said step of forming said first source ion implantation regi o n, said first drain i o n implantation regi o n, said sec o nd s o urce io n implantation regi o n, and said sec o nd drain i o n implantation regi o n in said 43 i-A lx GaN layer, further c o mprising steps of: forming an ion implantation buffer layer on said epitaxial structure of N-face Al GaN/GaN; forming a patterned photoresist layer on said ion implantation buffer layer and expos i ng a portion of said ion i mplantat io n buffer layer; doping n-type silicon to said ion implantation buffer layer exposed from said patterned photoresist layer and activating for forming said first source ion implantati o n regi o n, said fi rst drain i o n implantati o n regi o n, said sec ond source ion implantation region, and said second drain ion implantation regi o n in said i-A l X GaN layer; and removing said patterned photoresist layer and said ion implantation buffer l ayer.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, c o mprising: an epitaxial structure of N-face A l GaN/GaN, divided into a left region and a right regi on; a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A l GaN/GaN high electron mobility transistor with polarity inversion, l ocated in said left region, comprising: a p-GaN inverted trapezoidal gate structure, a fi rst source metal layer, and a first drain metal layer, l ocated on said i-A l X GaN layer, and the two-dimensional electron gas below said p-GaN inverted trapezoida l gate structure being depleted; a first source ion implantation region and a first drain ion implantation regi o n, located in said i-A lx GaN layer, said first source i on implantation region located below said first source metal layer, and said first drain i o n implantation regi o n located below said first drain metal layer; and a f irst gate metal layer, l o cated o n said p-GaN inverted trapezoidal gate structure; and a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and without gate dielectric layer, located in said right reg io n, comprising: a second source metal layer and a second drain metal layer, located on said i-A l x GaN layer; and a sec o nd s o urce i o n i m plantati o n regi o n and a sec o nd drain i on implantation regi o n, located in said i-A l x GaN layer, said sec ond so urce i o n implantati o n regi o n l o cated below said sec o nd s o urce metal layer, and said sec o nd drain i o n implantati o n regi o n l o cated below said sec o nd drain metal layer; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, l o cated on said C-doped bu ff er layer; an i-A lyG aN buffer layer, l o cated o n said C-doped i-GaN layer; an i-GaN channel layer, l o cated on said i-Al y GaN buffer layer; and an i-A lx GaN layer, l o cated o n said i-GaN channel layer; where x =0.1~ 0.3; y =0.05~0.75.
A method f o r fabricating a hybrid enhancement-m o de N-face A l GaN/GaN high electr o n mobility transistor with polarity inversion, c om prising steps of: providing an epitaxial structure of N-face A t GaN/GaN, and dividing said epitaxial structure of N-face A l GaN/GaN into a left region and a right regi on; forming a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion in said left region by steps comprising: fo rming a f irst s o urce i o n implantati o n regi o n and a f irst drain i on implantati o n regi o n in said i-A l x GaN layer; fo rming a p-GaN inverted trapezoidal gate structure o n said epitaxia l structure of N-face A l GaN/GaN using selective epitaxial growth and the two-dimensional electr o n gas below said p-GaN inverted trapezoidal gate structure being depleted; fo rming a fir st gate metal layer o n sa i d p-GaN i nverted trapez oi dal gate structure; and forming a first source metal layer and a fi rst drain metal layer o n said epitaxial structure of N-face A IG aN/G aN, said fi rst s o urce metal layer located on said first source ion implantation regi o n, and said first drain metal layer l o cated o n said first drain i o n implantati on region; and fo rming a depletion-m o de N-face A l GaN/GaN high electr on mo bility transistor with polarity inversion and gate dielectric layer in said right region by steps comprising: forming a second source ion implantation region and a second drain ion implantation region in said i-A lx GaN layer; fo rming a sec o nd s o urce metal layer and a sec o nd drain metal layer on said epitaxial structure of N-face A l GaN/GaN, said second source metal layer l o cated o n said sec o nd s o urce i o n implantati o n regi on, and said second drain metal layer located on said second drain ion implantati o n regi o n; and forming a gate dielectric layer on said epitaxial structure of N-face AI GaN/GaN; where said epitaxial structure of N-face A l GaN/GaN comprises: a substrate; a C-d o ped buffer layer, l o cated o n said substrate; a C-doped i-GaN layer, located on said C-doped buffer layer; an i-A ly GaN buffer layer, l o cated o n said C-d o ped i-GaN layer; an i-GaN channel layer, located on said i-Al y GaN buffer layer; and an i-A l X GaN layer, l o cated o n said i-GaN channel layer; where x= 0.10.3; y= 0.05~0.75.
The method of claim 20, and in said step of forming said first source ion implantati o n regi o n, said first drain i o n implantati o n regi o n, said sec o nd s o urce ion implantation region, and said second drain ion implantation region in said i-Alx GaN layer, further comprising steps of: fo rming an i o n implantation buffer layer o n said epitaxial structure o f N-face Al GaN/GaN; fo rming a patterned ph oto resist layer o n said i o n implantati o n bu ff er layer and exposing a portion of said ion implantation buffer layer; doping n-type silicon to said i o n implantation buffer l ayer exposed fro m said patterned photoresist layer and activating for forming said first source ion implantation regi o n, said first drain i o n implantation regi o n, said sec ond source ion implantation region, and said second drain ion implantation reg io n in sa id i-Al x GaN layer; and removing said patterned photoresist layer and said ion implantation buffer l ayer.
A hybrid enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion of claim 1, comprising: an epitaxial structure o f N-face A l GaN/GaN, divided into a left region and a right region; a selective-epitaxial-growth p-GaN gate and self-aligned gate metal enhancement-mode N-face A l GaN/GaN high electron mobility transistor with polarity inversion, located in said left regi o n, co m prising: a p-GaN inverted trapezoidal gate structure, a first source metal layer, and a first drain metal layer, located o n said i-A l X GaN layer, and the two-dimensional electron gas below said p-GaN inverted trapezoidal gate structure being depleted; a first s o urce i o n implantation regi o n and a first drain ion implantation 47 regi o n, l o cated in said i-A l x GaN layer, said first s o urce i on implantation region located bel o w said first source metal layer, and said first drain i o n implantati o n regi o n l o cated bel o w said first drain metal layer; and a f ir st gate metal layer, located o n sa i d p-GaN i nverted trapez oi dal gate structure; and a depletion-mode N-face A I GaN/GaN high electron mobility transistor with gate dielectric layer, located in said right regi o n, comprising: a second source metal layer and a second drain metal layer, located on said i-A l y GaN layer; a gate dielectric layer, located on said i-A l X GaN layer and between said sec o nd s o urce metal layer and said sec o nd drain metal layer; and a second source ion implantation region and a second drain ion i mplantati o n reg io n, l o cated i n sa i d i-A l y GaN layer, sa i d sec ond source ion implantation regi o n located below said second source metal layer, and said second drain ion implantation region located below said sec o nd drain metal layer; where said epitaxial structure of N-face A I GaN/GaN comprises: a substrate; a C-doped buffer layer, located on said substrate; a C-doped i-GaN layer, l ocated o n said C-doped buffer layer; an i-A ly GaN buffer layer, located o n said C-doped i-GaN layer; an i-GaN channel layer, located on said i-A Iy GaN buffer layer; and an i-A l y GaN layer, located on said i-GaN channel layer; where x= 0.1~0.3; y= 0.05~0.75.
Layer stacks claimed or described, ordered top of device to substrate.
selective-epitaxial-growth p-GaN gate enhancement-mode N-face AlGaN/GaN HEMT with polarity inversion
Materials described outside the worked examples.
C-doped buffer layer
C-doped i-GaN layer
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4B ~ 4D show the operations of the SEG p-GaN gate E-m o de N-face AIGaN/GaN HEMT with polarity inversion at a fixed Vd and va r ying gate voltages Vg …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 nm | — |
Thickness | ≥ 2500 nm |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE (GAN) POWER AMPLIFIERS (PA) WITH ANGLED ELECTRODES AND 100 CMOS AND METHOD FOR PRODUCING THE SAME
GALLIUM NITRIDE (GAN) SELECTIVE EPITAXIAL WINDOWS FOR INTEGRATED CIRCUIT TECHNOLOGY
depletion-mode N-face AlGaN/GaN HEMT with polarity inversion and without gate dielectric layer
depletion-mode N-face AlGaN/GaN HEMT with polarity inversion and gate dielectric layer
i-AlyGaN buffer layer
AlyGaN (y=0.05~0.75)
i-AlxGaN layer
AlxGaN (x=0.1~0.3)
i-AlzGaN grading buffer layer
AlzGaN (z=0.01~0.75)
silicon oxynitride mask layer
SiOxNy
buffered oxide etchant
substrate
silicon substrate
Si
FIG. 11 A-2; Figures 12A to 12F-2 show schematic diagrams of the process steps f o r fabricating the structures in F I G. 11A-1 and F I G. 11 A-2 according to …
FIG. 19A. First, use PECVD to deposit a layer of Si O₂ mas k 105 as a buffer layer. Thereby, during i on implantation, the peak value of the Gaussian …
| — |
Temperature | ≥ 1 k | — |
depletion-mode N-face AlGaN/GaN HEMT with polarity inversion and without gate dielectric layer
depletion-mode N-face AlGaN/GaN HEMT with polarity inversion and gate dielectric layer
i-AlyGaN buffer layer
AlyGaN (y=0.05~0.75)
i-AlxGaN layer
AlxGaN (x=0.1~0.3)
i-AlzGaN grading buffer layer
AlzGaN (z=0.01~0.75)
silicon oxynitride mask layer
SiOxNy
buffered oxide etchant
substrate
silicon substrate
Si
FIG. 11 A-2; Figures 12A to 12F-2 show schematic diagrams of the process steps f o r fabricating the structures in F I G. 11A-1 and F I G. 11 A-2 according to …
FIG. 19A. First, use PECVD to deposit a layer of Si O₂ mas k 105 as a buffer layer. Thereby, during i on implantation, the peak value of the Gaussian …
| — |
Temperature | ≥ 1 k | — |
depletion-mode N-face AlGaN/GaN HEMT with polarity inversion and without gate dielectric layer
depletion-mode N-face AlGaN/GaN HEMT with polarity inversion and gate dielectric layer
i-AlyGaN buffer layer
AlyGaN (y=0.05~0.75)
i-AlxGaN layer
AlxGaN (x=0.1~0.3)
i-AlzGaN grading buffer layer
AlzGaN (z=0.01~0.75)
silicon oxynitride mask layer
SiOxNy
buffered oxide etchant
substrate
silicon substrate
Si
FIG. 11 A-2; Figures 12A to 12F-2 show schematic diagrams of the process steps f o r fabricating the structures in F I G. 11A-1 and F I G. 11 A-2 according to …
FIG. 19A. First, use PECVD to deposit a layer of Si O₂ mas k 105 as a buffer layer. Thereby, during i on implantation, the peak value of the Gaussian …
| — |
Temperature | ≥ 1 k | — |
depletion-mode N-face AlGaN/GaN HEMT with polarity inversion and without gate dielectric layer
depletion-mode N-face AlGaN/GaN HEMT with polarity inversion and gate dielectric layer
i-AlyGaN buffer layer
AlyGaN (y=0.05~0.75)
i-AlxGaN layer
AlxGaN (x=0.1~0.3)
i-AlzGaN grading buffer layer
AlzGaN (z=0.01~0.75)
silicon oxynitride mask layer
SiOxNy
buffered oxide etchant
substrate
silicon substrate
Si
FIG. 11 A-2; Figures 12A to 12F-2 show schematic diagrams of the process steps f o r fabricating the structures in F I G. 11A-1 and F I G. 11 A-2 according to …
FIG. 19A. First, use PECVD to deposit a layer of Si O₂ mas k 105 as a buffer layer. Thereby, during i on implantation, the peak value of the Gaussian …
| — |
Temperature | ≥ 1 k | — |