Patent
Atlas literature
Patent
US 12,512,312 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 and 2 are simplified diagrams of a vertical FET device configured on a GaN substrate according to an example of the present invention.
FIG. 3 illustrates data collected using a capacitance volt- age technique on a SiN coated low-doped GaN sample 30 according to an example of the present …
FIGS. 4 to 12 illustrate a method of fabricating the vertical FET device according to an example of the present invention.
FIG. 5. 3.) High-quality low pressure chemical vapor deposited 40 SiN applied as gate dielectric, see
FIG. 6. 4.) ATi/Al based ohmic contact is applied to the top of the n+ layer of the fins by first etching through the SiN and lifting off the ohmic contact …
FIG. 7. 5.) Isolation/termination implant is performed to make an insulating region in the GaN, see
FIG. 8. 6.) Gate metal is lifted off at an angle to coat sidewalls to overlap the n+ region, see
FIG. 9. 50 7.) A thick field oxide is deposited by PECVD and vias etched to the source contact and the gate contact pad, see
FIG. 10. 8.) A source pad is lifted off and comprised of a highly conducting metal such as Al, Cu, Au, or combinations 55 thereof, see
FIG. 11. 9.) The n+ GaN substrate is thinned down to 25 to 100 µm. The substrate surface is then cleaned and chemically treated and an ohmic contact applied. …
FIG. 12. As shown the high voltage switching device is configured from a drain region configured from the backside region of the gallium and nitrogen containing …
FIGS. 13A to 19 illustrate experimental results according 35 to examples of the present invention.
FIGS. 14A, B, C. The PECVD was carried out at a GaN substrate temperature of 350° C. with silane and ammonia 10 sources. The nominal thickness was 30 nm. For …
FIGS. 15A, B, C illustrates SIMS profile of elements present in the Al₂O₃/GaN structure produced by ALD with TMA. In forming the MIS structures for …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
FIG. 17 gives the CV curves on a LPCVD silicon nitride sample at measurement frequencies from 1 kHz to 1 MHz.
FIG. 18 gives the CV curves on a ALD aluminum oxide sample at measurement frequencies from 1 kHz to 1 MHz.
FIG. 19 illustrates bidirectional CV curves taken on 45 PECVD MIS structure at measurement frequencies of 1 kHz and 1 MHz. Each dielectric in a MIS structure …
FIG. 20 illustrates a field plate structure overlying a dielectric material for a device according to an example of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a high power FET device, the method comprising: providing a substrate comprising a first side and a second side, the first side comprising an n-type drift material, and overlying intrinsic gallium nitride material, and an n+ type gallium nitride contact material; forming a plurality of fingers comprising an entirety of a thickness of a portion of the n+ type gallium nitride contact material and a portion of the intrinsic gallium nitride material, each of the fingers extending into a predetermined thickness of the n-type drift material such than each of the fingers has a length greater than the entirety of the thickness of the n+ type gallium nitride contract material and the portion of the intrinsic gallium nitride material; causing exposure of a portion of the n-type drift material between a pair of the plurality of fingers; forming a high quality silicon nitride material having a carbon content with a volume concentration of less than 1018 cm⁻³ overlying a surface of each of the plurality of fingers and exposed portions of the n-type drift material between each pair of the plurality of fingers; exposing a portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming a contact region overlying the exposed portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming an insulation region comprising a plurality of implanted species on each side of the plurality of fingers to a predetermined depth to withstand a prede-termined voltage; forming a gate metal region between each of the plurality of fingers and along a sidewall of a pair of plurality of fingers; forming a planarized dielectric material overlying exposed surfaces of the gate metal region, plurality of fingers, isolation region, and contact region; and exposing the source contact region and a gate contact region from the gate metal region.
The method of claim 1 wherein n-type drift material, overlying intrinsic gallium nitride material, and then n+ type gallium nitride contract material are formed using an epi-taxial growth process.
The method of claim 1 wherein the high quality silicon nitride material is deposited using a low pressure chemical vapor deposition process, and predetermined pressure.
The method of claim 1 wherein the contact region comprises a Ti/Al based ohmic contact on and in contact with the portion of the n+ type gallium and nitride contact material the Ti/Al based ohmic contact has been sintered using a controlled ambient process.
The method of claim 1 wherein the implanted species comprises a selected species having a predetermined con-centration.
The method of claim 1 wherein the gate metal regions comprises a gate metal material configured using a lift off at an angle to coat each of the sidewalls to overlap a portion of the n+ type gallium nitride contract material.
The method of claim 1 wherein the planarized dielectric material is a thick field oxide material deposited by PECVD.
The method of claim 1 wherein the source contact region is made using a lift off process to expose a highly conductive material selected from Al, Cu, Au, or combina-tions thereof.
The method of claim 1 further comprising removing a thickness of a backside portion of the substrate using a thinning process to leave a thickness of about 25 to 100 µm.
A method for fabricating a high power FET device, the method comprising: providing a substrate comprising a first side and a second side, the first side comprising an n-type drift material, and overlying intrinsic gallium nitride material, and an n+ type gallium nitride contact material; forming a plurality of fingers comprising an entirety of a thickness of a portion of the n+ type gallium nitride contact material and a portion of the intrinsic gallium nitride material, each of the fingers extending into a predetermined thickness of the n-type drift material such than each of the fingers has a length greater than the entirety of the thickness of the n+ type gallium nitride contract material and the portion of the intrinsic gallium nitride material; causing exposure of a portion of the n-type drift material between a pair of the plurality of fingers; forming a high quality silicon nitride material having a carbon species with a volume concentration of less than 1018 cm⁻³. overlying a surface of each of the plurality of fingers and exposed portions of the n-type drift material between each pair of the plurality of fingers; exposing a portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming a contact region overlying the exposed portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming an insulation region comprising a plurality of implanted species on each side of the plurality of fingers to a predetermined depth to withstand a prede-termined voltage; forming a gate metal region between each of the plurality of fingers and along a sidewall of a pair of plurality of fingers, forming a planarized dielectric material overlying exposed surfaces of the gate metal region, plurality of fingers, isolation region, and contact region; exposing the source contact region and a gate contact region from the gate metal region; removing a thickness of a backside portion of the substrate using a thinning process to leave a thickness of about 25 to 100 µm; cleaning surfaces of the substrate, and then forming a metal material overlying the backside portion using a low temperature <600° C. anneal for a time of prede-termined seconds and less to form an ohmic contact after formation of the metal material; and singulating each device from a wafer.
The method of claim 13 wherein n-type drift material, overlying intrinsic gallium nitride material, and then n+ type gallium nitride contract material are formed using an epi-taxial growth process.
The method of claim 13 wherein the high quality silicon nitride material is deposited using a low pressure chemical vapor deposition process, and predetermined pres-sure.
The method of claim 13 wherein the contact region comprises a Ti/Al based ohmic contact on and in contact with the portion of the n+ type gallium and nitride contact material the Ti/Al based ohmic contact has been sintered using a controlled ambient process.
The method of claim 13 wherein the implanted species comprises a selected species having a predetermined con-centration.
The method of claim 13 wherein the gate metal regions comprises a gate metal material configured using a lift off at an angle to coat each of the sidewalls to overlap a portion of the n+ type gallium nitride contract material.
The method of claim 13 wherein the planarized dielectric material is a thick field oxide material deposited by PECVD.
The method of claim 13 wherein the source contact region is made using a lift off process to expose a highly conductive material selected from Al, Cu, Au, or combina-tions thereof. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN FET
Materials described outside the worked examples.
high quality silicon nitride
Si₃N₄
intrinsic gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 and 2 are simplified diagrams of a vertical FET device configured on a GaN substrate according to an example of the present invention.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Carbon Volume Concentration | ≤ 1000000000000000000 cm⁻³ | Si₃N₄ |
Carbon Volume Concentration |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Cited non-patent literature · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,512,312 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 and 2 are simplified diagrams of a vertical FET device configured on a GaN substrate according to an example of the present invention.
FIG. 3 illustrates data collected using a capacitance volt- age technique on a SiN coated low-doped GaN sample 30 according to an example of the present …
FIGS. 4 to 12 illustrate a method of fabricating the vertical FET device according to an example of the present invention.
FIG. 5. 3.) High-quality low pressure chemical vapor deposited 40 SiN applied as gate dielectric, see
FIG. 6. 4.) ATi/Al based ohmic contact is applied to the top of the n+ layer of the fins by first etching through the SiN and lifting off the ohmic contact …
FIG. 7. 5.) Isolation/termination implant is performed to make an insulating region in the GaN, see
FIG. 8. 6.) Gate metal is lifted off at an angle to coat sidewalls to overlap the n+ region, see
FIG. 9. 50 7.) A thick field oxide is deposited by PECVD and vias etched to the source contact and the gate contact pad, see
FIG. 10. 8.) A source pad is lifted off and comprised of a highly conducting metal such as Al, Cu, Au, or combinations 55 thereof, see
FIG. 11. 9.) The n+ GaN substrate is thinned down to 25 to 100 µm. The substrate surface is then cleaned and chemically treated and an ohmic contact applied. …
FIG. 12. As shown the high voltage switching device is configured from a drain region configured from the backside region of the gallium and nitrogen containing …
FIGS. 13A to 19 illustrate experimental results according 35 to examples of the present invention.
FIGS. 14A, B, C. The PECVD was carried out at a GaN substrate temperature of 350° C. with silane and ammonia 10 sources. The nominal thickness was 30 nm. For …
FIGS. 15A, B, C illustrates SIMS profile of elements present in the Al₂O₃/GaN structure produced by ALD with TMA. In forming the MIS structures for …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
FIG. 17 gives the CV curves on a LPCVD silicon nitride sample at measurement frequencies from 1 kHz to 1 MHz.
FIG. 18 gives the CV curves on a ALD aluminum oxide sample at measurement frequencies from 1 kHz to 1 MHz.
FIG. 19 illustrates bidirectional CV curves taken on 45 PECVD MIS structure at measurement frequencies of 1 kHz and 1 MHz. Each dielectric in a MIS structure …
FIG. 20 illustrates a field plate structure overlying a dielectric material for a device according to an example of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a high power FET device, the method comprising: providing a substrate comprising a first side and a second side, the first side comprising an n-type drift material, and overlying intrinsic gallium nitride material, and an n+ type gallium nitride contact material; forming a plurality of fingers comprising an entirety of a thickness of a portion of the n+ type gallium nitride contact material and a portion of the intrinsic gallium nitride material, each of the fingers extending into a predetermined thickness of the n-type drift material such than each of the fingers has a length greater than the entirety of the thickness of the n+ type gallium nitride contract material and the portion of the intrinsic gallium nitride material; causing exposure of a portion of the n-type drift material between a pair of the plurality of fingers; forming a high quality silicon nitride material having a carbon content with a volume concentration of less than 1018 cm⁻³ overlying a surface of each of the plurality of fingers and exposed portions of the n-type drift material between each pair of the plurality of fingers; exposing a portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming a contact region overlying the exposed portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming an insulation region comprising a plurality of implanted species on each side of the plurality of fingers to a predetermined depth to withstand a prede-termined voltage; forming a gate metal region between each of the plurality of fingers and along a sidewall of a pair of plurality of fingers; forming a planarized dielectric material overlying exposed surfaces of the gate metal region, plurality of fingers, isolation region, and contact region; and exposing the source contact region and a gate contact region from the gate metal region.
The method of claim 1 wherein n-type drift material, overlying intrinsic gallium nitride material, and then n+ type gallium nitride contract material are formed using an epi-taxial growth process.
The method of claim 1 wherein the high quality silicon nitride material is deposited using a low pressure chemical vapor deposition process, and predetermined pressure.
The method of claim 1 wherein the contact region comprises a Ti/Al based ohmic contact on and in contact with the portion of the n+ type gallium and nitride contact material the Ti/Al based ohmic contact has been sintered using a controlled ambient process.
The method of claim 1 wherein the implanted species comprises a selected species having a predetermined con-centration.
The method of claim 1 wherein the gate metal regions comprises a gate metal material configured using a lift off at an angle to coat each of the sidewalls to overlap a portion of the n+ type gallium nitride contract material.
The method of claim 1 wherein the planarized dielectric material is a thick field oxide material deposited by PECVD.
The method of claim 1 wherein the source contact region is made using a lift off process to expose a highly conductive material selected from Al, Cu, Au, or combina-tions thereof.
The method of claim 1 further comprising removing a thickness of a backside portion of the substrate using a thinning process to leave a thickness of about 25 to 100 µm.
A method for fabricating a high power FET device, the method comprising: providing a substrate comprising a first side and a second side, the first side comprising an n-type drift material, and overlying intrinsic gallium nitride material, and an n+ type gallium nitride contact material; forming a plurality of fingers comprising an entirety of a thickness of a portion of the n+ type gallium nitride contact material and a portion of the intrinsic gallium nitride material, each of the fingers extending into a predetermined thickness of the n-type drift material such than each of the fingers has a length greater than the entirety of the thickness of the n+ type gallium nitride contract material and the portion of the intrinsic gallium nitride material; causing exposure of a portion of the n-type drift material between a pair of the plurality of fingers; forming a high quality silicon nitride material having a carbon species with a volume concentration of less than 1018 cm⁻³. overlying a surface of each of the plurality of fingers and exposed portions of the n-type drift material between each pair of the plurality of fingers; exposing a portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming a contact region overlying the exposed portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming an insulation region comprising a plurality of implanted species on each side of the plurality of fingers to a predetermined depth to withstand a prede-termined voltage; forming a gate metal region between each of the plurality of fingers and along a sidewall of a pair of plurality of fingers, forming a planarized dielectric material overlying exposed surfaces of the gate metal region, plurality of fingers, isolation region, and contact region; exposing the source contact region and a gate contact region from the gate metal region; removing a thickness of a backside portion of the substrate using a thinning process to leave a thickness of about 25 to 100 µm; cleaning surfaces of the substrate, and then forming a metal material overlying the backside portion using a low temperature <600° C. anneal for a time of prede-termined seconds and less to form an ohmic contact after formation of the metal material; and singulating each device from a wafer.
The method of claim 13 wherein n-type drift material, overlying intrinsic gallium nitride material, and then n+ type gallium nitride contract material are formed using an epi-taxial growth process.
The method of claim 13 wherein the high quality silicon nitride material is deposited using a low pressure chemical vapor deposition process, and predetermined pres-sure.
The method of claim 13 wherein the contact region comprises a Ti/Al based ohmic contact on and in contact with the portion of the n+ type gallium and nitride contact material the Ti/Al based ohmic contact has been sintered using a controlled ambient process.
The method of claim 13 wherein the implanted species comprises a selected species having a predetermined con-centration.
The method of claim 13 wherein the gate metal regions comprises a gate metal material configured using a lift off at an angle to coat each of the sidewalls to overlap a portion of the n+ type gallium nitride contract material.
The method of claim 13 wherein the planarized dielectric material is a thick field oxide material deposited by PECVD.
The method of claim 13 wherein the source contact region is made using a lift off process to expose a highly conductive material selected from Al, Cu, Au, or combina-tions thereof. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN FET
Materials described outside the worked examples.
high quality silicon nitride
Si₃N₄
intrinsic gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 and 2 are simplified diagrams of a vertical FET device configured on a GaN substrate according to an example of the present invention.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Carbon Volume Concentration | ≤ 1000000000000000000 cm⁻³ | Si₃N₄ |
Carbon Volume Concentration |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Cited non-patent literature · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,512,312 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 and 2 are simplified diagrams of a vertical FET device configured on a GaN substrate according to an example of the present invention.
FIG. 3 illustrates data collected using a capacitance volt- age technique on a SiN coated low-doped GaN sample 30 according to an example of the present …
FIGS. 4 to 12 illustrate a method of fabricating the vertical FET device according to an example of the present invention.
FIG. 5. 3.) High-quality low pressure chemical vapor deposited 40 SiN applied as gate dielectric, see
FIG. 6. 4.) ATi/Al based ohmic contact is applied to the top of the n+ layer of the fins by first etching through the SiN and lifting off the ohmic contact …
FIG. 7. 5.) Isolation/termination implant is performed to make an insulating region in the GaN, see
FIG. 8. 6.) Gate metal is lifted off at an angle to coat sidewalls to overlap the n+ region, see
FIG. 9. 50 7.) A thick field oxide is deposited by PECVD and vias etched to the source contact and the gate contact pad, see
FIG. 10. 8.) A source pad is lifted off and comprised of a highly conducting metal such as Al, Cu, Au, or combinations 55 thereof, see
FIG. 11. 9.) The n+ GaN substrate is thinned down to 25 to 100 µm. The substrate surface is then cleaned and chemically treated and an ohmic contact applied. …
FIG. 12. As shown the high voltage switching device is configured from a drain region configured from the backside region of the gallium and nitrogen containing …
FIGS. 13A to 19 illustrate experimental results according 35 to examples of the present invention.
FIGS. 14A, B, C. The PECVD was carried out at a GaN substrate temperature of 350° C. with silane and ammonia 10 sources. The nominal thickness was 30 nm. For …
FIGS. 15A, B, C illustrates SIMS profile of elements present in the Al₂O₃/GaN structure produced by ALD with TMA. In forming the MIS structures for …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
FIG. 17 gives the CV curves on a LPCVD silicon nitride sample at measurement frequencies from 1 kHz to 1 MHz.
FIG. 18 gives the CV curves on a ALD aluminum oxide sample at measurement frequencies from 1 kHz to 1 MHz.
FIG. 19 illustrates bidirectional CV curves taken on 45 PECVD MIS structure at measurement frequencies of 1 kHz and 1 MHz. Each dielectric in a MIS structure …
FIG. 20 illustrates a field plate structure overlying a dielectric material for a device according to an example of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a high power FET device, the method comprising: providing a substrate comprising a first side and a second side, the first side comprising an n-type drift material, and overlying intrinsic gallium nitride material, and an n+ type gallium nitride contact material; forming a plurality of fingers comprising an entirety of a thickness of a portion of the n+ type gallium nitride contact material and a portion of the intrinsic gallium nitride material, each of the fingers extending into a predetermined thickness of the n-type drift material such than each of the fingers has a length greater than the entirety of the thickness of the n+ type gallium nitride contract material and the portion of the intrinsic gallium nitride material; causing exposure of a portion of the n-type drift material between a pair of the plurality of fingers; forming a high quality silicon nitride material having a carbon content with a volume concentration of less than 1018 cm⁻³ overlying a surface of each of the plurality of fingers and exposed portions of the n-type drift material between each pair of the plurality of fingers; exposing a portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming a contact region overlying the exposed portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming an insulation region comprising a plurality of implanted species on each side of the plurality of fingers to a predetermined depth to withstand a prede-termined voltage; forming a gate metal region between each of the plurality of fingers and along a sidewall of a pair of plurality of fingers; forming a planarized dielectric material overlying exposed surfaces of the gate metal region, plurality of fingers, isolation region, and contact region; and exposing the source contact region and a gate contact region from the gate metal region.
The method of claim 1 wherein n-type drift material, overlying intrinsic gallium nitride material, and then n+ type gallium nitride contract material are formed using an epi-taxial growth process.
The method of claim 1 wherein the high quality silicon nitride material is deposited using a low pressure chemical vapor deposition process, and predetermined pressure.
The method of claim 1 wherein the contact region comprises a Ti/Al based ohmic contact on and in contact with the portion of the n+ type gallium and nitride contact material the Ti/Al based ohmic contact has been sintered using a controlled ambient process.
The method of claim 1 wherein the implanted species comprises a selected species having a predetermined con-centration.
The method of claim 1 wherein the gate metal regions comprises a gate metal material configured using a lift off at an angle to coat each of the sidewalls to overlap a portion of the n+ type gallium nitride contract material.
The method of claim 1 wherein the planarized dielectric material is a thick field oxide material deposited by PECVD.
The method of claim 1 wherein the source contact region is made using a lift off process to expose a highly conductive material selected from Al, Cu, Au, or combina-tions thereof.
The method of claim 1 further comprising removing a thickness of a backside portion of the substrate using a thinning process to leave a thickness of about 25 to 100 µm.
A method for fabricating a high power FET device, the method comprising: providing a substrate comprising a first side and a second side, the first side comprising an n-type drift material, and overlying intrinsic gallium nitride material, and an n+ type gallium nitride contact material; forming a plurality of fingers comprising an entirety of a thickness of a portion of the n+ type gallium nitride contact material and a portion of the intrinsic gallium nitride material, each of the fingers extending into a predetermined thickness of the n-type drift material such than each of the fingers has a length greater than the entirety of the thickness of the n+ type gallium nitride contract material and the portion of the intrinsic gallium nitride material; causing exposure of a portion of the n-type drift material between a pair of the plurality of fingers; forming a high quality silicon nitride material having a carbon species with a volume concentration of less than 1018 cm⁻³. overlying a surface of each of the plurality of fingers and exposed portions of the n-type drift material between each pair of the plurality of fingers; exposing a portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming a contact region overlying the exposed portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming an insulation region comprising a plurality of implanted species on each side of the plurality of fingers to a predetermined depth to withstand a prede-termined voltage; forming a gate metal region between each of the plurality of fingers and along a sidewall of a pair of plurality of fingers, forming a planarized dielectric material overlying exposed surfaces of the gate metal region, plurality of fingers, isolation region, and contact region; exposing the source contact region and a gate contact region from the gate metal region; removing a thickness of a backside portion of the substrate using a thinning process to leave a thickness of about 25 to 100 µm; cleaning surfaces of the substrate, and then forming a metal material overlying the backside portion using a low temperature <600° C. anneal for a time of prede-termined seconds and less to form an ohmic contact after formation of the metal material; and singulating each device from a wafer.
The method of claim 13 wherein n-type drift material, overlying intrinsic gallium nitride material, and then n+ type gallium nitride contract material are formed using an epi-taxial growth process.
The method of claim 13 wherein the high quality silicon nitride material is deposited using a low pressure chemical vapor deposition process, and predetermined pres-sure.
The method of claim 13 wherein the contact region comprises a Ti/Al based ohmic contact on and in contact with the portion of the n+ type gallium and nitride contact material the Ti/Al based ohmic contact has been sintered using a controlled ambient process.
The method of claim 13 wherein the implanted species comprises a selected species having a predetermined con-centration.
The method of claim 13 wherein the gate metal regions comprises a gate metal material configured using a lift off at an angle to coat each of the sidewalls to overlap a portion of the n+ type gallium nitride contract material.
The method of claim 13 wherein the planarized dielectric material is a thick field oxide material deposited by PECVD.
The method of claim 13 wherein the source contact region is made using a lift off process to expose a highly conductive material selected from Al, Cu, Au, or combina-tions thereof. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN FET
Materials described outside the worked examples.
high quality silicon nitride
Si₃N₄
intrinsic gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 and 2 are simplified diagrams of a vertical FET device configured on a GaN substrate according to an example of the present invention.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Carbon Volume Concentration | ≤ 1000000000000000000 cm⁻³ | Si₃N₄ |
Carbon Volume Concentration |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Cited non-patent literature · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,512,312 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 and 2 are simplified diagrams of a vertical FET device configured on a GaN substrate according to an example of the present invention.
FIG. 3 illustrates data collected using a capacitance volt- age technique on a SiN coated low-doped GaN sample 30 according to an example of the present …
FIGS. 4 to 12 illustrate a method of fabricating the vertical FET device according to an example of the present invention.
FIG. 5. 3.) High-quality low pressure chemical vapor deposited 40 SiN applied as gate dielectric, see
FIG. 6. 4.) ATi/Al based ohmic contact is applied to the top of the n+ layer of the fins by first etching through the SiN and lifting off the ohmic contact …
FIG. 7. 5.) Isolation/termination implant is performed to make an insulating region in the GaN, see
FIG. 8. 6.) Gate metal is lifted off at an angle to coat sidewalls to overlap the n+ region, see
FIG. 9. 50 7.) A thick field oxide is deposited by PECVD and vias etched to the source contact and the gate contact pad, see
FIG. 10. 8.) A source pad is lifted off and comprised of a highly conducting metal such as Al, Cu, Au, or combinations 55 thereof, see
FIG. 11. 9.) The n+ GaN substrate is thinned down to 25 to 100 µm. The substrate surface is then cleaned and chemically treated and an ohmic contact applied. …
FIG. 12. As shown the high voltage switching device is configured from a drain region configured from the backside region of the gallium and nitrogen containing …
FIGS. 13A to 19 illustrate experimental results according 35 to examples of the present invention.
FIGS. 14A, B, C. The PECVD was carried out at a GaN substrate temperature of 350° C. with silane and ammonia 10 sources. The nominal thickness was 30 nm. For …
FIGS. 15A, B, C illustrates SIMS profile of elements present in the Al₂O₃/GaN structure produced by ALD with TMA. In forming the MIS structures for …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
FIG. 17 gives the CV curves on a LPCVD silicon nitride sample at measurement frequencies from 1 kHz to 1 MHz.
FIG. 18 gives the CV curves on a ALD aluminum oxide sample at measurement frequencies from 1 kHz to 1 MHz.
FIG. 19 illustrates bidirectional CV curves taken on 45 PECVD MIS structure at measurement frequencies of 1 kHz and 1 MHz. Each dielectric in a MIS structure …
FIG. 20 illustrates a field plate structure overlying a dielectric material for a device according to an example of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a high power FET device, the method comprising: providing a substrate comprising a first side and a second side, the first side comprising an n-type drift material, and overlying intrinsic gallium nitride material, and an n+ type gallium nitride contact material; forming a plurality of fingers comprising an entirety of a thickness of a portion of the n+ type gallium nitride contact material and a portion of the intrinsic gallium nitride material, each of the fingers extending into a predetermined thickness of the n-type drift material such than each of the fingers has a length greater than the entirety of the thickness of the n+ type gallium nitride contract material and the portion of the intrinsic gallium nitride material; causing exposure of a portion of the n-type drift material between a pair of the plurality of fingers; forming a high quality silicon nitride material having a carbon content with a volume concentration of less than 1018 cm⁻³ overlying a surface of each of the plurality of fingers and exposed portions of the n-type drift material between each pair of the plurality of fingers; exposing a portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming a contact region overlying the exposed portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming an insulation region comprising a plurality of implanted species on each side of the plurality of fingers to a predetermined depth to withstand a prede-termined voltage; forming a gate metal region between each of the plurality of fingers and along a sidewall of a pair of plurality of fingers; forming a planarized dielectric material overlying exposed surfaces of the gate metal region, plurality of fingers, isolation region, and contact region; and exposing the source contact region and a gate contact region from the gate metal region.
The method of claim 1 wherein n-type drift material, overlying intrinsic gallium nitride material, and then n+ type gallium nitride contract material are formed using an epi-taxial growth process.
The method of claim 1 wherein the high quality silicon nitride material is deposited using a low pressure chemical vapor deposition process, and predetermined pressure.
The method of claim 1 wherein the contact region comprises a Ti/Al based ohmic contact on and in contact with the portion of the n+ type gallium and nitride contact material the Ti/Al based ohmic contact has been sintered using a controlled ambient process.
The method of claim 1 wherein the implanted species comprises a selected species having a predetermined con-centration.
The method of claim 1 wherein the gate metal regions comprises a gate metal material configured using a lift off at an angle to coat each of the sidewalls to overlap a portion of the n+ type gallium nitride contract material.
The method of claim 1 wherein the planarized dielectric material is a thick field oxide material deposited by PECVD.
The method of claim 1 wherein the source contact region is made using a lift off process to expose a highly conductive material selected from Al, Cu, Au, or combina-tions thereof.
The method of claim 1 further comprising removing a thickness of a backside portion of the substrate using a thinning process to leave a thickness of about 25 to 100 µm.
A method for fabricating a high power FET device, the method comprising: providing a substrate comprising a first side and a second side, the first side comprising an n-type drift material, and overlying intrinsic gallium nitride material, and an n+ type gallium nitride contact material; forming a plurality of fingers comprising an entirety of a thickness of a portion of the n+ type gallium nitride contact material and a portion of the intrinsic gallium nitride material, each of the fingers extending into a predetermined thickness of the n-type drift material such than each of the fingers has a length greater than the entirety of the thickness of the n+ type gallium nitride contract material and the portion of the intrinsic gallium nitride material; causing exposure of a portion of the n-type drift material between a pair of the plurality of fingers; forming a high quality silicon nitride material having a carbon species with a volume concentration of less than 1018 cm⁻³. overlying a surface of each of the plurality of fingers and exposed portions of the n-type drift material between each pair of the plurality of fingers; exposing a portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming a contact region overlying the exposed portion of the n+ type gallium and nitride contact material on each of the plurality of fingers; forming an insulation region comprising a plurality of implanted species on each side of the plurality of fingers to a predetermined depth to withstand a prede-termined voltage; forming a gate metal region between each of the plurality of fingers and along a sidewall of a pair of plurality of fingers, forming a planarized dielectric material overlying exposed surfaces of the gate metal region, plurality of fingers, isolation region, and contact region; exposing the source contact region and a gate contact region from the gate metal region; removing a thickness of a backside portion of the substrate using a thinning process to leave a thickness of about 25 to 100 µm; cleaning surfaces of the substrate, and then forming a metal material overlying the backside portion using a low temperature <600° C. anneal for a time of prede-termined seconds and less to form an ohmic contact after formation of the metal material; and singulating each device from a wafer.
The method of claim 13 wherein n-type drift material, overlying intrinsic gallium nitride material, and then n+ type gallium nitride contract material are formed using an epi-taxial growth process.
The method of claim 13 wherein the high quality silicon nitride material is deposited using a low pressure chemical vapor deposition process, and predetermined pres-sure.
The method of claim 13 wherein the contact region comprises a Ti/Al based ohmic contact on and in contact with the portion of the n+ type gallium and nitride contact material the Ti/Al based ohmic contact has been sintered using a controlled ambient process.
The method of claim 13 wherein the implanted species comprises a selected species having a predetermined con-centration.
The method of claim 13 wherein the gate metal regions comprises a gate metal material configured using a lift off at an angle to coat each of the sidewalls to overlap a portion of the n+ type gallium nitride contract material.
The method of claim 13 wherein the planarized dielectric material is a thick field oxide material deposited by PECVD.
The method of claim 13 wherein the source contact region is made using a lift off process to expose a highly conductive material selected from Al, Cu, Au, or combina-tions thereof. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN FET
Materials described outside the worked examples.
high quality silicon nitride
Si₃N₄
intrinsic gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 and 2 are simplified diagrams of a vertical FET device configured on a GaN substrate according to an example of the present invention.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Carbon Volume Concentration | ≤ 1000000000000000000 cm⁻³ | Si₃N₄ |
Carbon Volume Concentration |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Cited non-patent literature · 3
Related documents with shared materials, methods, properties, or citations.
Metal-Insulator-Semiconductor (MIS) structure on GaN
n-type drift material
Ti/Al based ohmic contact
Ti/Al
thick field oxide
source contact metal
dichlorosilane
SiH₂Cl₂
ammonia
NH₃
FIGS. 4 to 12 illustrate a method of fabricating the vertical FET device according to an example of the present invention.
FIGS. 14A, B, C. The PECVD was carried out at a GaN substrate temperature of 350° C. with silane and ammonia 10 sources. The nominal thickness was 30 nm. For …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
Si₃N₄ |
Oxygen Volume Concentration | ≤ 200000000000000000000 cm⁻³ | Si₃N₄ |
Oxygen Volume Concentration | ≤ 10000000000000000000 cm⁻³ | Si₃N₄ |
Hydrogen Volume Concentration | <1 % volume | Si₃N₄ |
Thickness | 100–1000 nm | — |
Thickness | 5–50 nm | — |
Thickness | 25–100 µm | — |
Thickness | 10–75 µm | — |
Thickness | 0.25–2 µm | — |
Thickness | ≤ 1 µm | — |
Temperature | ≤ 600 °C | — |
Temperature | ≤ 350 °C | — |
Thickness | ≤ 1000000000000000000 cm | — |
Thickness | ≤ 10000000000000000000 cm | — |
Temperature | ≥ 700 °C | — |
Pressure | ≥ 1 pA | — |
Metal-Insulator-Semiconductor (MIS) structure on GaN
n-type drift material
Ti/Al based ohmic contact
Ti/Al
thick field oxide
source contact metal
dichlorosilane
SiH₂Cl₂
ammonia
NH₃
FIGS. 4 to 12 illustrate a method of fabricating the vertical FET device according to an example of the present invention.
FIGS. 14A, B, C. The PECVD was carried out at a GaN substrate temperature of 350° C. with silane and ammonia 10 sources. The nominal thickness was 30 nm. For …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
Si₃N₄ |
Oxygen Volume Concentration | ≤ 200000000000000000000 cm⁻³ | Si₃N₄ |
Oxygen Volume Concentration | ≤ 10000000000000000000 cm⁻³ | Si₃N₄ |
Hydrogen Volume Concentration | <1 % volume | Si₃N₄ |
Thickness | 100–1000 nm | — |
Thickness | 5–50 nm | — |
Thickness | 25–100 µm | — |
Thickness | 10–75 µm | — |
Thickness | 0.25–2 µm | — |
Thickness | ≤ 1 µm | — |
Temperature | ≤ 600 °C | — |
Temperature | ≤ 350 °C | — |
Thickness | ≤ 1000000000000000000 cm | — |
Thickness | ≤ 10000000000000000000 cm | — |
Temperature | ≥ 700 °C | — |
Pressure | ≥ 1 pA | — |
Metal-Insulator-Semiconductor (MIS) structure on GaN
n-type drift material
Ti/Al based ohmic contact
Ti/Al
thick field oxide
source contact metal
dichlorosilane
SiH₂Cl₂
ammonia
NH₃
FIGS. 4 to 12 illustrate a method of fabricating the vertical FET device according to an example of the present invention.
FIGS. 14A, B, C. The PECVD was carried out at a GaN substrate temperature of 350° C. with silane and ammonia 10 sources. The nominal thickness was 30 nm. For …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
Si₃N₄ |
Oxygen Volume Concentration | ≤ 200000000000000000000 cm⁻³ | Si₃N₄ |
Oxygen Volume Concentration | ≤ 10000000000000000000 cm⁻³ | Si₃N₄ |
Hydrogen Volume Concentration | <1 % volume | Si₃N₄ |
Thickness | 100–1000 nm | — |
Thickness | 5–50 nm | — |
Thickness | 25–100 µm | — |
Thickness | 10–75 µm | — |
Thickness | 0.25–2 µm | — |
Thickness | ≤ 1 µm | — |
Temperature | ≤ 600 °C | — |
Temperature | ≤ 350 °C | — |
Thickness | ≤ 1000000000000000000 cm | — |
Thickness | ≤ 10000000000000000000 cm | — |
Temperature | ≥ 700 °C | — |
Pressure | ≥ 1 pA | — |
Metal-Insulator-Semiconductor (MIS) structure on GaN
n-type drift material
Ti/Al based ohmic contact
Ti/Al
thick field oxide
source contact metal
dichlorosilane
SiH₂Cl₂
ammonia
NH₃
FIGS. 4 to 12 illustrate a method of fabricating the vertical FET device according to an example of the present invention.
FIGS. 14A, B, C. The PECVD was carried out at a GaN substrate temperature of 350° C. with silane and ammonia 10 sources. The nominal thickness was 30 nm. For …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
FIG. 16. Greater pinhole densities produce larger measured currents at forward biases greater than 1 volt along with a noticeable increase in reverse leakage …
Si₃N₄ |
Oxygen Volume Concentration | ≤ 200000000000000000000 cm⁻³ | Si₃N₄ |
Oxygen Volume Concentration | ≤ 10000000000000000000 cm⁻³ | Si₃N₄ |
Hydrogen Volume Concentration | <1 % volume | Si₃N₄ |
Thickness | 100–1000 nm | — |
Thickness | 5–50 nm | — |
Thickness | 25–100 µm | — |
Thickness | 10–75 µm | — |
Thickness | 0.25–2 µm | — |
Thickness | ≤ 1 µm | — |
Temperature | ≤ 600 °C | — |
Temperature | ≤ 350 °C | — |
Thickness | ≤ 1000000000000000000 cm | — |
Thickness | ≤ 10000000000000000000 cm | — |
Temperature | ≥ 700 °C | — |
Pressure | ≥ 1 pA | — |
