Patent
US 8,981,432METHOD AND SYSTEM FOR GALLIUM NITRIDE ELECTRONIC DEVICES USING ENGINEERED SUBSTRATES
Hui Nie, Donald R. Disney, Isik C. Kizilyalli
AVOGY, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 8,981,432Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 and 2, embodiments of the present invention are not limited to GaN seed layers. Other I II-V materials, in particular, III- nitride materials, are …
FIG. 2, a buffer layer 201 (e.g., an n+ GaN buffer layer) is formed, for example, using a metalorganic 10 chemical vapor deposition (MOC V D) process on the …
FIG. 3. Multiple top electrodes 1201 and 1202 are fabricated in the embodiment illustrated in
FIG. 4 is a simplified cross-sectional diagram illustrating joining of a carrier wafer according to an embodiment of the present invention. Referring to
FIG. 5 illustrates partial removal of the handle substrate using, for example, a thinning, grinding, or other removal process. Although not illustrated in 20
FIG. 6, the handle substrate, the bonding layer and the seed layer 102 have been removed as described above to expose the buffer layer 201 and a bottom …
FIG. 7, a device substrate 5 1001 (also referred to as an electrical and thermal substrate because of the properties discussed below) is joined to the bottom …
FIG. 8. As illustrated in
FIG. 9A, a Schottky contact is formed as the top electrode, providing a Schottky 5 barrier to lightly doped n-type GaN-based drift layer. [0047] By using an …
FIG. 10 is a vertical junction field effect transistor (JFET), which can be fabricated using techniques discussed in more detail in U.S. Patent Application No. …
FIG. 11, this is not required by the present invention and PNP designs can be utilized as well. Doping and thickness of the various layers of 10 the BJT are …
FIG. 12. The structure is then flip-chip bonded to substrate 1220 using bonds 1210. Thus, flip-chip bonding can be 20 used after the formation of the functional …
FIG. 13 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. The method 1300 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method for fabricating an electronic device, the method 2 comprising: 3 providing an engineered substrate structure comprising a III -nitride seed layer; 4 forming GaN-based functional layers coupled to the I II -nitride seed layer; 5 forming a first electrode structure electrically coupled to at least a portion of the 6 GaN-based functional layers; 7 joining a carrier substrate opposing the GaN-based functional layers; 8 removing at least a portion of the engineered substrate structure; 9 forming a second electrode structure electrically coupled to at least another 10 portion of the GaN-based functional layers; and 11 removing the carrier substrate. withdrawn
1 2. The method of claim 1 further comprising joining a device 2 substrate to the second electrode prior to removing the carrier substrate. withdrawn
1 3. The method of claim 1 wherein the I II -nitride seed layer 2 comprises a GaN material. withdrawn
1 4. The method of claim 1 wherein the III -nitride seed layer 2 comprises an n-type GaN-based material. withdrawn
1 5. The method of claim 1 further comprising epitaxially 2 growing a III -nitride buffer layer coupled to the I II -nitride seed layer and a III -nitride drift layer 3 coupled to the I II -nitride buffer layer. withdrawn
1 7. The method of claim 1 wherein joining the carrier wafer to 2 the GaN-based functional layers comprises: 3 forming an electrode structure coupled to at least a portion of one of the GaN-4 based functional layers; 5 forming a sacrificial bonding layer coupled to another portion of the one of the 6 GaN-based functional layers and at least a portion of the electrode structure; and 7 bonding the carrier wafer to the sacrificial bonding layer. withdrawn
1 9. The method of claim 1 wherein the engineered substrate 2 comprises a handle wafer and a bonding layer coupled to the I II -nitride seed layer, and wherein 3 removing at least a portion of the engineered substrate structure comprises mechanically 4 removing the handle wafer, chemically etching the bonding layer, and physically etching the III- 5 nitride seed layer. withdrawn
1 10. A vertical I II -nitride electronic device comprising: 2 a first electrical contact structure; SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.1.svg 0.16 6.83 Black and white 4 the first electrical contact structure; SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.2.svg 0.16 6.46 Black and white 6 epitaxial buffer layer; and SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.3.svg 0.16 6.65 Black and white 8 the I II -nitride epitaxial drift la yer. et e-
1 11. The vertical I II -nitride electronic device of claim 10 2 wherein the I II -nitride epitaxial buffer layer comprises an n-type GaN layer.
1 12. The vertical I II -nitride electronic device of claim 10 wherein 2 the first conductivity type comprises an n-type.
1 13. The vertical I II -nitride electronic device of claim 10 2 wherein the I II -nitride epitaxial drift la yer sm ue comprises an n-type GaN layer and one or 3 more additional GaN layers.
1 15. The vertical I II -nitride electronic device of claim 10 further 2 comprising a device substrate supporting the first electrical contact structure.
1 16. A vertical I II -nitride JF E T comprising: 2 a device substrate; 3 an interface layer coupled to the device substrate; 4 a first electrode structure coupled to the interface layer; 5 a III-nitride epitaxial layer connected to the first electrode structure; 6 a III -nitride drift layer epitaxially coupled to the I II -nitride epitaxial layer; 7 a III -nitride channel region epitaxially coupled to the I II -nitride drift layer; 8 a III -nitride source region epitaxially coupled to the I II-nitride channel region; 9 and 10 one or more gate regions disposed adjacent the I II -nitride channel region s 11 wherein the interface la y er, the first electrode structure, the I II -nitride epitaxial 12 la v er, the I II -nitride drift layer, the I II -nitride channel region, and the I II -nitride source region are 13 all on the same side of the substrate.
1 17. The vertical I II -nitride JFET of claim 16 f u rther comprising a 2 source electrode structure coupled to the I II -nitride source region.
1 18. The vertical I II -nitride JF E T of claim 16 f u rther comprising one 2 or more gate electrode structures coupled to the one or more gate regions.
1 19. The vertical I II -nitride JF E T of claim 16 wherein a thickness of 2 the interface layer ranges from about 0.1 p m to about 1 pm.
1 20. The vertical I II -nitride JF E T of claim 16 wherein a thickness of 2 the I II -nitride drift layer ranges from about 1 m to about 100 pm.
1 21. The vertical I II -nitride JF E T of claim 16 wherein a distance 2 measured from the first electrode structure to the I II -nitride drift layer is less than 10 pm.
1 22. The vertical I II -nitride JF E T of claim 16 wherein the I II -nitride 2 epitaxial layer and the I II -nitride drift layer are silicon-doped n-type layers.
Layer stacks claimed or described, ordered top of device to substrate.
vertical III-nitride electronic device
vertical III-nitride JFET
Materials described outside the worked examples.
III-nitride seed layer
GaN-based functional layers
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 and 2, embodiments of the present invention are not limited to GaN seed layers. Other I II-V materials, in particular, III- nitride materials, are …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
interface layer thickness | 0.1–1 µm | — |
III-nitride drift layer thickness | 1–100 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,981,432Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 and 2, embodiments of the present invention are not limited to GaN seed layers. Other I II-V materials, in particular, III- nitride materials, are …
FIG. 2, a buffer layer 201 (e.g., an n+ GaN buffer layer) is formed, for example, using a metalorganic 10 chemical vapor deposition (MOC V D) process on the …
FIG. 3. Multiple top electrodes 1201 and 1202 are fabricated in the embodiment illustrated in
FIG. 4 is a simplified cross-sectional diagram illustrating joining of a carrier wafer according to an embodiment of the present invention. Referring to
FIG. 5 illustrates partial removal of the handle substrate using, for example, a thinning, grinding, or other removal process. Although not illustrated in 20
FIG. 6, the handle substrate, the bonding layer and the seed layer 102 have been removed as described above to expose the buffer layer 201 and a bottom …
FIG. 7, a device substrate 5 1001 (also referred to as an electrical and thermal substrate because of the properties discussed below) is joined to the bottom …
FIG. 8. As illustrated in
FIG. 9A, a Schottky contact is formed as the top electrode, providing a Schottky 5 barrier to lightly doped n-type GaN-based drift layer. [0047] By using an …
FIG. 10 is a vertical junction field effect transistor (JFET), which can be fabricated using techniques discussed in more detail in U.S. Patent Application No. …
FIG. 11, this is not required by the present invention and PNP designs can be utilized as well. Doping and thickness of the various layers of 10 the BJT are …
FIG. 12. The structure is then flip-chip bonded to substrate 1220 using bonds 1210. Thus, flip-chip bonding can be 20 used after the formation of the functional …
FIG. 13 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. The method 1300 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method for fabricating an electronic device, the method 2 comprising: 3 providing an engineered substrate structure comprising a III -nitride seed layer; 4 forming GaN-based functional layers coupled to the I II -nitride seed layer; 5 forming a first electrode structure electrically coupled to at least a portion of the 6 GaN-based functional layers; 7 joining a carrier substrate opposing the GaN-based functional layers; 8 removing at least a portion of the engineered substrate structure; 9 forming a second electrode structure electrically coupled to at least another 10 portion of the GaN-based functional layers; and 11 removing the carrier substrate. withdrawn
1 2. The method of claim 1 further comprising joining a device 2 substrate to the second electrode prior to removing the carrier substrate. withdrawn
1 3. The method of claim 1 wherein the I II -nitride seed layer 2 comprises a GaN material. withdrawn
1 4. The method of claim 1 wherein the III -nitride seed layer 2 comprises an n-type GaN-based material. withdrawn
1 5. The method of claim 1 further comprising epitaxially 2 growing a III -nitride buffer layer coupled to the I II -nitride seed layer and a III -nitride drift layer 3 coupled to the I II -nitride buffer layer. withdrawn
1 7. The method of claim 1 wherein joining the carrier wafer to 2 the GaN-based functional layers comprises: 3 forming an electrode structure coupled to at least a portion of one of the GaN-4 based functional layers; 5 forming a sacrificial bonding layer coupled to another portion of the one of the 6 GaN-based functional layers and at least a portion of the electrode structure; and 7 bonding the carrier wafer to the sacrificial bonding layer. withdrawn
1 9. The method of claim 1 wherein the engineered substrate 2 comprises a handle wafer and a bonding layer coupled to the I II -nitride seed layer, and wherein 3 removing at least a portion of the engineered substrate structure comprises mechanically 4 removing the handle wafer, chemically etching the bonding layer, and physically etching the III- 5 nitride seed layer. withdrawn
1 10. A vertical I II -nitride electronic device comprising: 2 a first electrical contact structure; SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.1.svg 0.16 6.83 Black and white 4 the first electrical contact structure; SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.2.svg 0.16 6.46 Black and white 6 epitaxial buffer layer; and SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.3.svg 0.16 6.65 Black and white 8 the I II -nitride epitaxial drift la yer. et e-
1 11. The vertical I II -nitride electronic device of claim 10 2 wherein the I II -nitride epitaxial buffer layer comprises an n-type GaN layer.
1 12. The vertical I II -nitride electronic device of claim 10 wherein 2 the first conductivity type comprises an n-type.
1 13. The vertical I II -nitride electronic device of claim 10 2 wherein the I II -nitride epitaxial drift la yer sm ue comprises an n-type GaN layer and one or 3 more additional GaN layers.
1 15. The vertical I II -nitride electronic device of claim 10 further 2 comprising a device substrate supporting the first electrical contact structure.
1 16. A vertical I II -nitride JF E T comprising: 2 a device substrate; 3 an interface layer coupled to the device substrate; 4 a first electrode structure coupled to the interface layer; 5 a III-nitride epitaxial layer connected to the first electrode structure; 6 a III -nitride drift layer epitaxially coupled to the I II -nitride epitaxial layer; 7 a III -nitride channel region epitaxially coupled to the I II -nitride drift layer; 8 a III -nitride source region epitaxially coupled to the I II-nitride channel region; 9 and 10 one or more gate regions disposed adjacent the I II -nitride channel region s 11 wherein the interface la y er, the first electrode structure, the I II -nitride epitaxial 12 la v er, the I II -nitride drift layer, the I II -nitride channel region, and the I II -nitride source region are 13 all on the same side of the substrate.
1 17. The vertical I II -nitride JFET of claim 16 f u rther comprising a 2 source electrode structure coupled to the I II -nitride source region.
1 18. The vertical I II -nitride JF E T of claim 16 f u rther comprising one 2 or more gate electrode structures coupled to the one or more gate regions.
1 19. The vertical I II -nitride JF E T of claim 16 wherein a thickness of 2 the interface layer ranges from about 0.1 p m to about 1 pm.
1 20. The vertical I II -nitride JF E T of claim 16 wherein a thickness of 2 the I II -nitride drift layer ranges from about 1 m to about 100 pm.
1 21. The vertical I II -nitride JF E T of claim 16 wherein a distance 2 measured from the first electrode structure to the I II -nitride drift layer is less than 10 pm.
1 22. The vertical I II -nitride JF E T of claim 16 wherein the I II -nitride 2 epitaxial layer and the I II -nitride drift layer are silicon-doped n-type layers.
Layer stacks claimed or described, ordered top of device to substrate.
vertical III-nitride electronic device
vertical III-nitride JFET
Materials described outside the worked examples.
III-nitride seed layer
GaN-based functional layers
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 and 2, embodiments of the present invention are not limited to GaN seed layers. Other I II-V materials, in particular, III- nitride materials, are …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
interface layer thickness | 0.1–1 µm | — |
III-nitride drift layer thickness | 1–100 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,981,432Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 and 2, embodiments of the present invention are not limited to GaN seed layers. Other I II-V materials, in particular, III- nitride materials, are …
FIG. 2, a buffer layer 201 (e.g., an n+ GaN buffer layer) is formed, for example, using a metalorganic 10 chemical vapor deposition (MOC V D) process on the …
FIG. 3. Multiple top electrodes 1201 and 1202 are fabricated in the embodiment illustrated in
FIG. 4 is a simplified cross-sectional diagram illustrating joining of a carrier wafer according to an embodiment of the present invention. Referring to
FIG. 5 illustrates partial removal of the handle substrate using, for example, a thinning, grinding, or other removal process. Although not illustrated in 20
FIG. 6, the handle substrate, the bonding layer and the seed layer 102 have been removed as described above to expose the buffer layer 201 and a bottom …
FIG. 7, a device substrate 5 1001 (also referred to as an electrical and thermal substrate because of the properties discussed below) is joined to the bottom …
FIG. 8. As illustrated in
FIG. 9A, a Schottky contact is formed as the top electrode, providing a Schottky 5 barrier to lightly doped n-type GaN-based drift layer. [0047] By using an …
FIG. 10 is a vertical junction field effect transistor (JFET), which can be fabricated using techniques discussed in more detail in U.S. Patent Application No. …
FIG. 11, this is not required by the present invention and PNP designs can be utilized as well. Doping and thickness of the various layers of 10 the BJT are …
FIG. 12. The structure is then flip-chip bonded to substrate 1220 using bonds 1210. Thus, flip-chip bonding can be 20 used after the formation of the functional …
FIG. 13 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. The method 1300 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method for fabricating an electronic device, the method 2 comprising: 3 providing an engineered substrate structure comprising a III -nitride seed layer; 4 forming GaN-based functional layers coupled to the I II -nitride seed layer; 5 forming a first electrode structure electrically coupled to at least a portion of the 6 GaN-based functional layers; 7 joining a carrier substrate opposing the GaN-based functional layers; 8 removing at least a portion of the engineered substrate structure; 9 forming a second electrode structure electrically coupled to at least another 10 portion of the GaN-based functional layers; and 11 removing the carrier substrate. withdrawn
1 2. The method of claim 1 further comprising joining a device 2 substrate to the second electrode prior to removing the carrier substrate. withdrawn
1 3. The method of claim 1 wherein the I II -nitride seed layer 2 comprises a GaN material. withdrawn
1 4. The method of claim 1 wherein the III -nitride seed layer 2 comprises an n-type GaN-based material. withdrawn
1 5. The method of claim 1 further comprising epitaxially 2 growing a III -nitride buffer layer coupled to the I II -nitride seed layer and a III -nitride drift layer 3 coupled to the I II -nitride buffer layer. withdrawn
1 7. The method of claim 1 wherein joining the carrier wafer to 2 the GaN-based functional layers comprises: 3 forming an electrode structure coupled to at least a portion of one of the GaN-4 based functional layers; 5 forming a sacrificial bonding layer coupled to another portion of the one of the 6 GaN-based functional layers and at least a portion of the electrode structure; and 7 bonding the carrier wafer to the sacrificial bonding layer. withdrawn
1 9. The method of claim 1 wherein the engineered substrate 2 comprises a handle wafer and a bonding layer coupled to the I II -nitride seed layer, and wherein 3 removing at least a portion of the engineered substrate structure comprises mechanically 4 removing the handle wafer, chemically etching the bonding layer, and physically etching the III- 5 nitride seed layer. withdrawn
1 10. A vertical I II -nitride electronic device comprising: 2 a first electrical contact structure; SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.1.svg 0.16 6.83 Black and white 4 the first electrical contact structure; SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.2.svg 0.16 6.46 Black and white 6 epitaxial buffer layer; and SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.3.svg 0.16 6.65 Black and white 8 the I II -nitride epitaxial drift la yer. et e-
1 11. The vertical I II -nitride electronic device of claim 10 2 wherein the I II -nitride epitaxial buffer layer comprises an n-type GaN layer.
1 12. The vertical I II -nitride electronic device of claim 10 wherein 2 the first conductivity type comprises an n-type.
1 13. The vertical I II -nitride electronic device of claim 10 2 wherein the I II -nitride epitaxial drift la yer sm ue comprises an n-type GaN layer and one or 3 more additional GaN layers.
1 15. The vertical I II -nitride electronic device of claim 10 further 2 comprising a device substrate supporting the first electrical contact structure.
1 16. A vertical I II -nitride JF E T comprising: 2 a device substrate; 3 an interface layer coupled to the device substrate; 4 a first electrode structure coupled to the interface layer; 5 a III-nitride epitaxial layer connected to the first electrode structure; 6 a III -nitride drift layer epitaxially coupled to the I II -nitride epitaxial layer; 7 a III -nitride channel region epitaxially coupled to the I II -nitride drift layer; 8 a III -nitride source region epitaxially coupled to the I II-nitride channel region; 9 and 10 one or more gate regions disposed adjacent the I II -nitride channel region s 11 wherein the interface la y er, the first electrode structure, the I II -nitride epitaxial 12 la v er, the I II -nitride drift layer, the I II -nitride channel region, and the I II -nitride source region are 13 all on the same side of the substrate.
1 17. The vertical I II -nitride JFET of claim 16 f u rther comprising a 2 source electrode structure coupled to the I II -nitride source region.
1 18. The vertical I II -nitride JF E T of claim 16 f u rther comprising one 2 or more gate electrode structures coupled to the one or more gate regions.
1 19. The vertical I II -nitride JF E T of claim 16 wherein a thickness of 2 the interface layer ranges from about 0.1 p m to about 1 pm.
1 20. The vertical I II -nitride JF E T of claim 16 wherein a thickness of 2 the I II -nitride drift layer ranges from about 1 m to about 100 pm.
1 21. The vertical I II -nitride JF E T of claim 16 wherein a distance 2 measured from the first electrode structure to the I II -nitride drift layer is less than 10 pm.
1 22. The vertical I II -nitride JF E T of claim 16 wherein the I II -nitride 2 epitaxial layer and the I II -nitride drift layer are silicon-doped n-type layers.
Layer stacks claimed or described, ordered top of device to substrate.
vertical III-nitride electronic device
vertical III-nitride JFET
Materials described outside the worked examples.
III-nitride seed layer
GaN-based functional layers
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 and 2, embodiments of the present invention are not limited to GaN seed layers. Other I II-V materials, in particular, III- nitride materials, are …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
interface layer thickness | 0.1–1 µm | — |
III-nitride drift layer thickness | 1–100 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,981,432Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 and 2, embodiments of the present invention are not limited to GaN seed layers. Other I II-V materials, in particular, III- nitride materials, are …
FIG. 2, a buffer layer 201 (e.g., an n+ GaN buffer layer) is formed, for example, using a metalorganic 10 chemical vapor deposition (MOC V D) process on the …
FIG. 3. Multiple top electrodes 1201 and 1202 are fabricated in the embodiment illustrated in
FIG. 4 is a simplified cross-sectional diagram illustrating joining of a carrier wafer according to an embodiment of the present invention. Referring to
FIG. 5 illustrates partial removal of the handle substrate using, for example, a thinning, grinding, or other removal process. Although not illustrated in 20
FIG. 6, the handle substrate, the bonding layer and the seed layer 102 have been removed as described above to expose the buffer layer 201 and a bottom …
FIG. 7, a device substrate 5 1001 (also referred to as an electrical and thermal substrate because of the properties discussed below) is joined to the bottom …
FIG. 8. As illustrated in
FIG. 9A, a Schottky contact is formed as the top electrode, providing a Schottky 5 barrier to lightly doped n-type GaN-based drift layer. [0047] By using an …
FIG. 10 is a vertical junction field effect transistor (JFET), which can be fabricated using techniques discussed in more detail in U.S. Patent Application No. …
FIG. 11, this is not required by the present invention and PNP designs can be utilized as well. Doping and thickness of the various layers of 10 the BJT are …
FIG. 12. The structure is then flip-chip bonded to substrate 1220 using bonds 1210. Thus, flip-chip bonding can be 20 used after the formation of the functional …
FIG. 13 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. The method 1300 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method for fabricating an electronic device, the method 2 comprising: 3 providing an engineered substrate structure comprising a III -nitride seed layer; 4 forming GaN-based functional layers coupled to the I II -nitride seed layer; 5 forming a first electrode structure electrically coupled to at least a portion of the 6 GaN-based functional layers; 7 joining a carrier substrate opposing the GaN-based functional layers; 8 removing at least a portion of the engineered substrate structure; 9 forming a second electrode structure electrically coupled to at least another 10 portion of the GaN-based functional layers; and 11 removing the carrier substrate. withdrawn
1 2. The method of claim 1 further comprising joining a device 2 substrate to the second electrode prior to removing the carrier substrate. withdrawn
1 3. The method of claim 1 wherein the I II -nitride seed layer 2 comprises a GaN material. withdrawn
1 4. The method of claim 1 wherein the III -nitride seed layer 2 comprises an n-type GaN-based material. withdrawn
1 5. The method of claim 1 further comprising epitaxially 2 growing a III -nitride buffer layer coupled to the I II -nitride seed layer and a III -nitride drift layer 3 coupled to the I II -nitride buffer layer. withdrawn
1 7. The method of claim 1 wherein joining the carrier wafer to 2 the GaN-based functional layers comprises: 3 forming an electrode structure coupled to at least a portion of one of the GaN-4 based functional layers; 5 forming a sacrificial bonding layer coupled to another portion of the one of the 6 GaN-based functional layers and at least a portion of the electrode structure; and 7 bonding the carrier wafer to the sacrificial bonding layer. withdrawn
1 9. The method of claim 1 wherein the engineered substrate 2 comprises a handle wafer and a bonding layer coupled to the I II -nitride seed layer, and wherein 3 removing at least a portion of the engineered substrate structure comprises mechanically 4 removing the handle wafer, chemically etching the bonding layer, and physically etching the III- 5 nitride seed layer. withdrawn
1 10. A vertical I II -nitride electronic device comprising: 2 a first electrical contact structure; SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.1.svg 0.16 6.83 Black and white 4 the first electrical contact structure; SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.2.svg 0.16 6.46 Black and white 6 epitaxial buffer layer; and SVG 13572408.09-19-2014.I₀A₄₄A₈₆PXXIFW3.CLM.3.svg 0.16 6.65 Black and white 8 the I II -nitride epitaxial drift la yer. et e-
1 11. The vertical I II -nitride electronic device of claim 10 2 wherein the I II -nitride epitaxial buffer layer comprises an n-type GaN layer.
1 12. The vertical I II -nitride electronic device of claim 10 wherein 2 the first conductivity type comprises an n-type.
1 13. The vertical I II -nitride electronic device of claim 10 2 wherein the I II -nitride epitaxial drift la yer sm ue comprises an n-type GaN layer and one or 3 more additional GaN layers.
1 15. The vertical I II -nitride electronic device of claim 10 further 2 comprising a device substrate supporting the first electrical contact structure.
1 16. A vertical I II -nitride JF E T comprising: 2 a device substrate; 3 an interface layer coupled to the device substrate; 4 a first electrode structure coupled to the interface layer; 5 a III-nitride epitaxial layer connected to the first electrode structure; 6 a III -nitride drift layer epitaxially coupled to the I II -nitride epitaxial layer; 7 a III -nitride channel region epitaxially coupled to the I II -nitride drift layer; 8 a III -nitride source region epitaxially coupled to the I II-nitride channel region; 9 and 10 one or more gate regions disposed adjacent the I II -nitride channel region s 11 wherein the interface la y er, the first electrode structure, the I II -nitride epitaxial 12 la v er, the I II -nitride drift layer, the I II -nitride channel region, and the I II -nitride source region are 13 all on the same side of the substrate.
1 17. The vertical I II -nitride JFET of claim 16 f u rther comprising a 2 source electrode structure coupled to the I II -nitride source region.
1 18. The vertical I II -nitride JF E T of claim 16 f u rther comprising one 2 or more gate electrode structures coupled to the one or more gate regions.
1 19. The vertical I II -nitride JF E T of claim 16 wherein a thickness of 2 the interface layer ranges from about 0.1 p m to about 1 pm.
1 20. The vertical I II -nitride JF E T of claim 16 wherein a thickness of 2 the I II -nitride drift layer ranges from about 1 m to about 100 pm.
1 21. The vertical I II -nitride JF E T of claim 16 wherein a distance 2 measured from the first electrode structure to the I II -nitride drift layer is less than 10 pm.
1 22. The vertical I II -nitride JF E T of claim 16 wherein the I II -nitride 2 epitaxial layer and the I II -nitride drift layer are silicon-doped n-type layers.
Layer stacks claimed or described, ordered top of device to substrate.
vertical III-nitride electronic device
vertical III-nitride JFET
Materials described outside the worked examples.
III-nitride seed layer
GaN-based functional layers
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1 and 2, embodiments of the present invention are not limited to GaN seed layers. Other I II-V materials, in particular, III- nitride materials, are …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
interface layer thickness | 0.1–1 µm | — |
III-nitride drift layer thickness | 1–100 µm |
Related documents with shared materials, methods, properties, or citations.
GaN seed layer
GaN
n-type GaN-based seed material
III-nitride buffer layer
III-nitride drift layer
III-nitride epitaxial buffer layer
III-nitride epitaxial drift layer
III-nitride epitaxial layer (JFET buffer/contact)
III-nitride drift layer (JFET)
III-nitride channel region
III-nitride source region
FIG. 3. Multiple top electrodes 1201 and 1202 are fabricated in the embodiment illustrated in
FIG. 6, the handle substrate, the bonding layer and the seed layer 102 have been removed as described above to expose the buffer layer 201 and a bottom …
FIG. 7, a device substrate 5 1001 (also referred to as an electrical and thermal substrate because of the properties discussed below) is joined to the bottom …
FIG. 10 is a vertical junction field effect transistor (JFET), which can be fabricated using techniques discussed in more detail in U.S. Patent Application No. …
FIG. 11, this is not required by the present invention and PNP designs can be utilized as well. Doping and thickness of the various layers of 10 the BJT are …
FIG. 12. The structure is then flip-chip bonded to substrate 1220 using bonds 1210. Thus, flip-chip bonding can be 20 used after the formation of the functional …
distance from first electrode structure to III-nitride drift layer | ≤ 10 µm | — |
oxygen concentration in III-nitride epitaxial layer and drift layer | ≤ 200000000 cm⁻³ | — |
silicon concentration in III-nitride epitaxial layer | ≥ 1000000000000000000 cm⁻³ | III-nitride epitaxial layer (JFET buffer/contact) |
GaN seed layer
GaN
n-type GaN-based seed material
III-nitride buffer layer
III-nitride drift layer
III-nitride epitaxial buffer layer
III-nitride epitaxial drift layer
III-nitride epitaxial layer (JFET buffer/contact)
III-nitride drift layer (JFET)
III-nitride channel region
III-nitride source region
FIG. 3. Multiple top electrodes 1201 and 1202 are fabricated in the embodiment illustrated in
FIG. 6, the handle substrate, the bonding layer and the seed layer 102 have been removed as described above to expose the buffer layer 201 and a bottom …
FIG. 7, a device substrate 5 1001 (also referred to as an electrical and thermal substrate because of the properties discussed below) is joined to the bottom …
FIG. 10 is a vertical junction field effect transistor (JFET), which can be fabricated using techniques discussed in more detail in U.S. Patent Application No. …
FIG. 11, this is not required by the present invention and PNP designs can be utilized as well. Doping and thickness of the various layers of 10 the BJT are …
FIG. 12. The structure is then flip-chip bonded to substrate 1220 using bonds 1210. Thus, flip-chip bonding can be 20 used after the formation of the functional …
distance from first electrode structure to III-nitride drift layer | ≤ 10 µm | — |
oxygen concentration in III-nitride epitaxial layer and drift layer | ≤ 200000000 cm⁻³ | — |
silicon concentration in III-nitride epitaxial layer | ≥ 1000000000000000000 cm⁻³ | III-nitride epitaxial layer (JFET buffer/contact) |
GaN seed layer
GaN
n-type GaN-based seed material
III-nitride buffer layer
III-nitride drift layer
III-nitride epitaxial buffer layer
III-nitride epitaxial drift layer
III-nitride epitaxial layer (JFET buffer/contact)
III-nitride drift layer (JFET)
III-nitride channel region
III-nitride source region
FIG. 3. Multiple top electrodes 1201 and 1202 are fabricated in the embodiment illustrated in
FIG. 6, the handle substrate, the bonding layer and the seed layer 102 have been removed as described above to expose the buffer layer 201 and a bottom …
FIG. 7, a device substrate 5 1001 (also referred to as an electrical and thermal substrate because of the properties discussed below) is joined to the bottom …
FIG. 10 is a vertical junction field effect transistor (JFET), which can be fabricated using techniques discussed in more detail in U.S. Patent Application No. …
FIG. 11, this is not required by the present invention and PNP designs can be utilized as well. Doping and thickness of the various layers of 10 the BJT are …
FIG. 12. The structure is then flip-chip bonded to substrate 1220 using bonds 1210. Thus, flip-chip bonding can be 20 used after the formation of the functional …
distance from first electrode structure to III-nitride drift layer | ≤ 10 µm | — |
oxygen concentration in III-nitride epitaxial layer and drift layer | ≤ 200000000 cm⁻³ | — |
silicon concentration in III-nitride epitaxial layer | ≥ 1000000000000000000 cm⁻³ | III-nitride epitaxial layer (JFET buffer/contact) |
GaN seed layer
GaN
n-type GaN-based seed material
III-nitride buffer layer
III-nitride drift layer
III-nitride epitaxial buffer layer
III-nitride epitaxial drift layer
III-nitride epitaxial layer (JFET buffer/contact)
III-nitride drift layer (JFET)
III-nitride channel region
III-nitride source region
FIG. 3. Multiple top electrodes 1201 and 1202 are fabricated in the embodiment illustrated in
FIG. 6, the handle substrate, the bonding layer and the seed layer 102 have been removed as described above to expose the buffer layer 201 and a bottom …
FIG. 7, a device substrate 5 1001 (also referred to as an electrical and thermal substrate because of the properties discussed below) is joined to the bottom …
FIG. 10 is a vertical junction field effect transistor (JFET), which can be fabricated using techniques discussed in more detail in U.S. Patent Application No. …
FIG. 11, this is not required by the present invention and PNP designs can be utilized as well. Doping and thickness of the various layers of 10 the BJT are …
FIG. 12. The structure is then flip-chip bonded to substrate 1220 using bonds 1210. Thus, flip-chip bonding can be 20 used after the formation of the functional …
distance from first electrode structure to III-nitride drift layer | ≤ 10 µm | — |
oxygen concentration in III-nitride epitaxial layer and drift layer | ≤ 200000000 cm⁻³ | — |
silicon concentration in III-nitride epitaxial layer | ≥ 1000000000000000000 cm⁻³ | III-nitride epitaxial layer (JFET buffer/contact) |